clk: rockchip: Fix initialization of mux_pll_src_4plls_p

[people/arne_f/kernel.git] / drivers / clk / rockchip / clk-rk3228.c

diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 11e7f2d1c0548166f8b762582414b3337f363a6f..8d11d76e1db7c62219791e5af6e0b19dbd655590 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -144,7 +144,7 @@ PNAME(mux_usb480m_p)                = { "usb480m_phy", "xin24m" };
 PNAME(mux_hdmiphy_p)           = { "hdmiphy_phy", "xin24m" };
 PNAME(mux_aclk_cpu_src_p)      = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
 
-PNAME(mux_pll_src_4plls_p)     = { "cpll", "gpll", "hdmiphy" "usb480m" };
+PNAME(mux_pll_src_4plls_p)     = { "cpll", "gpll", "hdmiphy", "usb480m" };
 PNAME(mux_pll_src_3plls_p)     = { "cpll", "gpll", "hdmiphy" };
 PNAME(mux_pll_src_2plls_p)     = { "cpll", "gpll" };
 PNAME(mux_sclk_hdmi_cec_p)     = { "cpll", "gpll", "xin24m" };
@@ -163,8 +163,6 @@ PNAME(mux_i2s_out_p)                = { "i2s1_pre", "xin12m" };
 PNAME(mux_i2s2_p)              = { "i2s2_src", "i2s2_frac", "xin12m" };
 PNAME(mux_sclk_spdif_p)                = { "sclk_spdif_src", "spdif_frac", "xin12m" };
 
-PNAME(mux_aclk_gpu_pre_p)      = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" };
-
 PNAME(mux_uart0_p)             = { "uart0_src", "uart0_frac", "xin24m" };
 PNAME(mux_uart1_p)             = { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)             = { "uart2_src", "uart2_frac", "xin24m" };
@@ -387,7 +385,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
                        RK2928_CLKGATE_CON(2), 15, GFLAGS),
 
-       COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
+       COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
                        RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK2928_CLKGATE_CON(2), 11, GFLAGS),
 
@@ -475,16 +473,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
                        RK2928_CLKGATE_CON(2), 8, GFLAGS),
 
-       GATE(0, "cpll_gpu", "cpll", 0,
-                       RK2928_CLKGATE_CON(3), 13, GFLAGS),
-       GATE(0, "gpll_gpu", "gpll", 0,
-                       RK2928_CLKGATE_CON(3), 13, GFLAGS),
-       GATE(0, "hdmiphy_gpu", "hdmiphy", 0,
-                       RK2928_CLKGATE_CON(3), 13, GFLAGS),
-       GATE(0, "usb480m_gpu", "usb480m", 0,
+       COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0,
+                       RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS,
                        RK2928_CLKGATE_CON(3), 13, GFLAGS),
-       COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0,
-                       RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS),
 
        COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
                        RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
@@ -589,8 +580,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
        GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
 
        /* PD_GPU */
-       GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
-       GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
+       GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
+       GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
 
        /* PD_BUS */
        GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),