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MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
authorThomas Bogendoerfer <tsbogend@alpha.franken.de>
Mon, 14 Sep 2020 16:05:00 +0000 (18:05 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 23 Sep 2020 08:46:35 +0000 (10:46 +0200)
commit38eefb1964388f93644b35ec77000c5fbecca9cc
tree5621cb3cd19e7c8eb4ba28f7597e5ad51cf91a76tree | snapshot
parentf3440c029e471962719de3cbd771933e2165b338commit | diff
MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT

[ Upstream commit 564c836fd945a94b5dd46597d6b7adb464092650 ]

Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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