[people/ms/linux.git] / arch / mips / kernel / irq_cpu.c

/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
 *
 * Copyright (C) 2001 Ralf Baechle
 * Copyright (C) 2005  MIPS Technologies, Inc.	All rights reserved.
 *	Author: Maciej W. Rozycki <macro@mips.com>
 *
 * This file define the irq handler for MIPS CPU interrupts.
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/*
 * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
 * device).  The first two are software interrupts which we don't really
 * use or support.  The last one is usually the CPU timer interrupt if
 * counter register is present or, for CPUs with an external FPU, by
 * convention it's the FPU exception interrupt.
 *
 * Don't even think about using this on SMP.  You have been warned.
 *
 * This file exports one global function:
 *	void mips_cpu_irq_init(void);
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>

#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>

static inline void unmask_mips_irq(struct irq_data *d)
{
	set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
	irq_enable_hazard();
}

static inline void mask_mips_irq(struct irq_data *d)
{
	clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
	irq_disable_hazard();
}

static struct irq_chip mips_cpu_irq_controller = {
	.name		= "MIPS",
	.irq_ack	= mask_mips_irq,
	.irq_mask	= mask_mips_irq,
	.irq_mask_ack	= mask_mips_irq,
	.irq_unmask	= unmask_mips_irq,
	.irq_eoi	= unmask_mips_irq,
	.irq_disable	= mask_mips_irq,
	.irq_enable	= unmask_mips_irq,
};

/*
 * Basically the same as above but taking care of all the MT stuff
 */

static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
{
	unsigned int vpflags = dvpe();

	clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
	evpe(vpflags);
	unmask_mips_irq(d);
	return 0;
}

/*
 * While we ack the interrupt interrupts are disabled and thus we don't need
 * to deal with concurrency issues.  Same for mips_cpu_irq_end.
 */
static void mips_mt_cpu_irq_ack(struct irq_data *d)
{
	unsigned int vpflags = dvpe();
	clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
	evpe(vpflags);
	mask_mips_irq(d);
}

static struct irq_chip mips_mt_cpu_irq_controller = {
	.name		= "MIPS",
	.irq_startup	= mips_mt_cpu_irq_startup,
	.irq_ack	= mips_mt_cpu_irq_ack,
	.irq_mask	= mask_mips_irq,
	.irq_mask_ack	= mips_mt_cpu_irq_ack,
	.irq_unmask	= unmask_mips_irq,
	.irq_eoi	= unmask_mips_irq,
	.irq_disable	= mask_mips_irq,
	.irq_enable	= unmask_mips_irq,
};

void __init mips_cpu_irq_init(void)
{
	int irq_base = MIPS_CPU_IRQ_BASE;
	int i;

	/* Mask interrupts. */
	clear_c0_status(ST0_IM);
	clear_c0_cause(CAUSEF_IP);

	/* Software interrupts are used for MT/CMT IPI */
	for (i = irq_base; i < irq_base + 2; i++)
		irq_set_chip_and_handler(i, cpu_has_mipsmt ?
					 &mips_mt_cpu_irq_controller :
					 &mips_cpu_irq_controller,
					 handle_percpu_irq);

	for (i = irq_base + 2; i < irq_base + 8; i++)
		irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
					 handle_percpu_irq);
}

#ifdef CONFIG_IRQ_DOMAIN
static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
			     irq_hw_number_t hw)
{
	static struct irq_chip *chip;

	if (hw < 2 && cpu_has_mipsmt) {
		/* Software interrupts are used for MT/CMT IPI */
		chip = &mips_mt_cpu_irq_controller;
	} else {
		chip = &mips_cpu_irq_controller;
	}

	irq_set_chip_and_handler(irq, chip, handle_percpu_irq);

	return 0;
}

static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
	.map = mips_cpu_intc_map,
	.xlate = irq_domain_xlate_onecell,
};

int __init mips_cpu_intc_init(struct device_node *of_node,
			      struct device_node *parent)
{
	struct irq_domain *domain;

	/* Mask interrupts. */
	clear_c0_status(ST0_IM);
	clear_c0_cause(CAUSEF_IP);

	domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
				       &mips_cpu_intc_irq_domain_ops, NULL);
	if (!domain)
		panic("Failed to add irqdomain for MIPS CPU\n");

	return 0;
}
#endif /* CONFIG_IRQ_DOMAIN */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright 2001 MontaVista Software Inc.
	3	* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
	4	*
	5	* Copyright (C) 2001 Ralf Baechle
70342287 RB	6	* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
70342287 RB	7	* Author: Maciej W. Rozycki <macro@mips.com>
1da177e4 LT	8	*
	9	* This file define the irq handler for MIPS CPU interrupts.
	10	*
70342287 RB	11	* This program is free software; you can redistribute it and/or modify it
70342287 RB	12	* under the terms of the GNU General Public License as published by the
1da177e4 LT	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
	15	*/
	16
	17	/*
	18	* Almost all MIPS CPUs define 8 interrupt sources. They are typically
	19	* level triggered (i.e., cannot be cleared from CPU; must be cleared from
	20	* device). The first two are software interrupts which we don't really
	21	* use or support. The last one is usually the CPU timer interrupt if
	22	* counter register is present or, for CPUs with an external FPU, by
	23	* convention it's the FPU exception interrupt.
	24	*
	25	* Don't even think about using this on SMP. You have been warned.
	26	*
	27	* This file exports one global function:
97dcb82d	28	* void mips_cpu_irq_init(void);
1da177e4 LT	29	*/
	30	#include <linux/init.h>
	31	#include <linux/interrupt.h>
	32	#include <linux/kernel.h>
ca4d3e67	33	#include <linux/irq.h>
0916b469	34	#include <linux/irqdomain.h>
1da177e4 LT	35
	36	#include <asm/irq_cpu.h>
	37	#include <asm/mipsregs.h>
d03d0a57	38	#include <asm/mipsmtregs.h>
1da177e4	39
a93951c4	40	static inline void unmask_mips_irq(struct irq_data *d)
1da177e4	41	{
a93951c4	42	set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
569f75bd	43	irq_enable_hazard();
1da177e4 LT	44	}
1da177e4 LT	45
a93951c4	46	static inline void mask_mips_irq(struct irq_data *d)
1da177e4	47	{
a93951c4	48	clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
569f75bd	49	irq_disable_hazard();
1da177e4 LT	50	}
1da177e4 LT	51
94dee171	52	static struct irq_chip mips_cpu_irq_controller = {
70d21cde	53	.name = "MIPS",
a93951c4 TG	54	.irq_ack = mask_mips_irq,
	55	.irq_mask = mask_mips_irq,
	56	.irq_mask_ack = mask_mips_irq,
	57	.irq_unmask = unmask_mips_irq,
	58	.irq_eoi = unmask_mips_irq,
290deda9 FF	59	.irq_disable = mask_mips_irq,
290deda9 FF	60	.irq_enable = unmask_mips_irq,
1da177e4 LT	61	};
1da177e4 LT	62
d03d0a57 RB	63	/*
	64	* Basically the same as above but taking care of all the MT stuff
	65	*/
	66
a93951c4	67	static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
d03d0a57 RB	68	{
	69	unsigned int vpflags = dvpe();
	70
a93951c4	71	clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
d03d0a57	72	evpe(vpflags);
a93951c4	73	unmask_mips_irq(d);
d03d0a57 RB	74	return 0;
	75	}
	76
d03d0a57 RB	77	/*
	78	* While we ack the interrupt interrupts are disabled and thus we don't need
	79	* to deal with concurrency issues. Same for mips_cpu_irq_end.
	80	*/
a93951c4	81	static void mips_mt_cpu_irq_ack(struct irq_data *d)
d03d0a57 RB	82	{
d03d0a57 RB	83	unsigned int vpflags = dvpe();
a93951c4	84	clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
d03d0a57	85	evpe(vpflags);
a93951c4	86	mask_mips_irq(d);
d03d0a57 RB	87	}
d03d0a57 RB	88
94dee171	89	static struct irq_chip mips_mt_cpu_irq_controller = {
70d21cde	90	.name = "MIPS",
a93951c4 TG	91	.irq_startup = mips_mt_cpu_irq_startup,
	92	.irq_ack = mips_mt_cpu_irq_ack,
	93	.irq_mask = mask_mips_irq,
	94	.irq_mask_ack = mips_mt_cpu_irq_ack,
	95	.irq_unmask = unmask_mips_irq,
	96	.irq_eoi = unmask_mips_irq,
290deda9 FF	97	.irq_disable = mask_mips_irq,
290deda9 FF	98	.irq_enable = unmask_mips_irq,
d03d0a57	99	};
1da177e4	100
97dcb82d	101	void __init mips_cpu_irq_init(void)
1da177e4	102	{
97dcb82d	103	int irq_base = MIPS_CPU_IRQ_BASE;
1da177e4 LT	104	int i;
1da177e4 LT	105
925ddb04 MR	106	/* Mask interrupts. */
	107	clear_c0_status(ST0_IM);
	108	clear_c0_cause(CAUSEF_IP);
	109
273f2d7e KC	110	/* Software interrupts are used for MT/CMT IPI */
	111	for (i = irq_base; i < irq_base + 2; i++)
	112	irq_set_chip_and_handler(i, cpu_has_mipsmt ?
	113	&mips_mt_cpu_irq_controller :
	114	&mips_cpu_irq_controller,
	115	handle_percpu_irq);
1603b5ac AN	116
1603b5ac AN	117	for (i = irq_base + 2; i < irq_base + 8; i++)
e4ec7989	118	irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
30e748a5	119	handle_percpu_irq);
1da177e4	120	}
0916b469 GJ	121
	122	#ifdef CONFIG_IRQ_DOMAIN
	123	static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
	124	irq_hw_number_t hw)
	125	{
	126	static struct irq_chip *chip;
	127
	128	if (hw < 2 && cpu_has_mipsmt) {
	129	/* Software interrupts are used for MT/CMT IPI */
	130	chip = &mips_mt_cpu_irq_controller;
	131	} else {
	132	chip = &mips_cpu_irq_controller;
	133	}
	134
	135	irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
	136
	137	return 0;
	138	}
	139
	140	static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
	141	.map = mips_cpu_intc_map,
	142	.xlate = irq_domain_xlate_onecell,
	143	};
	144
	145	int __init mips_cpu_intc_init(struct device_node *of_node,
	146	struct device_node *parent)
	147	{
	148	struct irq_domain *domain;
	149
	150	/* Mask interrupts. */
	151	clear_c0_status(ST0_IM);
	152	clear_c0_cause(CAUSEF_IP);
	153
	154	domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
	155	&mips_cpu_intc_irq_domain_ops, NULL);
	156	if (!domain)
	157	panic("Failed to add irqdomain for MIPS CPU\n");
	158
	159	return 0;
	160	}
	161	#endif /* CONFIG_IRQ_DOMAIN */