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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[people/ms/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/amdgpu_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swiotlb.h>
42#include <linux/swap.h>
43#include <linux/pagemap.h>
44#include <linux/debugfs.h>
45#include "amdgpu.h"
46#include "bif/bif_4_1_d.h"
47
48#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
51static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
52
53static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
54{
55 struct amdgpu_mman *mman;
56 struct amdgpu_device *adev;
57
58 mman = container_of(bdev, struct amdgpu_mman, bdev);
59 adev = container_of(mman, struct amdgpu_device, mman);
60 return adev;
61}
62
63
64/*
65 * Global memory.
66 */
67static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
68{
69 return ttm_mem_global_init(ref->object);
70}
71
72static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
73{
74 ttm_mem_global_release(ref->object);
75}
76
77static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
78{
79 struct drm_global_reference *global_ref;
80 int r;
81
82 adev->mman.mem_global_referenced = false;
83 global_ref = &adev->mman.mem_global_ref;
84 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
85 global_ref->size = sizeof(struct ttm_mem_global);
86 global_ref->init = &amdgpu_ttm_mem_global_init;
87 global_ref->release = &amdgpu_ttm_mem_global_release;
88 r = drm_global_item_ref(global_ref);
89 if (r != 0) {
90 DRM_ERROR("Failed setting up TTM memory accounting "
91 "subsystem.\n");
92 return r;
93 }
94
95 adev->mman.bo_global_ref.mem_glob =
96 adev->mman.mem_global_ref.object;
97 global_ref = &adev->mman.bo_global_ref.ref;
98 global_ref->global_type = DRM_GLOBAL_TTM_BO;
99 global_ref->size = sizeof(struct ttm_bo_global);
100 global_ref->init = &ttm_bo_global_init;
101 global_ref->release = &ttm_bo_global_release;
102 r = drm_global_item_ref(global_ref);
103 if (r != 0) {
104 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
105 drm_global_item_unref(&adev->mman.mem_global_ref);
106 return r;
107 }
108
109 adev->mman.mem_global_referenced = true;
110 return 0;
111}
112
113static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
114{
115 if (adev->mman.mem_global_referenced) {
116 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
117 drm_global_item_unref(&adev->mman.mem_global_ref);
118 adev->mman.mem_global_referenced = false;
119 }
120}
121
122static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
123{
124 return 0;
125}
126
127static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
128 struct ttm_mem_type_manager *man)
129{
130 struct amdgpu_device *adev;
131
132 adev = amdgpu_get_adev(bdev);
133
134 switch (type) {
135 case TTM_PL_SYSTEM:
136 /* System memory */
137 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
138 man->available_caching = TTM_PL_MASK_CACHING;
139 man->default_caching = TTM_PL_FLAG_CACHED;
140 break;
141 case TTM_PL_TT:
142 man->func = &ttm_bo_manager_func;
143 man->gpu_offset = adev->mc.gtt_start;
144 man->available_caching = TTM_PL_MASK_CACHING;
145 man->default_caching = TTM_PL_FLAG_CACHED;
146 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
147 break;
148 case TTM_PL_VRAM:
149 /* "On-card" video ram */
150 man->func = &ttm_bo_manager_func;
151 man->gpu_offset = adev->mc.vram_start;
152 man->flags = TTM_MEMTYPE_FLAG_FIXED |
153 TTM_MEMTYPE_FLAG_MAPPABLE;
154 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
155 man->default_caching = TTM_PL_FLAG_WC;
156 break;
157 case AMDGPU_PL_GDS:
158 case AMDGPU_PL_GWS:
159 case AMDGPU_PL_OA:
160 /* On-chip GDS memory*/
161 man->func = &ttm_bo_manager_func;
162 man->gpu_offset = 0;
163 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
164 man->available_caching = TTM_PL_FLAG_UNCACHED;
165 man->default_caching = TTM_PL_FLAG_UNCACHED;
166 break;
167 default:
168 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
169 return -EINVAL;
170 }
171 return 0;
172}
173
174static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
175 struct ttm_placement *placement)
176{
177 struct amdgpu_bo *rbo;
178 static struct ttm_place placements = {
179 .fpfn = 0,
180 .lpfn = 0,
181 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
182 };
183
184 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
185 placement->placement = &placements;
186 placement->busy_placement = &placements;
187 placement->num_placement = 1;
188 placement->num_busy_placement = 1;
189 return;
190 }
191 rbo = container_of(bo, struct amdgpu_bo, tbo);
192 switch (bo->mem.mem_type) {
193 case TTM_PL_VRAM:
194 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
195 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
196 else
197 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
198 break;
199 case TTM_PL_TT:
200 default:
201 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
202 }
203 *placement = rbo->placement;
204}
205
206static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
207{
208 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
209
210 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
211}
212
213static void amdgpu_move_null(struct ttm_buffer_object *bo,
214 struct ttm_mem_reg *new_mem)
215{
216 struct ttm_mem_reg *old_mem = &bo->mem;
217
218 BUG_ON(old_mem->mm_node != NULL);
219 *old_mem = *new_mem;
220 new_mem->mm_node = NULL;
221}
222
223static int amdgpu_move_blit(struct ttm_buffer_object *bo,
224 bool evict, bool no_wait_gpu,
225 struct ttm_mem_reg *new_mem,
226 struct ttm_mem_reg *old_mem)
227{
228 struct amdgpu_device *adev;
229 struct amdgpu_ring *ring;
230 uint64_t old_start, new_start;
c7ae72c0 231 struct fence *fence;
d38ceaf9
AD		 232 int r;
233
234 adev = amdgpu_get_adev(bo->bdev);
235 ring = adev->mman.buffer_funcs_ring;
236 old_start = old_mem->start << PAGE_SHIFT;
237 new_start = new_mem->start << PAGE_SHIFT;
238
239 switch (old_mem->mem_type) {
240 case TTM_PL_VRAM:
241 old_start += adev->mc.vram_start;
242 break;
243 case TTM_PL_TT:
244 old_start += adev->mc.gtt_start;
245 break;
246 default:
247 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
248 return -EINVAL;
249 }
250 switch (new_mem->mem_type) {
251 case TTM_PL_VRAM:
252 new_start += adev->mc.vram_start;
253 break;
254 case TTM_PL_TT:
255 new_start += adev->mc.gtt_start;
256 break;
257 default:
258 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
259 return -EINVAL;
260 }
261 if (!ring->ready) {
262 DRM_ERROR("Trying to move memory with ring turned off.\n");
263 return -EINVAL;
264 }
265
266 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
267
268 r = amdgpu_copy_buffer(ring, old_start, new_start,
269 new_mem->num_pages * PAGE_SIZE, /* bytes */
270 bo->resv, &fence);
271 /* FIXME: handle copy error */
c7ae72c0 272 r = ttm_bo_move_accel_cleanup(bo, fence,
d38ceaf9 273 evict, no_wait_gpu, new_mem);
c7ae72c0 274 fence_put(fence);
d38ceaf9
AD		 275 return r;
276}
277
278static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
279 bool evict, bool interruptible,
280 bool no_wait_gpu,
281 struct ttm_mem_reg *new_mem)
282{
283 struct amdgpu_device *adev;
284 struct ttm_mem_reg *old_mem = &bo->mem;
285 struct ttm_mem_reg tmp_mem;
286 struct ttm_place placements;
287 struct ttm_placement placement;
288 int r;
289
290 adev = amdgpu_get_adev(bo->bdev);
291 tmp_mem = *new_mem;
292 tmp_mem.mm_node = NULL;
293 placement.num_placement = 1;
294 placement.placement = &placements;
295 placement.num_busy_placement = 1;
296 placement.busy_placement = &placements;
297 placements.fpfn = 0;
298 placements.lpfn = 0;
299 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
300 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
301 interruptible, no_wait_gpu);
302 if (unlikely(r)) {
303 return r;
304 }
305
306 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
307 if (unlikely(r)) {
308 goto out_cleanup;
309 }
310
311 r = ttm_tt_bind(bo->ttm, &tmp_mem);
312 if (unlikely(r)) {
313 goto out_cleanup;
314 }
315 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
316 if (unlikely(r)) {
317 goto out_cleanup;
318 }
319 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
320out_cleanup:
321 ttm_bo_mem_put(bo, &tmp_mem);
322 return r;
323}
324
325static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
326 bool evict, bool interruptible,
327 bool no_wait_gpu,
328 struct ttm_mem_reg *new_mem)
329{
330 struct amdgpu_device *adev;
331 struct ttm_mem_reg *old_mem = &bo->mem;
332 struct ttm_mem_reg tmp_mem;
333 struct ttm_placement placement;
334 struct ttm_place placements;
335 int r;
336
337 adev = amdgpu_get_adev(bo->bdev);
338 tmp_mem = *new_mem;
339 tmp_mem.mm_node = NULL;
340 placement.num_placement = 1;
341 placement.placement = &placements;
342 placement.num_busy_placement = 1;
343 placement.busy_placement = &placements;
344 placements.fpfn = 0;
345 placements.lpfn = 0;
346 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
347 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
348 interruptible, no_wait_gpu);
349 if (unlikely(r)) {
350 return r;
351 }
352 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
353 if (unlikely(r)) {
354 goto out_cleanup;
355 }
356 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
357 if (unlikely(r)) {
358 goto out_cleanup;
359 }
360out_cleanup:
361 ttm_bo_mem_put(bo, &tmp_mem);
362 return r;
363}
364
365static int amdgpu_bo_move(struct ttm_buffer_object *bo,
366 bool evict, bool interruptible,
367 bool no_wait_gpu,
368 struct ttm_mem_reg *new_mem)
369{
370 struct amdgpu_device *adev;
371 struct ttm_mem_reg *old_mem = &bo->mem;
372 int r;
373
374 adev = amdgpu_get_adev(bo->bdev);
375 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
376 amdgpu_move_null(bo, new_mem);
377 return 0;
378 }
379 if ((old_mem->mem_type == TTM_PL_TT &&
380 new_mem->mem_type == TTM_PL_SYSTEM) ||
381 (old_mem->mem_type == TTM_PL_SYSTEM &&
382 new_mem->mem_type == TTM_PL_TT)) {
383 /* bind is enough */
384 amdgpu_move_null(bo, new_mem);
385 return 0;
386 }
387 if (adev->mman.buffer_funcs == NULL ||
388 adev->mman.buffer_funcs_ring == NULL ||
389 !adev->mman.buffer_funcs_ring->ready) {
390 /* use memcpy */
391 goto memcpy;
392 }
393
394 if (old_mem->mem_type == TTM_PL_VRAM &&
395 new_mem->mem_type == TTM_PL_SYSTEM) {
396 r = amdgpu_move_vram_ram(bo, evict, interruptible,
397 no_wait_gpu, new_mem);
398 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
399 new_mem->mem_type == TTM_PL_VRAM) {
400 r = amdgpu_move_ram_vram(bo, evict, interruptible,
401 no_wait_gpu, new_mem);
402 } else {
403 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
404 }
405
406 if (r) {
407memcpy:
408 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
409 if (r) {
410 return r;
411 }
412 }
413
414 /* update statistics */
415 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
416 return 0;
417}
418
419static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
420{
421 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
422 struct amdgpu_device *adev = amdgpu_get_adev(bdev);
423
424 mem->bus.addr = NULL;
425 mem->bus.offset = 0;
426 mem->bus.size = mem->num_pages << PAGE_SHIFT;
427 mem->bus.base = 0;
428 mem->bus.is_iomem = false;
429 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
430 return -EINVAL;
431 switch (mem->mem_type) {
432 case TTM_PL_SYSTEM:
433 /* system memory */
434 return 0;
435 case TTM_PL_TT:
436 break;
437 case TTM_PL_VRAM:
438 mem->bus.offset = mem->start << PAGE_SHIFT;
439 /* check if it's visible */
440 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
441 return -EINVAL;
442 mem->bus.base = adev->mc.aper_base;
443 mem->bus.is_iomem = true;
444#ifdef __alpha__
445 /*
446 * Alpha: use bus.addr to hold the ioremap() return,
447 * so we can modify bus.base below.
448 */
449 if (mem->placement & TTM_PL_FLAG_WC)
450 mem->bus.addr =
451 ioremap_wc(mem->bus.base + mem->bus.offset,
452 mem->bus.size);
453 else
454 mem->bus.addr =
455 ioremap_nocache(mem->bus.base + mem->bus.offset,
456 mem->bus.size);
457
458 /*
459 * Alpha: Use just the bus offset plus
460 * the hose/domain memory base for bus.base.
461 * It then can be used to build PTEs for VRAM
462 * access, as done in ttm_bo_vm_fault().
463 */
464 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
465 adev->ddev->hose->dense_mem_base;
466#endif
467 break;
468 default:
469 return -EINVAL;
470 }
471 return 0;
472}
473
474static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
475{
476}
477
478/*
479 * TTM backend functions.
480 */
481struct amdgpu_ttm_tt {
482 struct ttm_dma_tt ttm;
483 struct amdgpu_device *adev;
484 u64 offset;
485 uint64_t userptr;
486 struct mm_struct *usermm;
487 uint32_t userflags;
488};
489
490/* prepare the sg table with the user pages */
491static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
492{
493 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
494 struct amdgpu_ttm_tt *gtt = (void *)ttm;
495 unsigned pinned = 0, nents;
496 int r;
497
498 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
499 enum dma_data_direction direction = write ?
500 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
501
502 if (current->mm != gtt->usermm)
503 return -EPERM;
504
505 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
506 /* check that we only pin down anonymous memory
507 to prevent problems with writeback */
508 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
509 struct vm_area_struct *vma;
510
511 vma = find_vma(gtt->usermm, gtt->userptr);
512 if (!vma || vma->vm_file || vma->vm_end < end)
513 return -EPERM;
514 }
515
516 do {
517 unsigned num_pages = ttm->num_pages - pinned;
518 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
519 struct page **pages = ttm->pages + pinned;
520
521 r = get_user_pages(current, current->mm, userptr, num_pages,
522 write, 0, pages, NULL);
523 if (r < 0)
524 goto release_pages;
525
526 pinned += r;
527
528 } while (pinned < ttm->num_pages);
529
530 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
531 ttm->num_pages << PAGE_SHIFT,
532 GFP_KERNEL);
533 if (r)
534 goto release_sg;
535
536 r = -ENOMEM;
537 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
538 if (nents != ttm->sg->nents)
539 goto release_sg;
540
541 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
542 gtt->ttm.dma_address, ttm->num_pages);
543
544 return 0;
545
546release_sg:
547 kfree(ttm->sg);
548
549release_pages:
550 release_pages(ttm->pages, pinned, 0);
551 return r;
552}
553
554static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
555{
556 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
557 struct amdgpu_ttm_tt *gtt = (void *)ttm;
dd08fae1 558 struct sg_page_iter sg_iter;
d38ceaf9
AD		 559
560 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
561 enum dma_data_direction direction = write ?
562 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
563
564 /* double check that we don't free the table twice */
565 if (!ttm->sg->sgl)
566 return;
567
568 /* free the sg table and pages again */
569 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
570
dd08fae1 571 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
572 struct page *page = sg_page_iter_page(&sg_iter);
d38ceaf9
AD		 573 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
574 set_page_dirty(page);
575
576 mark_page_accessed(page);
577 page_cache_release(page);
578 }
579
580 sg_free_table(ttm->sg);
581}
582
583static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
584 struct ttm_mem_reg *bo_mem)
585{
586 struct amdgpu_ttm_tt *gtt = (void*)ttm;
587 uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
588 int r;
589
e2f784fa
CZ		 590 if (gtt->userptr) {
591 r = amdgpu_ttm_tt_pin_userptr(ttm);
592 if (r) {
593 DRM_ERROR("failed to pin userptr\n");
594 return r;
595 }
596 }
d38ceaf9
AD		 597 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
598 if (!ttm->num_pages) {
599 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
600 ttm->num_pages, bo_mem, ttm);
601 }
602
603 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
604 bo_mem->mem_type == AMDGPU_PL_GWS ||
605 bo_mem->mem_type == AMDGPU_PL_OA)
606 return -EINVAL;
607
608 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
609 ttm->pages, gtt->ttm.dma_address, flags);
610
611 if (r) {
612 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
613 ttm->num_pages, (unsigned)gtt->offset);
614 return r;
615 }
616 return 0;
617}
618
619static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
620{
621 struct amdgpu_ttm_tt *gtt = (void *)ttm;
622
623 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
624 if (gtt->adev->gart.ready)
625 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
626
627 if (gtt->userptr)
628 amdgpu_ttm_tt_unpin_userptr(ttm);
629
630 return 0;
631}
632
633static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
634{
635 struct amdgpu_ttm_tt *gtt = (void *)ttm;
636
637 ttm_dma_tt_fini(&gtt->ttm);
638 kfree(gtt);
639}
640
641static struct ttm_backend_func amdgpu_backend_func = {
642 .bind = &amdgpu_ttm_backend_bind,
643 .unbind = &amdgpu_ttm_backend_unbind,
644 .destroy = &amdgpu_ttm_backend_destroy,
645};
646
647static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
648 unsigned long size, uint32_t page_flags,
649 struct page *dummy_read_page)
650{
651 struct amdgpu_device *adev;
652 struct amdgpu_ttm_tt *gtt;
653
654 adev = amdgpu_get_adev(bdev);
655
656 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
657 if (gtt == NULL) {
658 return NULL;
659 }
660 gtt->ttm.ttm.func = &amdgpu_backend_func;
661 gtt->adev = adev;
662 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
663 kfree(gtt);
664 return NULL;
665 }
666 return &gtt->ttm.ttm;
667}
668
669static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
670{
671 struct amdgpu_device *adev;
672 struct amdgpu_ttm_tt *gtt = (void *)ttm;
673 unsigned i;
674 int r;
675 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
676
677 if (ttm->state != tt_unpopulated)
678 return 0;
679
680 if (gtt && gtt->userptr) {
5f0b34cc 681 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
d38ceaf9
AD		 682 if (!ttm->sg)
683 return -ENOMEM;
684
685 ttm->page_flags |= TTM_PAGE_FLAG_SG;
686 ttm->state = tt_unbound;
687 return 0;
688 }
689
690 if (slave && ttm->sg) {
691 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
692 gtt->ttm.dma_address, ttm->num_pages);
693 ttm->state = tt_unbound;
694 return 0;
695 }
696
697 adev = amdgpu_get_adev(ttm->bdev);
698
699#ifdef CONFIG_SWIOTLB
700 if (swiotlb_nr_tbl()) {
701 return ttm_dma_populate(&gtt->ttm, adev->dev);
702 }
703#endif
704
705 r = ttm_pool_populate(ttm);
706 if (r) {
707 return r;
708 }
709
710 for (i = 0; i < ttm->num_pages; i++) {
711 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
712 0, PAGE_SIZE,
713 PCI_DMA_BIDIRECTIONAL);
714 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
715 while (--i) {
716 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
717 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
718 gtt->ttm.dma_address[i] = 0;
719 }
720 ttm_pool_unpopulate(ttm);
721 return -EFAULT;
722 }
723 }
724 return 0;
725}
726
727static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
728{
729 struct amdgpu_device *adev;
730 struct amdgpu_ttm_tt *gtt = (void *)ttm;
731 unsigned i;
732 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
733
734 if (gtt && gtt->userptr) {
735 kfree(ttm->sg);
736 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
737 return;
738 }
739
740 if (slave)
741 return;
742
743 adev = amdgpu_get_adev(ttm->bdev);
744
745#ifdef CONFIG_SWIOTLB
746 if (swiotlb_nr_tbl()) {
747 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
748 return;
749 }
750#endif
751
752 for (i = 0; i < ttm->num_pages; i++) {
753 if (gtt->ttm.dma_address[i]) {
754 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
755 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
756 }
757 }
758
759 ttm_pool_unpopulate(ttm);
760}
761
762int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
763 uint32_t flags)
764{
765 struct amdgpu_ttm_tt *gtt = (void *)ttm;
766
767 if (gtt == NULL)
768 return -EINVAL;
769
770 gtt->userptr = addr;
771 gtt->usermm = current->mm;
772 gtt->userflags = flags;
773 return 0;
774}
775
776bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm)
777{
778 struct amdgpu_ttm_tt *gtt = (void *)ttm;
779
780 if (gtt == NULL)
781 return false;
782
783 return !!gtt->userptr;
784}
785
786bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
787{
788 struct amdgpu_ttm_tt *gtt = (void *)ttm;
789
790 if (gtt == NULL)
791 return false;
792
793 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
794}
795
796uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
797 struct ttm_mem_reg *mem)
798{
799 uint32_t flags = 0;
800
801 if (mem && mem->mem_type != TTM_PL_SYSTEM)
802 flags |= AMDGPU_PTE_VALID;
803
6d99905a 804 if (mem && mem->mem_type == TTM_PL_TT) {
d38ceaf9
AD		 805 flags |= AMDGPU_PTE_SYSTEM;
806
6d99905a
CK		 807 if (ttm->caching_state == tt_cached)
808 flags |= AMDGPU_PTE_SNOOPED;
809 }
d38ceaf9
AD		 810
811 if (adev->asic_type >= CHIP_TOPAZ)
812 flags |= AMDGPU_PTE_EXECUTABLE;
813
814 flags |= AMDGPU_PTE_READABLE;
815
816 if (!amdgpu_ttm_tt_is_readonly(ttm))
817 flags |= AMDGPU_PTE_WRITEABLE;
818
819 return flags;
820}
821
822static struct ttm_bo_driver amdgpu_bo_driver = {
823 .ttm_tt_create = &amdgpu_ttm_tt_create,
824 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
825 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
826 .invalidate_caches = &amdgpu_invalidate_caches,
827 .init_mem_type = &amdgpu_init_mem_type,
828 .evict_flags = &amdgpu_evict_flags,
829 .move = &amdgpu_bo_move,
830 .verify_access = &amdgpu_verify_access,
831 .move_notify = &amdgpu_bo_move_notify,
832 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
833 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
834 .io_mem_free = &amdgpu_ttm_io_mem_free,
835};
836
837int amdgpu_ttm_init(struct amdgpu_device *adev)
838{
839 int r;
840
841 r = amdgpu_ttm_global_init(adev);
842 if (r) {
843 return r;
844 }
845 /* No others user of address space so set it to 0 */
846 r = ttm_bo_device_init(&adev->mman.bdev,
847 adev->mman.bo_global_ref.ref.object,
848 &amdgpu_bo_driver,
849 adev->ddev->anon_inode->i_mapping,
850 DRM_FILE_PAGE_OFFSET,
851 adev->need_dma32);
852 if (r) {
853 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
854 return r;
855 }
856 adev->mman.initialized = true;
857 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
858 adev->mc.real_vram_size >> PAGE_SHIFT);
859 if (r) {
860 DRM_ERROR("Failed initializing VRAM heap.\n");
861 return r;
862 }
863 /* Change the size here instead of the init above so only lpfn is affected */
864 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
865
866 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
857d913d
AD		 867 AMDGPU_GEM_DOMAIN_VRAM,
868 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 869 NULL, NULL, &adev->stollen_vga_memory);
d38ceaf9
AD		 870 if (r) {
871 return r;
872 }
873 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
874 if (r)
875 return r;
876 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
877 amdgpu_bo_unreserve(adev->stollen_vga_memory);
878 if (r) {
879 amdgpu_bo_unref(&adev->stollen_vga_memory);
880 return r;
881 }
882 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
883 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
884 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
885 adev->mc.gtt_size >> PAGE_SHIFT);
886 if (r) {
887 DRM_ERROR("Failed initializing GTT heap.\n");
888 return r;
889 }
890 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
891 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
892
893 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
894 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
895 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
896 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
897 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
898 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
899 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
900 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
901 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
902 /* GDS Memory */
903 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
904 adev->gds.mem.total_size >> PAGE_SHIFT);
905 if (r) {
906 DRM_ERROR("Failed initializing GDS heap.\n");
907 return r;
908 }
909
910 /* GWS */
911 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
912 adev->gds.gws.total_size >> PAGE_SHIFT);
913 if (r) {
914 DRM_ERROR("Failed initializing gws heap.\n");
915 return r;
916 }
917
918 /* OA */
919 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
920 adev->gds.oa.total_size >> PAGE_SHIFT);
921 if (r) {
922 DRM_ERROR("Failed initializing oa heap.\n");
923 return r;
924 }
925
926 r = amdgpu_ttm_debugfs_init(adev);
927 if (r) {
928 DRM_ERROR("Failed to init debugfs\n");
929 return r;
930 }
931 return 0;
932}
933
934void amdgpu_ttm_fini(struct amdgpu_device *adev)
935{
936 int r;
937
938 if (!adev->mman.initialized)
939 return;
940 amdgpu_ttm_debugfs_fini(adev);
941 if (adev->stollen_vga_memory) {
942 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
943 if (r == 0) {
944 amdgpu_bo_unpin(adev->stollen_vga_memory);
945 amdgpu_bo_unreserve(adev->stollen_vga_memory);
946 }
947 amdgpu_bo_unref(&adev->stollen_vga_memory);
948 }
949 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
950 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
951 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
952 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
953 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
954 ttm_bo_device_release(&adev->mman.bdev);
955 amdgpu_gart_fini(adev);
956 amdgpu_ttm_global_fini(adev);
957 adev->mman.initialized = false;
958 DRM_INFO("amdgpu: ttm finalized\n");
959}
960
961/* this should only be called at bootup or when userspace
962 * isn't running */
963void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
964{
965 struct ttm_mem_type_manager *man;
966
967 if (!adev->mman.initialized)
968 return;
969
970 man = &adev->mman.bdev.man[TTM_PL_VRAM];
971 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
972 man->size = size >> PAGE_SHIFT;
973}
974
d38ceaf9
AD		 975int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
976{
977 struct drm_file *file_priv;
978 struct amdgpu_device *adev;
d38ceaf9 979
e176fe17 980 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
d38ceaf9 981 return -EINVAL;
d38ceaf9
AD		 982
983 file_priv = filp->private_data;
984 adev = file_priv->minor->dev->dev_private;
e176fe17 985 if (adev == NULL)
d38ceaf9 986 return -EINVAL;
e176fe17
CK		 987
988 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
d38ceaf9
AD		 989}
990
991int amdgpu_copy_buffer(struct amdgpu_ring *ring,
992 uint64_t src_offset,
993 uint64_t dst_offset,
994 uint32_t byte_count,
995 struct reservation_object *resv,
c7ae72c0 996 struct fence **fence)
d38ceaf9
AD		 997{
998 struct amdgpu_device *adev = ring->adev;
d38ceaf9
AD		 999 uint32_t max_bytes;
1000 unsigned num_loops, num_dw;
c7ae72c0 1001 struct amdgpu_ib *ib;
d38ceaf9
AD		 1002 unsigned i;
1003 int r;
1004
d38ceaf9
AD		 1005 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1006 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1007 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1008
c7ae72c0
CZ		 1009 /* for IB padding */
1010 while (num_dw & 0x7)
1011 num_dw++;
1012
1013 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
1014 if (!ib)
1015 return -ENOMEM;
d38ceaf9 1016
c7ae72c0 1017 r = amdgpu_ib_get(ring, NULL, num_dw * 4, ib);
9066b0c3 1018 if (r) {
c7ae72c0 1019 kfree(ib);
9066b0c3
CZ		 1020 return r;
1021 }
1022
c7ae72c0
CZ		 1023 ib->length_dw = 0;
1024
1025 if (resv) {
1026 r = amdgpu_sync_resv(adev, &ib->sync, resv,
1027 AMDGPU_FENCE_OWNER_UNDEFINED);
1028 if (r) {
1029 DRM_ERROR("sync failed (%d).\n", r);
1030 goto error_free;
1031 }
d38ceaf9 1032 }
d38ceaf9
AD		 1033
1034 for (i = 0; i < num_loops; i++) {
1035 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1036
c7ae72c0 1037 amdgpu_emit_copy_buffer(adev, ib, src_offset, dst_offset,
d38ceaf9
AD		 1038 cur_size_in_bytes);
1039
1040 src_offset += cur_size_in_bytes;
1041 dst_offset += cur_size_in_bytes;
1042 byte_count -= cur_size_in_bytes;
1043 }
1044
c7ae72c0
CZ		 1045 amdgpu_vm_pad_ib(adev, ib);
1046 WARN_ON(ib->length_dw > num_dw);
1047 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
1048 &amdgpu_vm_free_job,
7a91d6cb 1049 AMDGPU_FENCE_OWNER_UNDEFINED,
c7ae72c0
CZ		 1050 fence);
1051 if (r)
1052 goto error_free;
d38ceaf9 1053
c7ae72c0
CZ		 1054 if (!amdgpu_enable_scheduler) {
1055 amdgpu_ib_free(adev, ib);
1056 kfree(ib);
1057 }
d38ceaf9 1058 return 0;
c7ae72c0
CZ		 1059error_free:
1060 amdgpu_ib_free(adev, ib);
1061 kfree(ib);
1062 return r;
d38ceaf9
AD		 1063}
1064
1065#if defined(CONFIG_DEBUG_FS)
1066
1067static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1068{
1069 struct drm_info_node *node = (struct drm_info_node *)m->private;
1070 unsigned ttm_pl = *(int *)node->info_ent->data;
1071 struct drm_device *dev = node->minor->dev;
1072 struct amdgpu_device *adev = dev->dev_private;
1073 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1074 int ret;
1075 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1076
1077 spin_lock(&glob->lru_lock);
1078 ret = drm_mm_dump_table(m, mm);
1079 spin_unlock(&glob->lru_lock);
a2ef8a97 1080 if (ttm_pl == TTM_PL_VRAM)
e1b35f61 1081 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
a2ef8a97 1082 adev->mman.bdev.man[ttm_pl].size,
e1b35f61
AB		 1083 (u64)atomic64_read(&adev->vram_usage) >> 20,
1084 (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
d38ceaf9
AD		 1085 return ret;
1086}
1087
1088static int ttm_pl_vram = TTM_PL_VRAM;
1089static int ttm_pl_tt = TTM_PL_TT;
1090
1091static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1092 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1093 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1094 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1095#ifdef CONFIG_SWIOTLB
1096 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1097#endif
1098};
1099
1100static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1101 size_t size, loff_t *pos)
1102{
1103 struct amdgpu_device *adev = f->f_inode->i_private;
1104 ssize_t result = 0;
1105 int r;
1106
1107 if (size & 0x3 || *pos & 0x3)
1108 return -EINVAL;
1109
1110 while (size) {
1111 unsigned long flags;
1112 uint32_t value;
1113
1114 if (*pos >= adev->mc.mc_vram_size)
1115 return result;
1116
1117 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1118 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1119 WREG32(mmMM_INDEX_HI, *pos >> 31);
1120 value = RREG32(mmMM_DATA);
1121 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1122
1123 r = put_user(value, (uint32_t *)buf);
1124 if (r)
1125 return r;
1126
1127 result += 4;
1128 buf += 4;
1129 *pos += 4;
1130 size -= 4;
1131 }
1132
1133 return result;
1134}
1135
1136static const struct file_operations amdgpu_ttm_vram_fops = {
1137 .owner = THIS_MODULE,
1138 .read = amdgpu_ttm_vram_read,
1139 .llseek = default_llseek
1140};
1141
1142static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1143 size_t size, loff_t *pos)
1144{
1145 struct amdgpu_device *adev = f->f_inode->i_private;
1146 ssize_t result = 0;
1147 int r;
1148
1149 while (size) {
1150 loff_t p = *pos / PAGE_SIZE;
1151 unsigned off = *pos & ~PAGE_MASK;
1152 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1153 struct page *page;
1154 void *ptr;
1155
1156 if (p >= adev->gart.num_cpu_pages)
1157 return result;
1158
1159 page = adev->gart.pages[p];
1160 if (page) {
1161 ptr = kmap(page);
1162 ptr += off;
1163
1164 r = copy_to_user(buf, ptr, cur_size);
1165 kunmap(adev->gart.pages[p]);
1166 } else
1167 r = clear_user(buf, cur_size);
1168
1169 if (r)
1170 return -EFAULT;
1171
1172 result += cur_size;
1173 buf += cur_size;
1174 *pos += cur_size;
1175 size -= cur_size;
1176 }
1177
1178 return result;
1179}
1180
1181static const struct file_operations amdgpu_ttm_gtt_fops = {
1182 .owner = THIS_MODULE,
1183 .read = amdgpu_ttm_gtt_read,
1184 .llseek = default_llseek
1185};
1186
1187#endif
1188
1189static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1190{
1191#if defined(CONFIG_DEBUG_FS)
1192 unsigned count;
1193
1194 struct drm_minor *minor = adev->ddev->primary;
1195 struct dentry *ent, *root = minor->debugfs_root;
1196
1197 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1198 adev, &amdgpu_ttm_vram_fops);
1199 if (IS_ERR(ent))
1200 return PTR_ERR(ent);
1201 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1202 adev->mman.vram = ent;
1203
1204 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1205 adev, &amdgpu_ttm_gtt_fops);
1206 if (IS_ERR(ent))
1207 return PTR_ERR(ent);
1208 i_size_write(ent->d_inode, adev->mc.gtt_size);
1209 adev->mman.gtt = ent;
1210
1211 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1212
1213#ifdef CONFIG_SWIOTLB
1214 if (!swiotlb_nr_tbl())
1215 --count;
1216#endif
1217
1218 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1219#else
1220
1221 return 0;
1222#endif
1223}
1224
1225static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1226{
1227#if defined(CONFIG_DEBUG_FS)
1228
1229 debugfs_remove(adev->mman.vram);
1230 adev->mman.vram = NULL;
1231
1232 debugfs_remove(adev->mman.gtt);
1233 adev->mman.gtt = NULL;
1234#endif
1235}
Michael's Linux tree.