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IB/qib: Support the new memory registration API
[people/ms/linux.git] / drivers / infiniband / hw / qib / qib_verbs.c
CommitLineData
f931551b 1/*
e2eed58b 2 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
1fb9fed6 3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
f931551b
RC		 4 * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <rdma/ib_mad.h>
36#include <rdma/ib_user_verbs.h>
37#include <linux/io.h>
e4dd23d7 38#include <linux/module.h>
f931551b
RC		 39#include <linux/utsname.h>
40#include <linux/rculist.h>
41#include <linux/mm.h>
af061a64 42#include <linux/random.h>
d6f1c17e 43#include <linux/vmalloc.h>
f931551b
RC		 44
45#include "qib.h"
46#include "qib_common.h"
47
af061a64 48static unsigned int ib_qib_qp_table_size = 256;
f931551b
RC		 49module_param_named(qp_table_size, ib_qib_qp_table_size, uint, S_IRUGO);
50MODULE_PARM_DESC(qp_table_size, "QP table size");
51
52unsigned int ib_qib_lkey_table_size = 16;
53module_param_named(lkey_table_size, ib_qib_lkey_table_size, uint,
54 S_IRUGO);
55MODULE_PARM_DESC(lkey_table_size,
56 "LKEY table size in bits (2^n, 1 <= n <= 23)");
57
58static unsigned int ib_qib_max_pds = 0xFFFF;
59module_param_named(max_pds, ib_qib_max_pds, uint, S_IRUGO);
60MODULE_PARM_DESC(max_pds,
61 "Maximum number of protection domains to support");
62
63static unsigned int ib_qib_max_ahs = 0xFFFF;
64module_param_named(max_ahs, ib_qib_max_ahs, uint, S_IRUGO);
65MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
66
67unsigned int ib_qib_max_cqes = 0x2FFFF;
68module_param_named(max_cqes, ib_qib_max_cqes, uint, S_IRUGO);
69MODULE_PARM_DESC(max_cqes,
70 "Maximum number of completion queue entries to support");
71
72unsigned int ib_qib_max_cqs = 0x1FFFF;
73module_param_named(max_cqs, ib_qib_max_cqs, uint, S_IRUGO);
74MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
75
76unsigned int ib_qib_max_qp_wrs = 0x3FFF;
77module_param_named(max_qp_wrs, ib_qib_max_qp_wrs, uint, S_IRUGO);
78MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
79
80unsigned int ib_qib_max_qps = 16384;
81module_param_named(max_qps, ib_qib_max_qps, uint, S_IRUGO);
82MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
83
84unsigned int ib_qib_max_sges = 0x60;
85module_param_named(max_sges, ib_qib_max_sges, uint, S_IRUGO);
86MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
87
88unsigned int ib_qib_max_mcast_grps = 16384;
89module_param_named(max_mcast_grps, ib_qib_max_mcast_grps, uint, S_IRUGO);
90MODULE_PARM_DESC(max_mcast_grps,
91 "Maximum number of multicast groups to support");
92
93unsigned int ib_qib_max_mcast_qp_attached = 16;
94module_param_named(max_mcast_qp_attached, ib_qib_max_mcast_qp_attached,
95 uint, S_IRUGO);
96MODULE_PARM_DESC(max_mcast_qp_attached,
97 "Maximum number of attached QPs to support");
98
99unsigned int ib_qib_max_srqs = 1024;
100module_param_named(max_srqs, ib_qib_max_srqs, uint, S_IRUGO);
101MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
102
103unsigned int ib_qib_max_srq_sges = 128;
104module_param_named(max_srq_sges, ib_qib_max_srq_sges, uint, S_IRUGO);
105MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
106
107unsigned int ib_qib_max_srq_wrs = 0x1FFFF;
108module_param_named(max_srq_wrs, ib_qib_max_srq_wrs, uint, S_IRUGO);
109MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
110
111static unsigned int ib_qib_disable_sma;
112module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
113MODULE_PARM_DESC(disable_sma, "Disable the SMA");
114
115/*
116 * Note that it is OK to post send work requests in the SQE and ERR
117 * states; qib_do_send() will process them and generate error
118 * completions as per IB 1.2 C10-96.
119 */
120const int ib_qib_state_ops[IB_QPS_ERR + 1] = {
121 [IB_QPS_RESET] = 0,
122 [IB_QPS_INIT] = QIB_POST_RECV_OK,
123 [IB_QPS_RTR] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK,
124 [IB_QPS_RTS] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
125 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK |
126 QIB_PROCESS_NEXT_SEND_OK,
127 [IB_QPS_SQD] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
128 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK,
129 [IB_QPS_SQE] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
130 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
131 [IB_QPS_ERR] = QIB_POST_RECV_OK | QIB_FLUSH_RECV |
132 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
133};
134
135struct qib_ucontext {
136 struct ib_ucontext ibucontext;
137};
138
139static inline struct qib_ucontext *to_iucontext(struct ib_ucontext
140 *ibucontext)
141{
142 return container_of(ibucontext, struct qib_ucontext, ibucontext);
143}
144
145/*
146 * Translate ib_wr_opcode into ib_wc_opcode.
147 */
148const enum ib_wc_opcode ib_qib_wc_opcode[] = {
149 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
150 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
151 [IB_WR_SEND] = IB_WC_SEND,
152 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
153 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
154 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
155 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
156};
157
158/*
159 * System image GUID.
160 */
161__be64 ib_qib_sys_image_guid;
162
163/**
164 * qib_copy_sge - copy data to SGE memory
165 * @ss: the SGE state
166 * @data: the data to copy
167 * @length: the length of the data
168 */
169void qib_copy_sge(struct qib_sge_state *ss, void *data, u32 length, int release)
170{
171 struct qib_sge *sge = &ss->sge;
172
173 while (length) {
174 u32 len = sge->length;
175
176 if (len > length)
177 len = length;
178 if (len > sge->sge_length)
179 len = sge->sge_length;
180 BUG_ON(len == 0);
181 memcpy(sge->vaddr, data, len);
182 sge->vaddr += len;
183 sge->length -= len;
184 sge->sge_length -= len;
185 if (sge->sge_length == 0) {
186 if (release)
6a82649f 187 qib_put_mr(sge->mr);
f931551b
RC		 188 if (--ss->num_sge)
189 *sge = *ss->sg_list++;
190 } else if (sge->length == 0 && sge->mr->lkey) {
191 if (++sge->n >= QIB_SEGSZ) {
192 if (++sge->m >= sge->mr->mapsz)
193 break;
194 sge->n = 0;
195 }
196 sge->vaddr =
197 sge->mr->map[sge->m]->segs[sge->n].vaddr;
198 sge->length =
199 sge->mr->map[sge->m]->segs[sge->n].length;
200 }
201 data += len;
202 length -= len;
203 }
204}
205
206/**
207 * qib_skip_sge - skip over SGE memory - XXX almost dup of prev func
208 * @ss: the SGE state
209 * @length: the number of bytes to skip
210 */
211void qib_skip_sge(struct qib_sge_state *ss, u32 length, int release)
212{
213 struct qib_sge *sge = &ss->sge;
214
215 while (length) {
216 u32 len = sge->length;
217
218 if (len > length)
219 len = length;
220 if (len > sge->sge_length)
221 len = sge->sge_length;
222 BUG_ON(len == 0);
223 sge->vaddr += len;
224 sge->length -= len;
225 sge->sge_length -= len;
226 if (sge->sge_length == 0) {
227 if (release)
6a82649f 228 qib_put_mr(sge->mr);
f931551b
RC		 229 if (--ss->num_sge)
230 *sge = *ss->sg_list++;
231 } else if (sge->length == 0 && sge->mr->lkey) {
232 if (++sge->n >= QIB_SEGSZ) {
233 if (++sge->m >= sge->mr->mapsz)
234 break;
235 sge->n = 0;
236 }
237 sge->vaddr =
238 sge->mr->map[sge->m]->segs[sge->n].vaddr;
239 sge->length =
240 sge->mr->map[sge->m]->segs[sge->n].length;
241 }
242 length -= len;
243 }
244}
245
246/*
247 * Count the number of DMA descriptors needed to send length bytes of data.
248 * Don't modify the qib_sge_state to get the count.
249 * Return zero if any of the segments is not aligned.
250 */
251static u32 qib_count_sge(struct qib_sge_state *ss, u32 length)
252{
253 struct qib_sge *sg_list = ss->sg_list;
254 struct qib_sge sge = ss->sge;
255 u8 num_sge = ss->num_sge;
256 u32 ndesc = 1; /* count the header */
257
258 while (length) {
259 u32 len = sge.length;
260
261 if (len > length)
262 len = length;
263 if (len > sge.sge_length)
264 len = sge.sge_length;
265 BUG_ON(len == 0);
266 if (((long) sge.vaddr & (sizeof(u32) - 1)) ||
267 (len != length && (len & (sizeof(u32) - 1)))) {
268 ndesc = 0;
269 break;
270 }
271 ndesc++;
272 sge.vaddr += len;
273 sge.length -= len;
274 sge.sge_length -= len;
275 if (sge.sge_length == 0) {
276 if (--num_sge)
277 sge = *sg_list++;
278 } else if (sge.length == 0 && sge.mr->lkey) {
279 if (++sge.n >= QIB_SEGSZ) {
280 if (++sge.m >= sge.mr->mapsz)
281 break;
282 sge.n = 0;
283 }
284 sge.vaddr =
285 sge.mr->map[sge.m]->segs[sge.n].vaddr;
286 sge.length =
287 sge.mr->map[sge.m]->segs[sge.n].length;
288 }
289 length -= len;
290 }
291 return ndesc;
292}
293
294/*
295 * Copy from the SGEs to the data buffer.
296 */
297static void qib_copy_from_sge(void *data, struct qib_sge_state *ss, u32 length)
298{
299 struct qib_sge *sge = &ss->sge;
300
301 while (length) {
302 u32 len = sge->length;
303
304 if (len > length)
305 len = length;
306 if (len > sge->sge_length)
307 len = sge->sge_length;
308 BUG_ON(len == 0);
309 memcpy(data, sge->vaddr, len);
310 sge->vaddr += len;
311 sge->length -= len;
312 sge->sge_length -= len;
313 if (sge->sge_length == 0) {
314 if (--ss->num_sge)
315 *sge = *ss->sg_list++;
316 } else if (sge->length == 0 && sge->mr->lkey) {
317 if (++sge->n >= QIB_SEGSZ) {
318 if (++sge->m >= sge->mr->mapsz)
319 break;
320 sge->n = 0;
321 }
322 sge->vaddr =
323 sge->mr->map[sge->m]->segs[sge->n].vaddr;
324 sge->length =
325 sge->mr->map[sge->m]->segs[sge->n].length;
326 }
327 data += len;
328 length -= len;
329 }
330}
331
332/**
333 * qib_post_one_send - post one RC, UC, or UD send work request
334 * @qp: the QP to post on
335 * @wr: the work request to send
336 */
551ace12
MM		 337static int qib_post_one_send(struct qib_qp *qp, struct ib_send_wr *wr,
338 int *scheduled)
f931551b
RC		 339{
340 struct qib_swqe *wqe;
341 u32 next;
342 int i;
343 int j;
344 int acc;
345 int ret;
346 unsigned long flags;
347 struct qib_lkey_table *rkt;
348 struct qib_pd *pd;
349
350 spin_lock_irqsave(&qp->s_lock, flags);
351
352 /* Check that state is OK to post send. */
353 if (unlikely(!(ib_qib_state_ops[qp->state] & QIB_POST_SEND_OK)))
354 goto bail_inval;
355
356 /* IB spec says that num_sge == 0 is OK. */
357 if (wr->num_sge > qp->s_max_sge)
358 goto bail_inval;
359
360 /*
361 * Don't allow RDMA reads or atomic operations on UC or
362 * undefined operations.
363 * Make sure buffer is large enough to hold the result for atomics.
364 */
38071a46
SG		 365 if (wr->opcode == IB_WR_REG_MR) {
366 if (qib_reg_mr(qp, reg_wr(wr)))
367 goto bail_inval;
368 } else if (wr->opcode == IB_WR_FAST_REG_MR) {
f931551b
RC		 369 if (qib_fast_reg_mr(qp, wr))
370 goto bail_inval;
371 } else if (qp->ibqp.qp_type == IB_QPT_UC) {
372 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
373 goto bail_inval;
374 } else if (qp->ibqp.qp_type != IB_QPT_RC) {
375 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
376 if (wr->opcode != IB_WR_SEND &&
377 wr->opcode != IB_WR_SEND_WITH_IMM)
378 goto bail_inval;
379 /* Check UD destination address PD */
e622f2f4 380 if (qp->ibqp.pd != ud_wr(wr)->ah->pd)
f931551b
RC		 381 goto bail_inval;
382 } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
383 goto bail_inval;
384 else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
385 (wr->num_sge == 0 ||
386 wr->sg_list[0].length < sizeof(u64) ||
387 wr->sg_list[0].addr & (sizeof(u64) - 1)))
388 goto bail_inval;
389 else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
390 goto bail_inval;
391
392 next = qp->s_head + 1;
393 if (next >= qp->s_size)
394 next = 0;
395 if (next == qp->s_last) {
396 ret = -ENOMEM;
397 goto bail;
398 }
399
400 rkt = &to_idev(qp->ibqp.device)->lk_table;
401 pd = to_ipd(qp->ibqp.pd);
402 wqe = get_swqe_ptr(qp, qp->s_head);
e622f2f4
CH		 403
404 if (qp->ibqp.qp_type != IB_QPT_UC &&
405 qp->ibqp.qp_type != IB_QPT_RC)
406 memcpy(&wqe->ud_wr, ud_wr(wr), sizeof(wqe->ud_wr));
38071a46
SG		 407 else if (wr->opcode == IB_WR_REG_MR)
408 memcpy(&wqe->reg_wr, reg_wr(wr),
409 sizeof(wqe->reg_wr));
e622f2f4
CH		 410 else if (wr->opcode == IB_WR_FAST_REG_MR)
411 memcpy(&wqe->fast_reg_wr, fast_reg_wr(wr),
412 sizeof(wqe->fast_reg_wr));
413 else if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM ||
414 wr->opcode == IB_WR_RDMA_WRITE ||
415 wr->opcode == IB_WR_RDMA_READ)
416 memcpy(&wqe->rdma_wr, rdma_wr(wr), sizeof(wqe->rdma_wr));
417 else if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
418 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
419 memcpy(&wqe->atomic_wr, atomic_wr(wr), sizeof(wqe->atomic_wr));
420 else
421 memcpy(&wqe->wr, wr, sizeof(wqe->wr));
422
f931551b
RC		 423 wqe->length = 0;
424 j = 0;
425 if (wr->num_sge) {
426 acc = wr->opcode >= IB_WR_RDMA_READ ?
427 IB_ACCESS_LOCAL_WRITE : 0;
428 for (i = 0; i < wr->num_sge; i++) {
429 u32 length = wr->sg_list[i].length;
430 int ok;
431
432 if (length == 0)
433 continue;
434 ok = qib_lkey_ok(rkt, pd, &wqe->sg_list[j],
435 &wr->sg_list[i], acc);
436 if (!ok)
437 goto bail_inval_free;
438 wqe->length += length;
439 j++;
440 }
441 wqe->wr.num_sge = j;
442 }
443 if (qp->ibqp.qp_type == IB_QPT_UC ||
444 qp->ibqp.qp_type == IB_QPT_RC) {
445 if (wqe->length > 0x80000000U)
446 goto bail_inval_free;
447 } else if (wqe->length > (dd_from_ibdev(qp->ibqp.device)->pport +
448 qp->port_num - 1)->ibmtu)
449 goto bail_inval_free;
450 else
e622f2f4 451 atomic_inc(&to_iah(ud_wr(wr)->ah)->refcount);
f931551b
RC		 452 wqe->ssn = qp->s_ssn++;
453 qp->s_head = next;
454
455 ret = 0;
456 goto bail;
457
458bail_inval_free:
459 while (j) {
460 struct qib_sge *sge = &wqe->sg_list[--j];
461
6a82649f 462 qib_put_mr(sge->mr);
f931551b
RC		 463 }
464bail_inval:
465 ret = -EINVAL;
466bail:
551ace12
MM		 467 if (!ret && !wr->next &&
468 !qib_sdma_empty(
469 dd_from_ibdev(qp->ibqp.device)->pport + qp->port_num - 1)) {
470 qib_schedule_send(qp);
471 *scheduled = 1;
472 }
f931551b
RC		 473 spin_unlock_irqrestore(&qp->s_lock, flags);
474 return ret;
475}
476
477/**
478 * qib_post_send - post a send on a QP
479 * @ibqp: the QP to post the send on
480 * @wr: the list of work requests to post
481 * @bad_wr: the first bad WR is put here
482 *
483 * This may be called from interrupt context.
484 */
485static int qib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
486 struct ib_send_wr **bad_wr)
487{
488 struct qib_qp *qp = to_iqp(ibqp);
489 int err = 0;
551ace12 490 int scheduled = 0;
f931551b
RC		 491
492 for (; wr; wr = wr->next) {
551ace12 493 err = qib_post_one_send(qp, wr, &scheduled);
f931551b
RC		 494 if (err) {
495 *bad_wr = wr;
496 goto bail;
497 }
498 }
499
500 /* Try to do the send work in the caller's context. */
551ace12
MM		 501 if (!scheduled)
502 qib_do_send(&qp->s_work);
f931551b
RC		 503
504bail:
505 return err;
506}
507
508/**
509 * qib_post_receive - post a receive on a QP
510 * @ibqp: the QP to post the receive on
511 * @wr: the WR to post
512 * @bad_wr: the first bad WR is put here
513 *
514 * This may be called from interrupt context.
515 */
516static int qib_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
517 struct ib_recv_wr **bad_wr)
518{
519 struct qib_qp *qp = to_iqp(ibqp);
520 struct qib_rwq *wq = qp->r_rq.wq;
521 unsigned long flags;
522 int ret;
523
524 /* Check that state is OK to post receive. */
525 if (!(ib_qib_state_ops[qp->state] & QIB_POST_RECV_OK) || !wq) {
526 *bad_wr = wr;
527 ret = -EINVAL;
528 goto bail;
529 }
530
531 for (; wr; wr = wr->next) {
532 struct qib_rwqe *wqe;
533 u32 next;
534 int i;
535
536 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
537 *bad_wr = wr;
538 ret = -EINVAL;
539 goto bail;
540 }
541
542 spin_lock_irqsave(&qp->r_rq.lock, flags);
543 next = wq->head + 1;
544 if (next >= qp->r_rq.size)
545 next = 0;
546 if (next == wq->tail) {
547 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
548 *bad_wr = wr;
549 ret = -ENOMEM;
550 goto bail;
551 }
552
553 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
554 wqe->wr_id = wr->wr_id;
555 wqe->num_sge = wr->num_sge;
556 for (i = 0; i < wr->num_sge; i++)
557 wqe->sg_list[i] = wr->sg_list[i];
558 /* Make sure queue entry is written before the head index. */
559 smp_wmb();
560 wq->head = next;
561 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
562 }
563 ret = 0;
564
565bail:
566 return ret;
567}
568
569/**
570 * qib_qp_rcv - processing an incoming packet on a QP
571 * @rcd: the context pointer
572 * @hdr: the packet header
573 * @has_grh: true if the packet has a GRH
574 * @data: the packet data
575 * @tlen: the packet length
576 * @qp: the QP the packet came on
577 *
578 * This is called from qib_ib_rcv() to process an incoming packet
579 * for the given QP.
580 * Called at interrupt level.
581 */
582static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct qib_ib_header *hdr,
583 int has_grh, void *data, u32 tlen, struct qib_qp *qp)
584{
585 struct qib_ibport *ibp = &rcd->ppd->ibport_data;
586
a5210c12
RC		 587 spin_lock(&qp->r_lock);
588
f931551b
RC		 589 /* Check for valid receive state. */
590 if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK)) {
591 ibp->n_pkt_drops++;
a5210c12 592 goto unlock;
f931551b
RC		 593 }
594
595 switch (qp->ibqp.qp_type) {
596 case IB_QPT_SMI:
597 case IB_QPT_GSI:
598 if (ib_qib_disable_sma)
599 break;
600 /* FALLTHROUGH */
601 case IB_QPT_UD:
602 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
603 break;
604
605 case IB_QPT_RC:
606 qib_rc_rcv(rcd, hdr, has_grh, data, tlen, qp);
607 break;
608
609 case IB_QPT_UC:
610 qib_uc_rcv(ibp, hdr, has_grh, data, tlen, qp);
611 break;
612
613 default:
614 break;
615 }
a5210c12
RC		 616
617unlock:
618 spin_unlock(&qp->r_lock);
f931551b
RC		 619}
620
621/**
622 * qib_ib_rcv - process an incoming packet
623 * @rcd: the context pointer
624 * @rhdr: the header of the packet
625 * @data: the packet payload
626 * @tlen: the packet length
627 *
628 * This is called from qib_kreceive() to process an incoming packet at
629 * interrupt level. Tlen is the length of the header + data + CRC in bytes.
630 */
631void qib_ib_rcv(struct qib_ctxtdata *rcd, void *rhdr, void *data, u32 tlen)
632{
633 struct qib_pportdata *ppd = rcd->ppd;
634 struct qib_ibport *ibp = &ppd->ibport_data;
635 struct qib_ib_header *hdr = rhdr;
636 struct qib_other_headers *ohdr;
637 struct qib_qp *qp;
638 u32 qp_num;
639 int lnh;
640 u8 opcode;
641 u16 lid;
642
643 /* 24 == LRH+BTH+CRC */
644 if (unlikely(tlen < 24))
645 goto drop;
646
647 /* Check for a valid destination LID (see ch. 7.11.1). */
648 lid = be16_to_cpu(hdr->lrh[1]);
649 if (lid < QIB_MULTICAST_LID_BASE) {
650 lid &= ~((1 << ppd->lmc) - 1);
651 if (unlikely(lid != ppd->lid))
652 goto drop;
653 }
654
655 /* Check for GRH */
656 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
657 if (lnh == QIB_LRH_BTH)
658 ohdr = &hdr->u.oth;
659 else if (lnh == QIB_LRH_GRH) {
660 u32 vtf;
661
662 ohdr = &hdr->u.l.oth;
663 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
664 goto drop;
665 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
666 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
667 goto drop;
668 } else
669 goto drop;
670
ddb88765
MM		 671 opcode = (be32_to_cpu(ohdr->bth[0]) >> 24) & 0x7f;
672#ifdef CONFIG_DEBUG_FS
673 rcd->opstats->stats[opcode].n_bytes += tlen;
674 rcd->opstats->stats[opcode].n_packets++;
675#endif
f931551b
RC		 676
677 /* Get the destination QP number. */
678 qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK;
679 if (qp_num == QIB_MULTICAST_QPN) {
680 struct qib_mcast *mcast;
681 struct qib_mcast_qp *p;
682
683 if (lnh != QIB_LRH_GRH)
684 goto drop;
685 mcast = qib_mcast_find(ibp, &hdr->u.l.grh.dgid);
686 if (mcast == NULL)
687 goto drop;
7d7632ad 688 this_cpu_inc(ibp->pmastats->n_multicast_rcv);
f931551b
RC		 689 list_for_each_entry_rcu(p, &mcast->qp_list, list)
690 qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
691 /*
692 * Notify qib_multicast_detach() if it is waiting for us
693 * to finish.
694 */
695 if (atomic_dec_return(&mcast->refcount) <= 1)
696 wake_up(&mcast->wait);
697 } else {
af061a64
MM		 698 if (rcd->lookaside_qp) {
699 if (rcd->lookaside_qpn != qp_num) {
700 if (atomic_dec_and_test(
701 &rcd->lookaside_qp->refcount))
702 wake_up(
703 &rcd->lookaside_qp->wait);
8572de97
YD		 704 rcd->lookaside_qp = NULL;
705 }
af061a64
MM		 706 }
707 if (!rcd->lookaside_qp) {
708 qp = qib_lookup_qpn(ibp, qp_num);
709 if (!qp)
710 goto drop;
711 rcd->lookaside_qp = qp;
712 rcd->lookaside_qpn = qp_num;
713 } else
714 qp = rcd->lookaside_qp;
7d7632ad 715 this_cpu_inc(ibp->pmastats->n_unicast_rcv);
f931551b 716 qib_qp_rcv(rcd, hdr, lnh == QIB_LRH_GRH, data, tlen, qp);
f931551b
RC		 717 }
718 return;
719
720drop:
721 ibp->n_pkt_drops++;
722}
723
724/*
725 * This is called from a timer to check for QPs
726 * which need kernel memory in order to send a packet.
727 */
728static void mem_timer(unsigned long data)
729{
730 struct qib_ibdev *dev = (struct qib_ibdev *) data;
731 struct list_head *list = &dev->memwait;
732 struct qib_qp *qp = NULL;
733 unsigned long flags;
734
735 spin_lock_irqsave(&dev->pending_lock, flags);
736 if (!list_empty(list)) {
737 qp = list_entry(list->next, struct qib_qp, iowait);
738 list_del_init(&qp->iowait);
739 atomic_inc(&qp->refcount);
740 if (!list_empty(list))
741 mod_timer(&dev->mem_timer, jiffies + 1);
742 }
743 spin_unlock_irqrestore(&dev->pending_lock, flags);
744
745 if (qp) {
746 spin_lock_irqsave(&qp->s_lock, flags);
747 if (qp->s_flags & QIB_S_WAIT_KMEM) {
748 qp->s_flags &= ~QIB_S_WAIT_KMEM;
749 qib_schedule_send(qp);
750 }
751 spin_unlock_irqrestore(&qp->s_lock, flags);
752 if (atomic_dec_and_test(&qp->refcount))
753 wake_up(&qp->wait);
754 }
755}
756
757static void update_sge(struct qib_sge_state *ss, u32 length)
758{
759 struct qib_sge *sge = &ss->sge;
760
761 sge->vaddr += length;
762 sge->length -= length;
763 sge->sge_length -= length;
764 if (sge->sge_length == 0) {
765 if (--ss->num_sge)
766 *sge = *ss->sg_list++;
767 } else if (sge->length == 0 && sge->mr->lkey) {
768 if (++sge->n >= QIB_SEGSZ) {
769 if (++sge->m >= sge->mr->mapsz)
770 return;
771 sge->n = 0;
772 }
773 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
774 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
775 }
776}
777
778#ifdef __LITTLE_ENDIAN
779static inline u32 get_upper_bits(u32 data, u32 shift)
780{
781 return data >> shift;
782}
783
784static inline u32 set_upper_bits(u32 data, u32 shift)
785{
786 return data << shift;
787}
788
789static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
790{
791 data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
792 data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
793 return data;
794}
795#else
796static inline u32 get_upper_bits(u32 data, u32 shift)
797{
798 return data << shift;
799}
800
801static inline u32 set_upper_bits(u32 data, u32 shift)
802{
803 return data >> shift;
804}
805
806static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
807{
808 data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
809 data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
810 return data;
811}
812#endif
813
814static void copy_io(u32 __iomem *piobuf, struct qib_sge_state *ss,
815 u32 length, unsigned flush_wc)
816{
817 u32 extra = 0;
818 u32 data = 0;
819 u32 last;
820
821 while (1) {
822 u32 len = ss->sge.length;
823 u32 off;
824
825 if (len > length)
826 len = length;
827 if (len > ss->sge.sge_length)
828 len = ss->sge.sge_length;
829 BUG_ON(len == 0);
830 /* If the source address is not aligned, try to align it. */
831 off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
832 if (off) {
833 u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
834 ~(sizeof(u32) - 1));
835 u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
836 u32 y;
837
838 y = sizeof(u32) - off;
839 if (len > y)
840 len = y;
841 if (len + extra >= sizeof(u32)) {
842 data |= set_upper_bits(v, extra *
843 BITS_PER_BYTE);
844 len = sizeof(u32) - extra;
845 if (len == length) {
846 last = data;
847 break;
848 }
849 __raw_writel(data, piobuf);
850 piobuf++;
851 extra = 0;
852 data = 0;
853 } else {
854 /* Clear unused upper bytes */
855 data |= clear_upper_bytes(v, len, extra);
856 if (len == length) {
857 last = data;
858 break;
859 }
860 extra += len;
861 }
862 } else if (extra) {
863 /* Source address is aligned. */
864 u32 *addr = (u32 *) ss->sge.vaddr;
865 int shift = extra * BITS_PER_BYTE;
866 int ushift = 32 - shift;
867 u32 l = len;
868
869 while (l >= sizeof(u32)) {
870 u32 v = *addr;
871
872 data |= set_upper_bits(v, shift);
873 __raw_writel(data, piobuf);
874 data = get_upper_bits(v, ushift);
875 piobuf++;
876 addr++;
877 l -= sizeof(u32);
878 }
879 /*
880 * We still have 'extra' number of bytes leftover.
881 */
882 if (l) {
883 u32 v = *addr;
884
885 if (l + extra >= sizeof(u32)) {
886 data |= set_upper_bits(v, shift);
887 len -= l + extra - sizeof(u32);
888 if (len == length) {
889 last = data;
890 break;
891 }
892 __raw_writel(data, piobuf);
893 piobuf++;
894 extra = 0;
895 data = 0;
896 } else {
897 /* Clear unused upper bytes */
898 data |= clear_upper_bytes(v, l, extra);
899 if (len == length) {
900 last = data;
901 break;
902 }
903 extra += l;
904 }
905 } else if (len == length) {
906 last = data;
907 break;
908 }
909 } else if (len == length) {
910 u32 w;
911
912 /*
913 * Need to round up for the last dword in the
914 * packet.
915 */
916 w = (len + 3) >> 2;
917 qib_pio_copy(piobuf, ss->sge.vaddr, w - 1);
918 piobuf += w - 1;
919 last = ((u32 *) ss->sge.vaddr)[w - 1];
920 break;
921 } else {
922 u32 w = len >> 2;
923
924 qib_pio_copy(piobuf, ss->sge.vaddr, w);
925 piobuf += w;
926
927 extra = len & (sizeof(u32) - 1);
928 if (extra) {
929 u32 v = ((u32 *) ss->sge.vaddr)[w];
930
931 /* Clear unused upper bytes */
932 data = clear_upper_bytes(v, extra, 0);
933 }
934 }
935 update_sge(ss, len);
936 length -= len;
937 }
938 /* Update address before sending packet. */
939 update_sge(ss, length);
940 if (flush_wc) {
941 /* must flush early everything before trigger word */
942 qib_flush_wc();
943 __raw_writel(last, piobuf);
944 /* be sure trigger word is written */
945 qib_flush_wc();
946 } else
947 __raw_writel(last, piobuf);
948}
949
48947109
MM		 950static noinline struct qib_verbs_txreq *__get_txreq(struct qib_ibdev *dev,
951 struct qib_qp *qp)
f931551b
RC		 952{
953 struct qib_verbs_txreq *tx;
954 unsigned long flags;
955
956 spin_lock_irqsave(&qp->s_lock, flags);
957 spin_lock(&dev->pending_lock);
958
959 if (!list_empty(&dev->txreq_free)) {
960 struct list_head *l = dev->txreq_free.next;
961
962 list_del(l);
48947109
MM		 963 spin_unlock(&dev->pending_lock);
964 spin_unlock_irqrestore(&qp->s_lock, flags);
f931551b 965 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
f931551b
RC		 966 } else {
967 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK &&
968 list_empty(&qp->iowait)) {
969 dev->n_txwait++;
970 qp->s_flags |= QIB_S_WAIT_TX;
971 list_add_tail(&qp->iowait, &dev->txwait);
972 }
f931551b 973 qp->s_flags &= ~QIB_S_BUSY;
48947109
MM		 974 spin_unlock(&dev->pending_lock);
975 spin_unlock_irqrestore(&qp->s_lock, flags);
976 tx = ERR_PTR(-EBUSY);
f931551b 977 }
48947109
MM		 978 return tx;
979}
f931551b 980
48947109
MM		 981static inline struct qib_verbs_txreq *get_txreq(struct qib_ibdev *dev,
982 struct qib_qp *qp)
983{
984 struct qib_verbs_txreq *tx;
985 unsigned long flags;
f931551b 986
48947109
MM		 987 spin_lock_irqsave(&dev->pending_lock, flags);
988 /* assume the list non empty */
989 if (likely(!list_empty(&dev->txreq_free))) {
990 struct list_head *l = dev->txreq_free.next;
991
992 list_del(l);
993 spin_unlock_irqrestore(&dev->pending_lock, flags);
994 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
995 } else {
996 /* call slow path to get the extra lock */
997 spin_unlock_irqrestore(&dev->pending_lock, flags);
998 tx = __get_txreq(dev, qp);
999 }
f931551b
RC		 1000 return tx;
1001}
1002
1003void qib_put_txreq(struct qib_verbs_txreq *tx)
1004{
1005 struct qib_ibdev *dev;
1006 struct qib_qp *qp;
1007 unsigned long flags;
1008
1009 qp = tx->qp;
1010 dev = to_idev(qp->ibqp.device);
1011
1012 if (atomic_dec_and_test(&qp->refcount))
1013 wake_up(&qp->wait);
1014 if (tx->mr) {
6a82649f 1015 qib_put_mr(tx->mr);
f931551b
RC		 1016 tx->mr = NULL;
1017 }
1018 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF) {
1019 tx->txreq.flags &= ~QIB_SDMA_TXREQ_F_FREEBUF;
1020 dma_unmap_single(&dd_from_dev(dev)->pcidev->dev,
1021 tx->txreq.addr, tx->hdr_dwords << 2,
1022 DMA_TO_DEVICE);
1023 kfree(tx->align_buf);
1024 }
1025
1026 spin_lock_irqsave(&dev->pending_lock, flags);
1027
1028 /* Put struct back on free list */
1029 list_add(&tx->txreq.list, &dev->txreq_free);
1030
1031 if (!list_empty(&dev->txwait)) {
1032 /* Wake up first QP wanting a free struct */
1033 qp = list_entry(dev->txwait.next, struct qib_qp, iowait);
1034 list_del_init(&qp->iowait);
1035 atomic_inc(&qp->refcount);
1036 spin_unlock_irqrestore(&dev->pending_lock, flags);
1037
1038 spin_lock_irqsave(&qp->s_lock, flags);
1039 if (qp->s_flags & QIB_S_WAIT_TX) {
1040 qp->s_flags &= ~QIB_S_WAIT_TX;
1041 qib_schedule_send(qp);
1042 }
1043 spin_unlock_irqrestore(&qp->s_lock, flags);
1044
1045 if (atomic_dec_and_test(&qp->refcount))
1046 wake_up(&qp->wait);
1047 } else
1048 spin_unlock_irqrestore(&dev->pending_lock, flags);
1049}
1050
1051/*
1052 * This is called when there are send DMA descriptors that might be
1053 * available.
1054 *
1055 * This is called with ppd->sdma_lock held.
1056 */
1057void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
1058{
1059 struct qib_qp *qp, *nqp;
1060 struct qib_qp *qps[20];
1061 struct qib_ibdev *dev;
1062 unsigned i, n;
1063
1064 n = 0;
1065 dev = &ppd->dd->verbs_dev;
1066 spin_lock(&dev->pending_lock);
1067
1068 /* Search wait list for first QP wanting DMA descriptors. */
1069 list_for_each_entry_safe(qp, nqp, &dev->dmawait, iowait) {
1070 if (qp->port_num != ppd->port)
1071 continue;
1072 if (n == ARRAY_SIZE(qps))
1073 break;
1074 if (qp->s_tx->txreq.sg_count > avail)
1075 break;
1076 avail -= qp->s_tx->txreq.sg_count;
1077 list_del_init(&qp->iowait);
1078 atomic_inc(&qp->refcount);
1079 qps[n++] = qp;
1080 }
1081
1082 spin_unlock(&dev->pending_lock);
1083
1084 for (i = 0; i < n; i++) {
1085 qp = qps[i];
1086 spin_lock(&qp->s_lock);
1087 if (qp->s_flags & QIB_S_WAIT_DMA_DESC) {
1088 qp->s_flags &= ~QIB_S_WAIT_DMA_DESC;
1089 qib_schedule_send(qp);
1090 }
1091 spin_unlock(&qp->s_lock);
1092 if (atomic_dec_and_test(&qp->refcount))
1093 wake_up(&qp->wait);
1094 }
1095}
1096
1097/*
1098 * This is called with ppd->sdma_lock held.
1099 */
1100static void sdma_complete(struct qib_sdma_txreq *cookie, int status)
1101{
1102 struct qib_verbs_txreq *tx =
1103 container_of(cookie, struct qib_verbs_txreq, txreq);
1104 struct qib_qp *qp = tx->qp;
1105
1106 spin_lock(&qp->s_lock);
1107 if (tx->wqe)
1108 qib_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
1109 else if (qp->ibqp.qp_type == IB_QPT_RC) {
1110 struct qib_ib_header *hdr;
1111
1112 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF)
1113 hdr = &tx->align_buf->hdr;
1114 else {
1115 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1116
1117 hdr = &dev->pio_hdrs[tx->hdr_inx].hdr;
1118 }
1119 qib_rc_send_complete(qp, hdr);
1120 }
1121 if (atomic_dec_and_test(&qp->s_dma_busy)) {
1122 if (qp->state == IB_QPS_RESET)
1123 wake_up(&qp->wait_dma);
1124 else if (qp->s_flags & QIB_S_WAIT_DMA) {
1125 qp->s_flags &= ~QIB_S_WAIT_DMA;
1126 qib_schedule_send(qp);
1127 }
1128 }
1129 spin_unlock(&qp->s_lock);
1130
1131 qib_put_txreq(tx);
1132}
1133
1134static int wait_kmem(struct qib_ibdev *dev, struct qib_qp *qp)
1135{
1136 unsigned long flags;
1137 int ret = 0;
1138
1139 spin_lock_irqsave(&qp->s_lock, flags);
1140 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1141 spin_lock(&dev->pending_lock);
1142 if (list_empty(&qp->iowait)) {
1143 if (list_empty(&dev->memwait))
1144 mod_timer(&dev->mem_timer, jiffies + 1);
1145 qp->s_flags |= QIB_S_WAIT_KMEM;
1146 list_add_tail(&qp->iowait, &dev->memwait);
1147 }
1148 spin_unlock(&dev->pending_lock);
1149 qp->s_flags &= ~QIB_S_BUSY;
1150 ret = -EBUSY;
1151 }
1152 spin_unlock_irqrestore(&qp->s_lock, flags);
1153
1154 return ret;
1155}
1156
1157static int qib_verbs_send_dma(struct qib_qp *qp, struct qib_ib_header *hdr,
1158 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1159 u32 plen, u32 dwords)
1160{
1161 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1162 struct qib_devdata *dd = dd_from_dev(dev);
1163 struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1164 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1165 struct qib_verbs_txreq *tx;
1166 struct qib_pio_header *phdr;
1167 u32 control;
1168 u32 ndesc;
1169 int ret;
1170
1171 tx = qp->s_tx;
1172 if (tx) {
1173 qp->s_tx = NULL;
1174 /* resend previously constructed packet */
1175 ret = qib_sdma_verbs_send(ppd, tx->ss, tx->dwords, tx);
1176 goto bail;
1177 }
1178
48947109
MM		 1179 tx = get_txreq(dev, qp);
1180 if (IS_ERR(tx))
1181 goto bail_tx;
f931551b
RC		 1182
1183 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1184 be16_to_cpu(hdr->lrh[0]) >> 12);
1185 tx->qp = qp;
1186 atomic_inc(&qp->refcount);
1187 tx->wqe = qp->s_wqe;
1188 tx->mr = qp->s_rdma_mr;
1189 if (qp->s_rdma_mr)
1190 qp->s_rdma_mr = NULL;
1191 tx->txreq.callback = sdma_complete;
1192 if (dd->flags & QIB_HAS_SDMA_TIMEOUT)
1193 tx->txreq.flags = QIB_SDMA_TXREQ_F_HEADTOHOST;
1194 else
1195 tx->txreq.flags = QIB_SDMA_TXREQ_F_INTREQ;
1196 if (plen + 1 > dd->piosize2kmax_dwords)
1197 tx->txreq.flags |= QIB_SDMA_TXREQ_F_USELARGEBUF;
1198
1199 if (len) {
1200 /*
1201 * Don't try to DMA if it takes more descriptors than
1202 * the queue holds.
1203 */
1204 ndesc = qib_count_sge(ss, len);
1205 if (ndesc >= ppd->sdma_descq_cnt)
1206 ndesc = 0;
1207 } else
1208 ndesc = 1;
1209 if (ndesc) {
1210 phdr = &dev->pio_hdrs[tx->hdr_inx];
1211 phdr->pbc[0] = cpu_to_le32(plen);
1212 phdr->pbc[1] = cpu_to_le32(control);
1213 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1214 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEDESC;
1215 tx->txreq.sg_count = ndesc;
1216 tx->txreq.addr = dev->pio_hdrs_phys +
1217 tx->hdr_inx * sizeof(struct qib_pio_header);
1218 tx->hdr_dwords = hdrwords + 2; /* add PBC length */
1219 ret = qib_sdma_verbs_send(ppd, ss, dwords, tx);
1220 goto bail;
1221 }
1222
1223 /* Allocate a buffer and copy the header and payload to it. */
1224 tx->hdr_dwords = plen + 1;
1225 phdr = kmalloc(tx->hdr_dwords << 2, GFP_ATOMIC);
1226 if (!phdr)
1227 goto err_tx;
1228 phdr->pbc[0] = cpu_to_le32(plen);
1229 phdr->pbc[1] = cpu_to_le32(control);
1230 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1231 qib_copy_from_sge((u32 *) &phdr->hdr + hdrwords, ss, len);
1232
1233 tx->txreq.addr = dma_map_single(&dd->pcidev->dev, phdr,
1234 tx->hdr_dwords << 2, DMA_TO_DEVICE);
1235 if (dma_mapping_error(&dd->pcidev->dev, tx->txreq.addr))
1236 goto map_err;
1237 tx->align_buf = phdr;
1238 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEBUF;
1239 tx->txreq.sg_count = 1;
1240 ret = qib_sdma_verbs_send(ppd, NULL, 0, tx);
1241 goto unaligned;
1242
1243map_err:
1244 kfree(phdr);
1245err_tx:
1246 qib_put_txreq(tx);
1247 ret = wait_kmem(dev, qp);
1248unaligned:
1249 ibp->n_unaligned++;
1250bail:
1251 return ret;
48947109
MM		 1252bail_tx:
1253 ret = PTR_ERR(tx);
1254 goto bail;
f931551b
RC		 1255}
1256
1257/*
1258 * If we are now in the error state, return zero to flush the
1259 * send work request.
1260 */
1261static int no_bufs_available(struct qib_qp *qp)
1262{
1263 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1264 struct qib_devdata *dd;
1265 unsigned long flags;
1266 int ret = 0;
1267
1268 /*
1269 * Note that as soon as want_buffer() is called and
1270 * possibly before it returns, qib_ib_piobufavail()
1271 * could be called. Therefore, put QP on the I/O wait list before
1272 * enabling the PIO avail interrupt.
1273 */
1274 spin_lock_irqsave(&qp->s_lock, flags);
1275 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1276 spin_lock(&dev->pending_lock);
1277 if (list_empty(&qp->iowait)) {
1278 dev->n_piowait++;
1279 qp->s_flags |= QIB_S_WAIT_PIO;
1280 list_add_tail(&qp->iowait, &dev->piowait);
1281 dd = dd_from_dev(dev);
1282 dd->f_wantpiobuf_intr(dd, 1);
1283 }
1284 spin_unlock(&dev->pending_lock);
1285 qp->s_flags &= ~QIB_S_BUSY;
1286 ret = -EBUSY;
1287 }
1288 spin_unlock_irqrestore(&qp->s_lock, flags);
1289 return ret;
1290}
1291
1292static int qib_verbs_send_pio(struct qib_qp *qp, struct qib_ib_header *ibhdr,
1293 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1294 u32 plen, u32 dwords)
1295{
1296 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1297 struct qib_pportdata *ppd = dd->pport + qp->port_num - 1;
1298 u32 *hdr = (u32 *) ibhdr;
1299 u32 __iomem *piobuf_orig;
1300 u32 __iomem *piobuf;
1301 u64 pbc;
1302 unsigned long flags;
1303 unsigned flush_wc;
1304 u32 control;
1305 u32 pbufn;
1306
1307 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1308 be16_to_cpu(ibhdr->lrh[0]) >> 12);
1309 pbc = ((u64) control << 32) | plen;
1310 piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
1311 if (unlikely(piobuf == NULL))
1312 return no_bufs_available(qp);
1313
1314 /*
1315 * Write the pbc.
1316 * We have to flush after the PBC for correctness on some cpus
1317 * or WC buffer can be written out of order.
1318 */
1319 writeq(pbc, piobuf);
1320 piobuf_orig = piobuf;
1321 piobuf += 2;
1322
1323 flush_wc = dd->flags & QIB_PIO_FLUSH_WC;
1324 if (len == 0) {
1325 /*
1326 * If there is just the header portion, must flush before
1327 * writing last word of header for correctness, and after
1328 * the last header word (trigger word).
1329 */
1330 if (flush_wc) {
1331 qib_flush_wc();
1332 qib_pio_copy(piobuf, hdr, hdrwords - 1);
1333 qib_flush_wc();
1334 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
1335 qib_flush_wc();
1336 } else
1337 qib_pio_copy(piobuf, hdr, hdrwords);
1338 goto done;
1339 }
1340
1341 if (flush_wc)
1342 qib_flush_wc();
1343 qib_pio_copy(piobuf, hdr, hdrwords);
1344 piobuf += hdrwords;
1345
1346 /* The common case is aligned and contained in one segment. */
1347 if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
1348 !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
1349 u32 *addr = (u32 *) ss->sge.vaddr;
1350
1351 /* Update address before sending packet. */
1352 update_sge(ss, len);
1353 if (flush_wc) {
1354 qib_pio_copy(piobuf, addr, dwords - 1);
1355 /* must flush early everything before trigger word */
1356 qib_flush_wc();
1357 __raw_writel(addr[dwords - 1], piobuf + dwords - 1);
1358 /* be sure trigger word is written */
1359 qib_flush_wc();
1360 } else
1361 qib_pio_copy(piobuf, addr, dwords);
1362 goto done;
1363 }
1364 copy_io(piobuf, ss, len, flush_wc);
1365done:
1366 if (dd->flags & QIB_USE_SPCL_TRIG) {
1367 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
da12c1f6 1368
f931551b
RC		 1369 qib_flush_wc();
1370 __raw_writel(0xaebecede, piobuf_orig + spcl_off);
1371 }
1372 qib_sendbuf_done(dd, pbufn);
1373 if (qp->s_rdma_mr) {
6a82649f 1374 qib_put_mr(qp->s_rdma_mr);
f931551b
RC		 1375 qp->s_rdma_mr = NULL;
1376 }
1377 if (qp->s_wqe) {
1378 spin_lock_irqsave(&qp->s_lock, flags);
1379 qib_send_complete(qp, qp->s_wqe, IB_WC_SUCCESS);
1380 spin_unlock_irqrestore(&qp->s_lock, flags);
1381 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1382 spin_lock_irqsave(&qp->s_lock, flags);
1383 qib_rc_send_complete(qp, ibhdr);
1384 spin_unlock_irqrestore(&qp->s_lock, flags);
1385 }
1386 return 0;
1387}
1388
1389/**
1390 * qib_verbs_send - send a packet
1391 * @qp: the QP to send on
1392 * @hdr: the packet header
1393 * @hdrwords: the number of 32-bit words in the header
1394 * @ss: the SGE to send
1395 * @len: the length of the packet in bytes
1396 *
1397 * Return zero if packet is sent or queued OK.
1398 * Return non-zero and clear qp->s_flags QIB_S_BUSY otherwise.
1399 */
1400int qib_verbs_send(struct qib_qp *qp, struct qib_ib_header *hdr,
1401 u32 hdrwords, struct qib_sge_state *ss, u32 len)
1402{
1403 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1404 u32 plen;
1405 int ret;
1406 u32 dwords = (len + 3) >> 2;
1407
1408 /*
1409 * Calculate the send buffer trigger address.
1410 * The +1 counts for the pbc control dword following the pbc length.
1411 */
1412 plen = hdrwords + dwords + 1;
1413
1414 /*
1415 * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1416 * can defer SDMA restart until link goes ACTIVE without
1417 * worrying about just how we got there.
1418 */
1419 if (qp->ibqp.qp_type == IB_QPT_SMI ||
1420 !(dd->flags & QIB_HAS_SEND_DMA))
1421 ret = qib_verbs_send_pio(qp, hdr, hdrwords, ss, len,
1422 plen, dwords);
1423 else
1424 ret = qib_verbs_send_dma(qp, hdr, hdrwords, ss, len,
1425 plen, dwords);
1426
1427 return ret;
1428}
1429
1430int qib_snapshot_counters(struct qib_pportdata *ppd, u64 *swords,
1431 u64 *rwords, u64 *spkts, u64 *rpkts,
1432 u64 *xmit_wait)
1433{
1434 int ret;
1435 struct qib_devdata *dd = ppd->dd;
1436
1437 if (!(dd->flags & QIB_PRESENT)) {
1438 /* no hardware, freeze, etc. */
1439 ret = -EINVAL;
1440 goto bail;
1441 }
1442 *swords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDSEND);
1443 *rwords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDRCV);
1444 *spkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTSEND);
1445 *rpkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTRCV);
1446 *xmit_wait = dd->f_portcntr(ppd, QIBPORTCNTR_SENDSTALL);
1447
1448 ret = 0;
1449
1450bail:
1451 return ret;
1452}
1453
1454/**
1455 * qib_get_counters - get various chip counters
1456 * @dd: the qlogic_ib device
1457 * @cntrs: counters are placed here
1458 *
1459 * Return the counters needed by recv_pma_get_portcounters().
1460 */
1461int qib_get_counters(struct qib_pportdata *ppd,
1462 struct qib_verbs_counters *cntrs)
1463{
1464 int ret;
1465
1466 if (!(ppd->dd->flags & QIB_PRESENT)) {
1467 /* no hardware, freeze, etc. */
1468 ret = -EINVAL;
1469 goto bail;
1470 }
1471 cntrs->symbol_error_counter =
1472 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBSYMBOLERR);
1473 cntrs->link_error_recovery_counter =
1474 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKERRRECOV);
1475 /*
1476 * The link downed counter counts when the other side downs the
1477 * connection. We add in the number of times we downed the link
1478 * due to local link integrity errors to compensate.
1479 */
1480 cntrs->link_downed_counter =
1481 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKDOWN);
1482 cntrs->port_rcv_errors =
1483 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXDROPPKT) +
1484 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVOVFL) +
1485 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERR_RLEN) +
1486 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_INVALIDRLEN) +
1487 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLINK) +
1488 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRICRC) +
1489 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRVCRC) +
1490 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLPCRC) +
1491 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_BADFORMAT);
1492 cntrs->port_rcv_errors +=
1493 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXLOCALPHYERR);
1494 cntrs->port_rcv_errors +=
1495 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXVLERR);
1496 cntrs->port_rcv_remphys_errors =
1497 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVEBP);
1498 cntrs->port_xmit_discards =
1499 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_UNSUPVL);
1500 cntrs->port_xmit_data = ppd->dd->f_portcntr(ppd,
1501 QIBPORTCNTR_WORDSEND);
1502 cntrs->port_rcv_data = ppd->dd->f_portcntr(ppd,
1503 QIBPORTCNTR_WORDRCV);
1504 cntrs->port_xmit_packets = ppd->dd->f_portcntr(ppd,
1505 QIBPORTCNTR_PKTSEND);
1506 cntrs->port_rcv_packets = ppd->dd->f_portcntr(ppd,
1507 QIBPORTCNTR_PKTRCV);
1508 cntrs->local_link_integrity_errors =
1509 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_LLI);
1510 cntrs->excessive_buffer_overrun_errors =
1511 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_EXCESSBUFOVFL);
1512 cntrs->vl15_dropped =
1513 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_VL15PKTDROP);
1514
1515 ret = 0;
1516
1517bail:
1518 return ret;
1519}
1520
1521/**
1522 * qib_ib_piobufavail - callback when a PIO buffer is available
1523 * @dd: the device pointer
1524 *
1525 * This is called from qib_intr() at interrupt level when a PIO buffer is
1526 * available after qib_verbs_send() returned an error that no buffers were
1527 * available. Disable the interrupt if there are no more QPs waiting.
1528 */
1529void qib_ib_piobufavail(struct qib_devdata *dd)
1530{
1531 struct qib_ibdev *dev = &dd->verbs_dev;
1532 struct list_head *list;
1533 struct qib_qp *qps[5];
1534 struct qib_qp *qp;
1535 unsigned long flags;
1536 unsigned i, n;
1537
1538 list = &dev->piowait;
1539 n = 0;
1540
1541 /*
1542 * Note: checking that the piowait list is empty and clearing
1543 * the buffer available interrupt needs to be atomic or we
1544 * could end up with QPs on the wait list with the interrupt
1545 * disabled.
1546 */
1547 spin_lock_irqsave(&dev->pending_lock, flags);
1548 while (!list_empty(list)) {
1549 if (n == ARRAY_SIZE(qps))
1550 goto full;
1551 qp = list_entry(list->next, struct qib_qp, iowait);
1552 list_del_init(&qp->iowait);
1553 atomic_inc(&qp->refcount);
1554 qps[n++] = qp;
1555 }
1556 dd->f_wantpiobuf_intr(dd, 0);
1557full:
1558 spin_unlock_irqrestore(&dev->pending_lock, flags);
1559
1560 for (i = 0; i < n; i++) {
1561 qp = qps[i];
1562
1563 spin_lock_irqsave(&qp->s_lock, flags);
1564 if (qp->s_flags & QIB_S_WAIT_PIO) {
1565 qp->s_flags &= ~QIB_S_WAIT_PIO;
1566 qib_schedule_send(qp);
1567 }
1568 spin_unlock_irqrestore(&qp->s_lock, flags);
1569
1570 /* Notify qib_destroy_qp() if it is waiting. */
1571 if (atomic_dec_and_test(&qp->refcount))
1572 wake_up(&qp->wait);
1573 }
1574}
1575
2528e33e
MB		 1576static int qib_query_device(struct ib_device *ibdev, struct ib_device_attr *props,
1577 struct ib_udata *uhw)
f931551b
RC		 1578{
1579 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1580 struct qib_ibdev *dev = to_idev(ibdev);
1581
2528e33e
MB		 1582 if (uhw->inlen || uhw->outlen)
1583 return -EINVAL;
f931551b
RC		 1584 memset(props, 0, sizeof(*props));
1585
1586 props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1587 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1588 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1589 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1590 props->page_size_cap = PAGE_SIZE;
1591 props->vendor_id =
1592 QIB_SRC_OUI_1 << 16 | QIB_SRC_OUI_2 << 8 | QIB_SRC_OUI_3;
1593 props->vendor_part_id = dd->deviceid;
1594 props->hw_ver = dd->minrev;
1595 props->sys_image_guid = ib_qib_sys_image_guid;
1596 props->max_mr_size = ~0ULL;
1597 props->max_qp = ib_qib_max_qps;
1598 props->max_qp_wr = ib_qib_max_qp_wrs;
1599 props->max_sge = ib_qib_max_sges;
aaae91f4 1600 props->max_sge_rd = ib_qib_max_sges;
f931551b
RC		 1601 props->max_cq = ib_qib_max_cqs;
1602 props->max_ah = ib_qib_max_ahs;
1603 props->max_cqe = ib_qib_max_cqes;
1604 props->max_mr = dev->lk_table.max;
1605 props->max_fmr = dev->lk_table.max;
1606 props->max_map_per_fmr = 32767;
1607 props->max_pd = ib_qib_max_pds;
1608 props->max_qp_rd_atom = QIB_MAX_RDMA_ATOMIC;
1609 props->max_qp_init_rd_atom = 255;
1610 /* props->max_res_rd_atom */
1611 props->max_srq = ib_qib_max_srqs;
1612 props->max_srq_wr = ib_qib_max_srq_wrs;
1613 props->max_srq_sge = ib_qib_max_srq_sges;
1614 /* props->local_ca_ack_delay */
1615 props->atomic_cap = IB_ATOMIC_GLOB;
1616 props->max_pkeys = qib_get_npkeys(dd);
1617 props->max_mcast_grp = ib_qib_max_mcast_grps;
1618 props->max_mcast_qp_attach = ib_qib_max_mcast_qp_attached;
1619 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1620 props->max_mcast_grp;
1621
1622 return 0;
1623}
1624
1625static int qib_query_port(struct ib_device *ibdev, u8 port,
1626 struct ib_port_attr *props)
1627{
1628 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1629 struct qib_ibport *ibp = to_iport(ibdev, port);
1630 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1631 enum ib_mtu mtu;
1632 u16 lid = ppd->lid;
1633
1634 memset(props, 0, sizeof(*props));
1635 props->lid = lid ? lid : be16_to_cpu(IB_LID_PERMISSIVE);
1636 props->lmc = ppd->lmc;
1637 props->sm_lid = ibp->sm_lid;
1638 props->sm_sl = ibp->sm_sl;
1639 props->state = dd->f_iblink_state(ppd->lastibcstat);
1640 props->phys_state = dd->f_ibphys_portstate(ppd->lastibcstat);
1641 props->port_cap_flags = ibp->port_cap_flags;
1642 props->gid_tbl_len = QIB_GUIDS_PER_PORT;
1643 props->max_msg_sz = 0x80000000;
1644 props->pkey_tbl_len = qib_get_npkeys(dd);
1645 props->bad_pkey_cntr = ibp->pkey_violations;
1646 props->qkey_viol_cntr = ibp->qkey_violations;
1647 props->active_width = ppd->link_width_active;
1648 /* See rate_show() */
1649 props->active_speed = ppd->link_speed_active;
1650 props->max_vl_num = qib_num_vls(ppd->vls_supported);
1651 props->init_type_reply = 0;
1652
1653 props->max_mtu = qib_ibmtu ? qib_ibmtu : IB_MTU_4096;
1654 switch (ppd->ibmtu) {
1655 case 4096:
1656 mtu = IB_MTU_4096;
1657 break;
1658 case 2048:
1659 mtu = IB_MTU_2048;
1660 break;
1661 case 1024:
1662 mtu = IB_MTU_1024;
1663 break;
1664 case 512:
1665 mtu = IB_MTU_512;
1666 break;
1667 case 256:
1668 mtu = IB_MTU_256;
1669 break;
1670 default:
1671 mtu = IB_MTU_2048;
1672 }
1673 props->active_mtu = mtu;
1674 props->subnet_timeout = ibp->subnet_timeout;
1675
1676 return 0;
1677}
1678
1679static int qib_modify_device(struct ib_device *device,
1680 int device_modify_mask,
1681 struct ib_device_modify *device_modify)
1682{
1683 struct qib_devdata *dd = dd_from_ibdev(device);
1684 unsigned i;
1685 int ret;
1686
1687 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1688 IB_DEVICE_MODIFY_NODE_DESC)) {
1689 ret = -EOPNOTSUPP;
1690 goto bail;
1691 }
1692
1693 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1694 memcpy(device->node_desc, device_modify->node_desc, 64);
1695 for (i = 0; i < dd->num_pports; i++) {
1696 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1697
1698 qib_node_desc_chg(ibp);
1699 }
1700 }
1701
1702 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1703 ib_qib_sys_image_guid =
1704 cpu_to_be64(device_modify->sys_image_guid);
1705 for (i = 0; i < dd->num_pports; i++) {
1706 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1707
1708 qib_sys_guid_chg(ibp);
1709 }
1710 }
1711
1712 ret = 0;
1713
1714bail:
1715 return ret;
1716}
1717
1718static int qib_modify_port(struct ib_device *ibdev, u8 port,
1719 int port_modify_mask, struct ib_port_modify *props)
1720{
1721 struct qib_ibport *ibp = to_iport(ibdev, port);
1722 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1723
1724 ibp->port_cap_flags |= props->set_port_cap_mask;
1725 ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1726 if (props->set_port_cap_mask || props->clr_port_cap_mask)
1727 qib_cap_mask_chg(ibp);
1728 if (port_modify_mask & IB_PORT_SHUTDOWN)
1729 qib_set_linkstate(ppd, QIB_IB_LINKDOWN);
1730 if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1731 ibp->qkey_violations = 0;
1732 return 0;
1733}
1734
1735static int qib_query_gid(struct ib_device *ibdev, u8 port,
1736 int index, union ib_gid *gid)
1737{
1738 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1739 int ret = 0;
1740
1741 if (!port || port > dd->num_pports)
1742 ret = -EINVAL;
1743 else {
1744 struct qib_ibport *ibp = to_iport(ibdev, port);
1745 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1746
1747 gid->global.subnet_prefix = ibp->gid_prefix;
1748 if (index == 0)
1749 gid->global.interface_id = ppd->guid;
1750 else if (index < QIB_GUIDS_PER_PORT)
1751 gid->global.interface_id = ibp->guids[index - 1];
1752 else
1753 ret = -EINVAL;
1754 }
1755
1756 return ret;
1757}
1758
1759static struct ib_pd *qib_alloc_pd(struct ib_device *ibdev,
1760 struct ib_ucontext *context,
1761 struct ib_udata *udata)
1762{
1763 struct qib_ibdev *dev = to_idev(ibdev);
1764 struct qib_pd *pd;
1765 struct ib_pd *ret;
1766
1767 /*
1768 * This is actually totally arbitrary. Some correctness tests
1769 * assume there's a maximum number of PDs that can be allocated.
1770 * We don't actually have this limit, but we fail the test if
1771 * we allow allocations of more than we report for this value.
1772 */
1773
041af0bb 1774 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
f931551b
RC		 1775 if (!pd) {
1776 ret = ERR_PTR(-ENOMEM);
1777 goto bail;
1778 }
1779
1780 spin_lock(&dev->n_pds_lock);
1781 if (dev->n_pds_allocated == ib_qib_max_pds) {
1782 spin_unlock(&dev->n_pds_lock);
1783 kfree(pd);
1784 ret = ERR_PTR(-ENOMEM);
1785 goto bail;
1786 }
1787
1788 dev->n_pds_allocated++;
1789 spin_unlock(&dev->n_pds_lock);
1790
1791 /* ib_alloc_pd() will initialize pd->ibpd. */
1792 pd->user = udata != NULL;
1793
1794 ret = &pd->ibpd;
1795
1796bail:
1797 return ret;
1798}
1799
1800static int qib_dealloc_pd(struct ib_pd *ibpd)
1801{
1802 struct qib_pd *pd = to_ipd(ibpd);
1803 struct qib_ibdev *dev = to_idev(ibpd->device);
1804
1805 spin_lock(&dev->n_pds_lock);
1806 dev->n_pds_allocated--;
1807 spin_unlock(&dev->n_pds_lock);
1808
1809 kfree(pd);
1810
1811 return 0;
1812}
1813
1814int qib_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1815{
1816 /* A multicast address requires a GRH (see ch. 8.4.1). */
1817 if (ah_attr->dlid >= QIB_MULTICAST_LID_BASE &&
1818 ah_attr->dlid != QIB_PERMISSIVE_LID &&
1819 !(ah_attr->ah_flags & IB_AH_GRH))
1820 goto bail;
1821 if ((ah_attr->ah_flags & IB_AH_GRH) &&
1822 ah_attr->grh.sgid_index >= QIB_GUIDS_PER_PORT)
1823 goto bail;
1824 if (ah_attr->dlid == 0)
1825 goto bail;
1826 if (ah_attr->port_num < 1 ||
1827 ah_attr->port_num > ibdev->phys_port_cnt)
1828 goto bail;
1829 if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1830 ib_rate_to_mult(ah_attr->static_rate) < 0)
1831 goto bail;
1832 if (ah_attr->sl > 15)
1833 goto bail;
1834 return 0;
1835bail:
1836 return -EINVAL;
1837}
1838
1839/**
1840 * qib_create_ah - create an address handle
1841 * @pd: the protection domain
1842 * @ah_attr: the attributes of the AH
1843 *
1844 * This may be called from interrupt context.
1845 */
1846static struct ib_ah *qib_create_ah(struct ib_pd *pd,
1847 struct ib_ah_attr *ah_attr)
1848{
1849 struct qib_ah *ah;
1850 struct ib_ah *ret;
1851 struct qib_ibdev *dev = to_idev(pd->device);
1852 unsigned long flags;
1853
1854 if (qib_check_ah(pd->device, ah_attr)) {
1855 ret = ERR_PTR(-EINVAL);
1856 goto bail;
1857 }
1858
041af0bb 1859 ah = kmalloc(sizeof(*ah), GFP_ATOMIC);
f931551b
RC		 1860 if (!ah) {
1861 ret = ERR_PTR(-ENOMEM);
1862 goto bail;
1863 }
1864
1865 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1866 if (dev->n_ahs_allocated == ib_qib_max_ahs) {
1867 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1868 kfree(ah);
1869 ret = ERR_PTR(-ENOMEM);
1870 goto bail;
1871 }
1872
1873 dev->n_ahs_allocated++;
1874 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1875
1876 /* ib_create_ah() will initialize ah->ibah. */
1877 ah->attr = *ah_attr;
1878 atomic_set(&ah->refcount, 0);
1879
1880 ret = &ah->ibah;
1881
1882bail:
1883 return ret;
1884}
1885
1fb9fed6
MM		 1886struct ib_ah *qib_create_qp0_ah(struct qib_ibport *ibp, u16 dlid)
1887{
1888 struct ib_ah_attr attr;
1889 struct ib_ah *ah = ERR_PTR(-EINVAL);
1890 struct qib_qp *qp0;
1891
041af0bb 1892 memset(&attr, 0, sizeof(attr));
1fb9fed6
MM		 1893 attr.dlid = dlid;
1894 attr.port_num = ppd_from_ibp(ibp)->port;
1895 rcu_read_lock();
1896 qp0 = rcu_dereference(ibp->qp0);
1897 if (qp0)
1898 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1899 rcu_read_unlock();
1900 return ah;
1901}
1902
f931551b
RC		 1903/**
1904 * qib_destroy_ah - destroy an address handle
1905 * @ibah: the AH to destroy
1906 *
1907 * This may be called from interrupt context.
1908 */
1909static int qib_destroy_ah(struct ib_ah *ibah)
1910{
1911 struct qib_ibdev *dev = to_idev(ibah->device);
1912 struct qib_ah *ah = to_iah(ibah);
1913 unsigned long flags;
1914
1915 if (atomic_read(&ah->refcount) != 0)
1916 return -EBUSY;
1917
1918 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1919 dev->n_ahs_allocated--;
1920 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1921
1922 kfree(ah);
1923
1924 return 0;
1925}
1926
1927static int qib_modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1928{
1929 struct qib_ah *ah = to_iah(ibah);
1930
1931 if (qib_check_ah(ibah->device, ah_attr))
1932 return -EINVAL;
1933
1934 ah->attr = *ah_attr;
1935
1936 return 0;
1937}
1938
1939static int qib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1940{
1941 struct qib_ah *ah = to_iah(ibah);
1942
1943 *ah_attr = ah->attr;
1944
1945 return 0;
1946}
1947
1948/**
1949 * qib_get_npkeys - return the size of the PKEY table for context 0
1950 * @dd: the qlogic_ib device
1951 */
1952unsigned qib_get_npkeys(struct qib_devdata *dd)
1953{
1954 return ARRAY_SIZE(dd->rcd[0]->pkeys);
1955}
1956
1957/*
1958 * Return the indexed PKEY from the port PKEY table.
1959 * No need to validate rcd[ctxt]; the port is setup if we are here.
1960 */
1961unsigned qib_get_pkey(struct qib_ibport *ibp, unsigned index)
1962{
1963 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1964 struct qib_devdata *dd = ppd->dd;
1965 unsigned ctxt = ppd->hw_pidx;
1966 unsigned ret;
1967
1968 /* dd->rcd null if mini_init or some init failures */
1969 if (!dd->rcd || index >= ARRAY_SIZE(dd->rcd[ctxt]->pkeys))
1970 ret = 0;
1971 else
1972 ret = dd->rcd[ctxt]->pkeys[index];
1973
1974 return ret;
1975}
1976
1977static int qib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1978 u16 *pkey)
1979{
1980 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1981 int ret;
1982
1983 if (index >= qib_get_npkeys(dd)) {
1984 ret = -EINVAL;
1985 goto bail;
1986 }
1987
1988 *pkey = qib_get_pkey(to_iport(ibdev, port), index);
1989 ret = 0;
1990
1991bail:
1992 return ret;
1993}
1994
1995/**
1996 * qib_alloc_ucontext - allocate a ucontest
1997 * @ibdev: the infiniband device
1998 * @udata: not used by the QLogic_IB driver
1999 */
2000
2001static struct ib_ucontext *qib_alloc_ucontext(struct ib_device *ibdev,
2002 struct ib_udata *udata)
2003{
2004 struct qib_ucontext *context;
2005 struct ib_ucontext *ret;
2006
041af0bb 2007 context = kmalloc(sizeof(*context), GFP_KERNEL);
f931551b
RC		 2008 if (!context) {
2009 ret = ERR_PTR(-ENOMEM);
2010 goto bail;
2011 }
2012
2013 ret = &context->ibucontext;
2014
2015bail:
2016 return ret;
2017}
2018
2019static int qib_dealloc_ucontext(struct ib_ucontext *context)
2020{
2021 kfree(to_iucontext(context));
2022 return 0;
2023}
2024
2025static void init_ibport(struct qib_pportdata *ppd)
2026{
2027 struct qib_verbs_counters cntrs;
2028 struct qib_ibport *ibp = &ppd->ibport_data;
2029
2030 spin_lock_init(&ibp->lock);
2031 /* Set the prefix to the default value (see ch. 4.1.1) */
2032 ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
2033 ibp->sm_lid = be16_to_cpu(IB_LID_PERMISSIVE);
2034 ibp->port_cap_flags = IB_PORT_SYS_IMAGE_GUID_SUP |
2035 IB_PORT_CLIENT_REG_SUP | IB_PORT_SL_MAP_SUP |
2036 IB_PORT_TRAP_SUP | IB_PORT_AUTO_MIGR_SUP |
2037 IB_PORT_DR_NOTICE_SUP | IB_PORT_CAP_MASK_NOTICE_SUP |
2038 IB_PORT_OTHER_LOCAL_CHANGES_SUP;
2039 if (ppd->dd->flags & QIB_HAS_LINK_LATENCY)
2040 ibp->port_cap_flags |= IB_PORT_LINK_LATENCY_SUP;
2041 ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
2042 ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
2043 ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
2044 ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
2045 ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
2046
2047 /* Snapshot current HW counters to "clear" them. */
2048 qib_get_counters(ppd, &cntrs);
2049 ibp->z_symbol_error_counter = cntrs.symbol_error_counter;
2050 ibp->z_link_error_recovery_counter =
2051 cntrs.link_error_recovery_counter;
2052 ibp->z_link_downed_counter = cntrs.link_downed_counter;
2053 ibp->z_port_rcv_errors = cntrs.port_rcv_errors;
2054 ibp->z_port_rcv_remphys_errors = cntrs.port_rcv_remphys_errors;
2055 ibp->z_port_xmit_discards = cntrs.port_xmit_discards;
2056 ibp->z_port_xmit_data = cntrs.port_xmit_data;
2057 ibp->z_port_rcv_data = cntrs.port_rcv_data;
2058 ibp->z_port_xmit_packets = cntrs.port_xmit_packets;
2059 ibp->z_port_rcv_packets = cntrs.port_rcv_packets;
2060 ibp->z_local_link_integrity_errors =
2061 cntrs.local_link_integrity_errors;
2062 ibp->z_excessive_buffer_overrun_errors =
2063 cntrs.excessive_buffer_overrun_errors;
2064 ibp->z_vl15_dropped = cntrs.vl15_dropped;
af061a64
MM		 2065 RCU_INIT_POINTER(ibp->qp0, NULL);
2066 RCU_INIT_POINTER(ibp->qp1, NULL);
f931551b
RC		 2067}
2068
7738613e
IW		 2069static int qib_port_immutable(struct ib_device *ibdev, u8 port_num,
2070 struct ib_port_immutable *immutable)
2071{
2072 struct ib_port_attr attr;
2073 int err;
2074
2075 err = qib_query_port(ibdev, port_num, &attr);
2076 if (err)
2077 return err;
2078
2079 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2080 immutable->gid_tbl_len = attr.gid_tbl_len;
f9b22e35 2081 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
337877a4 2082 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2083
2084 return 0;
2085}
2086
f931551b
RC		 2087/**
2088 * qib_register_ib_device - register our device with the infiniband core
2089 * @dd: the device data structure
2090 * Return the allocated qib_ibdev pointer or NULL on error.
2091 */
2092int qib_register_ib_device(struct qib_devdata *dd)
2093{
2094 struct qib_ibdev *dev = &dd->verbs_dev;
2095 struct ib_device *ibdev = &dev->ibdev;
2096 struct qib_pportdata *ppd = dd->pport;
2097 unsigned i, lk_tab_size;
2098 int ret;
2099
2100 dev->qp_table_size = ib_qib_qp_table_size;
af061a64 2101 get_random_bytes(&dev->qp_rnd, sizeof(dev->qp_rnd));
a46a2802
MM		 2102 dev->qp_table = kmalloc_array(
2103 dev->qp_table_size,
2104 sizeof(*dev->qp_table),
f931551b
RC		 2105 GFP_KERNEL);
2106 if (!dev->qp_table) {
2107 ret = -ENOMEM;
2108 goto err_qpt;
2109 }
af061a64
MM		 2110 for (i = 0; i < dev->qp_table_size; i++)
2111 RCU_INIT_POINTER(dev->qp_table[i], NULL);
f931551b
RC		 2112
2113 for (i = 0; i < dd->num_pports; i++)
2114 init_ibport(ppd + i);
2115
2116 /* Only need to initialize non-zero fields. */
2117 spin_lock_init(&dev->qpt_lock);
2118 spin_lock_init(&dev->n_pds_lock);
2119 spin_lock_init(&dev->n_ahs_lock);
2120 spin_lock_init(&dev->n_cqs_lock);
2121 spin_lock_init(&dev->n_qps_lock);
2122 spin_lock_init(&dev->n_srqs_lock);
2123 spin_lock_init(&dev->n_mcast_grps_lock);
2124 init_timer(&dev->mem_timer);
2125 dev->mem_timer.function = mem_timer;
2126 dev->mem_timer.data = (unsigned long) dev;
2127
2128 qib_init_qpn_table(dd, &dev->qpn_table);
2129
2130 /*
2131 * The top ib_qib_lkey_table_size bits are used to index the
2132 * table. The lower 8 bits can be owned by the user (copied from
2133 * the LKEY). The remaining bits act as a generation number or tag.
2134 */
2135 spin_lock_init(&dev->lk_table.lock);
d6f1c17e
MM		 2136 /* insure generation is at least 4 bits see keys.c */
2137 if (ib_qib_lkey_table_size > MAX_LKEY_TABLE_BITS) {
2138 qib_dev_warn(dd, "lkey bits %u too large, reduced to %u\n",
2139 ib_qib_lkey_table_size, MAX_LKEY_TABLE_BITS);
2140 ib_qib_lkey_table_size = MAX_LKEY_TABLE_BITS;
2141 }
f931551b
RC		 2142 dev->lk_table.max = 1 << ib_qib_lkey_table_size;
2143 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
1fb9fed6 2144 dev->lk_table.table = (struct qib_mregion __rcu **)
d6f1c17e 2145 vmalloc(lk_tab_size);
f931551b
RC		 2146 if (dev->lk_table.table == NULL) {
2147 ret = -ENOMEM;
2148 goto err_lk;
2149 }
8aac4cc3
MM		 2150 RCU_INIT_POINTER(dev->dma_mr, NULL);
2151 for (i = 0; i < dev->lk_table.max; i++)
2152 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
f931551b
RC		 2153 INIT_LIST_HEAD(&dev->pending_mmaps);
2154 spin_lock_init(&dev->pending_lock);
2155 dev->mmap_offset = PAGE_SIZE;
2156 spin_lock_init(&dev->mmap_offset_lock);
2157 INIT_LIST_HEAD(&dev->piowait);
2158 INIT_LIST_HEAD(&dev->dmawait);
2159 INIT_LIST_HEAD(&dev->txwait);
2160 INIT_LIST_HEAD(&dev->memwait);
2161 INIT_LIST_HEAD(&dev->txreq_free);
2162
2163 if (ppd->sdma_descq_cnt) {
2164 dev->pio_hdrs = dma_alloc_coherent(&dd->pcidev->dev,
2165 ppd->sdma_descq_cnt *
2166 sizeof(struct qib_pio_header),
2167 &dev->pio_hdrs_phys,
2168 GFP_KERNEL);
2169 if (!dev->pio_hdrs) {
2170 ret = -ENOMEM;
2171 goto err_hdrs;
2172 }
2173 }
2174
2175 for (i = 0; i < ppd->sdma_descq_cnt; i++) {
2176 struct qib_verbs_txreq *tx;
2177
041af0bb 2178 tx = kzalloc(sizeof(*tx), GFP_KERNEL);
f931551b
RC		 2179 if (!tx) {
2180 ret = -ENOMEM;
2181 goto err_tx;
2182 }
2183 tx->hdr_inx = i;
2184 list_add(&tx->txreq.list, &dev->txreq_free);
2185 }
2186
2187 /*
2188 * The system image GUID is supposed to be the same for all
2189 * IB HCAs in a single system but since there can be other
2190 * device types in the system, we can't be sure this is unique.
2191 */
2192 if (!ib_qib_sys_image_guid)
2193 ib_qib_sys_image_guid = ppd->guid;
2194
2195 strlcpy(ibdev->name, "qib%d", IB_DEVICE_NAME_MAX);
2196 ibdev->owner = THIS_MODULE;
2197 ibdev->node_guid = ppd->guid;
2198 ibdev->uverbs_abi_ver = QIB_UVERBS_ABI_VERSION;
2199 ibdev->uverbs_cmd_mask =
2200 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2201 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2202 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2203 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2204 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2205 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2206 (1ull << IB_USER_VERBS_CMD_MODIFY_AH) |
2207 (1ull << IB_USER_VERBS_CMD_QUERY_AH) |
2208 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2209 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2210 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2211 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2212 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2213 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2214 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2215 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2216 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2217 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2218 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2219 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2220 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2221 (1ull << IB_USER_VERBS_CMD_POST_SEND) |
2222 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2223 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2224 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2225 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2226 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2227 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2228 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2229 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2230 ibdev->node_type = RDMA_NODE_IB_CA;
2231 ibdev->phys_port_cnt = dd->num_pports;
2232 ibdev->num_comp_vectors = 1;
2233 ibdev->dma_device = &dd->pcidev->dev;
2234 ibdev->query_device = qib_query_device;
2235 ibdev->modify_device = qib_modify_device;
2236 ibdev->query_port = qib_query_port;
2237 ibdev->modify_port = qib_modify_port;
2238 ibdev->query_pkey = qib_query_pkey;
2239 ibdev->query_gid = qib_query_gid;
2240 ibdev->alloc_ucontext = qib_alloc_ucontext;
2241 ibdev->dealloc_ucontext = qib_dealloc_ucontext;
2242 ibdev->alloc_pd = qib_alloc_pd;
2243 ibdev->dealloc_pd = qib_dealloc_pd;
2244 ibdev->create_ah = qib_create_ah;
2245 ibdev->destroy_ah = qib_destroy_ah;
2246 ibdev->modify_ah = qib_modify_ah;
2247 ibdev->query_ah = qib_query_ah;
2248 ibdev->create_srq = qib_create_srq;
2249 ibdev->modify_srq = qib_modify_srq;
2250 ibdev->query_srq = qib_query_srq;
2251 ibdev->destroy_srq = qib_destroy_srq;
2252 ibdev->create_qp = qib_create_qp;
2253 ibdev->modify_qp = qib_modify_qp;
2254 ibdev->query_qp = qib_query_qp;
2255 ibdev->destroy_qp = qib_destroy_qp;
2256 ibdev->post_send = qib_post_send;
2257 ibdev->post_recv = qib_post_receive;
2258 ibdev->post_srq_recv = qib_post_srq_receive;
2259 ibdev->create_cq = qib_create_cq;
2260 ibdev->destroy_cq = qib_destroy_cq;
2261 ibdev->resize_cq = qib_resize_cq;
2262 ibdev->poll_cq = qib_poll_cq;
2263 ibdev->req_notify_cq = qib_req_notify_cq;
2264 ibdev->get_dma_mr = qib_get_dma_mr;
2265 ibdev->reg_phys_mr = qib_reg_phys_mr;
2266 ibdev->reg_user_mr = qib_reg_user_mr;
2267 ibdev->dereg_mr = qib_dereg_mr;
1302f845 2268 ibdev->alloc_mr = qib_alloc_mr;
38071a46 2269 ibdev->map_mr_sg = qib_map_mr_sg;
f931551b
RC		 2270 ibdev->alloc_fast_reg_page_list = qib_alloc_fast_reg_page_list;
2271 ibdev->free_fast_reg_page_list = qib_free_fast_reg_page_list;
2272 ibdev->alloc_fmr = qib_alloc_fmr;
2273 ibdev->map_phys_fmr = qib_map_phys_fmr;
2274 ibdev->unmap_fmr = qib_unmap_fmr;
2275 ibdev->dealloc_fmr = qib_dealloc_fmr;
2276 ibdev->attach_mcast = qib_multicast_attach;
2277 ibdev->detach_mcast = qib_multicast_detach;
2278 ibdev->process_mad = qib_process_mad;
2279 ibdev->mmap = qib_mmap;
2280 ibdev->dma_ops = &qib_dma_mapping_ops;
7738613e 2281 ibdev->get_port_immutable = qib_port_immutable;
f931551b
RC		 2282
2283 snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
e2eed58b 2284 "Intel Infiniband HCA %s", init_utsname()->nodename);
f931551b
RC		 2285
2286 ret = ib_register_device(ibdev, qib_create_port_files);
2287 if (ret)
2288 goto err_reg;
2289
2290 ret = qib_create_agents(dev);
2291 if (ret)
2292 goto err_agents;
2293
c9bdad3c
MM		 2294 ret = qib_verbs_register_sysfs(dd);
2295 if (ret)
f931551b
RC		 2296 goto err_class;
2297
2298 goto bail;
2299
2300err_class:
2301 qib_free_agents(dev);
2302err_agents:
2303 ib_unregister_device(ibdev);
2304err_reg:
2305err_tx:
2306 while (!list_empty(&dev->txreq_free)) {
2307 struct list_head *l = dev->txreq_free.next;
2308 struct qib_verbs_txreq *tx;
2309
2310 list_del(l);
2311 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2312 kfree(tx);
2313 }
2314 if (ppd->sdma_descq_cnt)
2315 dma_free_coherent(&dd->pcidev->dev,
2316 ppd->sdma_descq_cnt *
2317 sizeof(struct qib_pio_header),
2318 dev->pio_hdrs, dev->pio_hdrs_phys);
2319err_hdrs:
d6f1c17e 2320 vfree(dev->lk_table.table);
f931551b
RC		 2321err_lk:
2322 kfree(dev->qp_table);
2323err_qpt:
2324 qib_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2325bail:
2326 return ret;
2327}
2328
2329void qib_unregister_ib_device(struct qib_devdata *dd)
2330{
2331 struct qib_ibdev *dev = &dd->verbs_dev;
2332 struct ib_device *ibdev = &dev->ibdev;
2333 u32 qps_inuse;
2334 unsigned lk_tab_size;
2335
2336 qib_verbs_unregister_sysfs(dd);
2337
2338 qib_free_agents(dev);
2339
2340 ib_unregister_device(ibdev);
2341
2342 if (!list_empty(&dev->piowait))
2343 qib_dev_err(dd, "piowait list not empty!\n");
2344 if (!list_empty(&dev->dmawait))
2345 qib_dev_err(dd, "dmawait list not empty!\n");
2346 if (!list_empty(&dev->txwait))
2347 qib_dev_err(dd, "txwait list not empty!\n");
2348 if (!list_empty(&dev->memwait))
2349 qib_dev_err(dd, "memwait list not empty!\n");
2350 if (dev->dma_mr)
2351 qib_dev_err(dd, "DMA MR not NULL!\n");
2352
2353 qps_inuse = qib_free_all_qps(dd);
2354 if (qps_inuse)
2355 qib_dev_err(dd, "QP memory leak! %u still in use\n",
2356 qps_inuse);
2357
2358 del_timer_sync(&dev->mem_timer);
2359 qib_free_qpn_table(&dev->qpn_table);
2360 while (!list_empty(&dev->txreq_free)) {
2361 struct list_head *l = dev->txreq_free.next;
2362 struct qib_verbs_txreq *tx;
2363
2364 list_del(l);
2365 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2366 kfree(tx);
2367 }
2368 if (dd->pport->sdma_descq_cnt)
2369 dma_free_coherent(&dd->pcidev->dev,
2370 dd->pport->sdma_descq_cnt *
2371 sizeof(struct qib_pio_header),
2372 dev->pio_hdrs, dev->pio_hdrs_phys);
2373 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
d6f1c17e 2374 vfree(dev->lk_table.table);
f931551b
RC		 2375 kfree(dev->qp_table);
2376}
551ace12
MM		 2377
2378/*
2379 * This must be called with s_lock held.
2380 */
2381void qib_schedule_send(struct qib_qp *qp)
2382{
2383 if (qib_send_ok(qp)) {
2384 struct qib_ibport *ibp =
2385 to_iport(qp->ibqp.device, qp->port_num);
2386 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
2387
2388 queue_work(ppd->qib_wq, &qp->s_work);
2389 }
2390}
Michael's Linux tree.