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a2443fd1 1// SPDX-License-Identifier: GPL-2.0+
00db8189
AF
2/*
3 * drivers/net/phy/marvell.c
4 *
5 * Driver for Marvell PHYs
6 *
7 * Author: Andy Fleming
8 *
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 *
3871c387 11 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
00db8189 12 */
00db8189 13#include <linux/kernel.h>
00db8189 14#include <linux/string.h>
0b04680f 15#include <linux/ctype.h>
00db8189
AF
16#include <linux/errno.h>
17#include <linux/unistd.h>
0b04680f 18#include <linux/hwmon.h>
00db8189
AF
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/spinlock.h>
26#include <linux/mm.h>
27#include <linux/module.h>
00db8189
AF
28#include <linux/mii.h>
29#include <linux/ethtool.h>
fc879f72 30#include <linux/ethtool_netlink.h>
00db8189 31#include <linux/phy.h>
2f495c39 32#include <linux/marvell_phy.h>
69f42be8 33#include <linux/bitfield.h>
cf41a51d 34#include <linux/of.h>
b697d9d3 35#include <linux/sfp.h>
00db8189 36
eea3b201 37#include <linux/io.h>
00db8189 38#include <asm/irq.h>
eea3b201 39#include <linux/uaccess.h>
00db8189 40
27d916d6 41#define MII_MARVELL_PHY_PAGE 22
52295666
AL
42#define MII_MARVELL_COPPER_PAGE 0x00
43#define MII_MARVELL_FIBER_PAGE 0x01
44#define MII_MARVELL_MSCR_PAGE 0x02
45#define MII_MARVELL_LED_PAGE 0x03
0c9bcc1d 46#define MII_MARVELL_VCT5_PAGE 0x05
52295666 47#define MII_MARVELL_MISC_TEST_PAGE 0x06
fc879f72 48#define MII_MARVELL_VCT7_PAGE 0x07
52295666 49#define MII_MARVELL_WOL_PAGE 0x11
b697d9d3 50#define MII_MARVELL_MODE_PAGE 0x12
27d916d6 51
00db8189
AF
52#define MII_M1011_IEVENT 0x13
53#define MII_M1011_IEVENT_CLEAR 0x0000
54
55#define MII_M1011_IMASK 0x12
56#define MII_M1011_IMASK_INIT 0x6400
57#define MII_M1011_IMASK_CLEAR 0x0000
58
fecd5e91
AL
59#define MII_M1011_PHY_SCR 0x10
60#define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
f8d975be 61#define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
a3bdfce7 62#define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
fecd5e91
AL
63#define MII_M1011_PHY_SCR_MDI (0x0 << 5)
64#define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
65#define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
76884679 66
a3bdfce7
HK
67#define MII_M1011_PHY_SSR 0x11
68#define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
69
76884679
AF
70#define MII_M1111_PHY_LED_CONTROL 0x18
71#define MII_M1111_PHY_LED_DIRECT 0x4100
72#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682 73#define MII_M1111_PHY_EXT_CR 0x14
5c6bc519
HK
74#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
75#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
76#define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
61111598
AL
77#define MII_M1111_RGMII_RX_DELAY BIT(7)
78#define MII_M1111_RGMII_TX_DELAY BIT(1)
895ee682 79#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS
80
81#define MII_M1111_HWCFG_MODE_MASK 0xf
be937f1f 82#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 83#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
865b813a 84#define MII_M1111_HWCFG_MODE_RTBI 0x7
1887023a 85#define MII_M1111_HWCFG_MODE_COPPER_1000X_AN 0x8
5f8cbc13 86#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
865b813a 87#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
1887023a
RH
88#define MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN 0xc
89#define MII_M1111_HWCFG_SERIAL_AN_BYPASS BIT(12)
865b813a
AL
90#define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
91#define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
be937f1f 92
c477d044
CC
93#define MII_88E1121_PHY_MSCR_REG 21
94#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
95#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
424ca4c5 96#define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
c477d044 97
0b04680f
AL
98#define MII_88E1121_MISC_TEST 0x1a
99#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
100#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
101#define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
102#define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
103#define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
104#define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
105
106#define MII_88E1510_TEMP_SENSOR 0x1b
107#define MII_88E1510_TEMP_SENSOR_MASK 0xff
108
69f42be8
HK
109#define MII_88E1540_COPPER_CTRL3 0x1a
110#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
111#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
112#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
113#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
114#define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
115#define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
116
fee2d546 117#define MII_88E6390_MISC_TEST 0x1b
4f920c29
MB
118#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S (0x0 << 14)
119#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE (0x1 << 14)
120#define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_ONESHOT (0x2 << 14)
121#define MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE (0x3 << 14)
122#define MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK (0x3 << 14)
a978f7c4
MB
123#define MII_88E6393_MISC_TEST_SAMPLES_2048 (0x0 << 11)
124#define MII_88E6393_MISC_TEST_SAMPLES_4096 (0x1 << 11)
125#define MII_88E6393_MISC_TEST_SAMPLES_8192 (0x2 << 11)
126#define MII_88E6393_MISC_TEST_SAMPLES_16384 (0x3 << 11)
127#define MII_88E6393_MISC_TEST_SAMPLES_MASK (0x3 << 11)
128#define MII_88E6393_MISC_TEST_RATE_2_3MS (0x5 << 8)
129#define MII_88E6393_MISC_TEST_RATE_6_4MS (0x6 << 8)
130#define MII_88E6393_MISC_TEST_RATE_11_9MS (0x7 << 8)
131#define MII_88E6393_MISC_TEST_RATE_MASK (0x7 << 8)
fee2d546
AL
132
133#define MII_88E6390_TEMP_SENSOR 0x1c
a978f7c4
MB
134#define MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK 0xff00
135#define MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT 8
136#define MII_88E6390_TEMP_SENSOR_MASK 0xff
137#define MII_88E6390_TEMP_SENSOR_SAMPLES 10
fee2d546 138
337ac9d5
CC
139#define MII_88E1318S_PHY_MSCR1_REG 16
140#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 141
3871c387 142/* Copper Specific Interrupt Enable Register */
8cf8b87b 143#define MII_88E1318S_PHY_CSIER 0x12
3871c387 144/* WOL Event Interrupt Enable */
8cf8b87b 145#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
3871c387
MS
146
147/* LED Timer Control Register */
8cf8b87b
AL
148#define MII_88E1318S_PHY_LED_TCR 0x12
149#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
150#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
151#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
3871c387
MS
152
153/* Magic Packet MAC address registers */
8cf8b87b
AL
154#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
155#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
156#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
3871c387 157
8cf8b87b
AL
158#define MII_88E1318S_PHY_WOL_CTRL 0x10
159#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
6164659f 160#define MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE BIT(13)
8cf8b87b 161#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
3871c387 162
07777246 163#define MII_PHY_LED_CTRL 16
140bc929 164#define MII_88E1121_PHY_LED_DEF 0x0030
07777246 165#define MII_88E1510_PHY_LED_DEF 0x1177
a93f7fe1 166#define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
140bc929 167
be937f1f
AS
168#define MII_M1011_PHY_STATUS 0x11
169#define MII_M1011_PHY_STATUS_1000 0x8000
170#define MII_M1011_PHY_STATUS_100 0x4000
171#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
172#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
173#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
174#define MII_M1011_PHY_STATUS_LINK 0x0400
175
6b358aed
SH
176#define MII_88E3016_PHY_SPEC_CTRL 0x10
177#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
178#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 179
930b37ee
SR
180#define MII_88E1510_GEN_CTRL_REG_1 0x14
181#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
b697d9d3 182#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII 0x0 /* RGMII to copper */
930b37ee 183#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
b697d9d3
IB
184/* RGMII to 1000BASE-X */
185#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X 0x2
186/* RGMII to 100BASE-FX */
187#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX 0x3
188/* RGMII to SGMII */
189#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII 0x4
930b37ee
SR
190#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
191
893dfb14
MABI
192#define MII_88E1510_MSCR_2 0x15
193
0c9bcc1d
AL
194#define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
195#define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
196#define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
197#define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
198#define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
199#define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
200#define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
201
202#define MII_VCT5_CTRL 0x17
203#define MII_VCT5_CTRL_ENABLE BIT(15)
204#define MII_VCT5_CTRL_COMPLETE BIT(14)
205#define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
206#define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
207#define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
208#define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
209#define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
210#define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
211#define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
212#define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
213#define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
214#define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
215#define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
216#define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
217#define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
218#define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
219#define MII_VCT5_CTRL_SAMPLES_SHIFT 8
220#define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
221#define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
222#define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
223#define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
224#define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
225
226#define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
f2bc8ad3 227#define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
0c9bcc1d
AL
228#define MII_VCT5_TX_PULSE_CTRL 0x1c
229#define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
230#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
231#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
232#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
233#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
234#define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
235#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
236#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
237#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
238#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
239#define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
240#define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
241#define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
242
db8668a1
AL
243/* For TDR measurements less than 11 meters, a short pulse should be
244 * used.
245 */
246#define TDR_SHORT_CABLE_LENGTH 11
247
fc879f72
AL
248#define MII_VCT7_PAIR_0_DISTANCE 0x10
249#define MII_VCT7_PAIR_1_DISTANCE 0x11
250#define MII_VCT7_PAIR_2_DISTANCE 0x12
251#define MII_VCT7_PAIR_3_DISTANCE 0x13
252
253#define MII_VCT7_RESULTS 0x14
254#define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
255#define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
256#define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
257#define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
258#define MII_VCT7_RESULTS_PAIR3_SHIFT 12
259#define MII_VCT7_RESULTS_PAIR2_SHIFT 8
260#define MII_VCT7_RESULTS_PAIR1_SHIFT 4
261#define MII_VCT7_RESULTS_PAIR0_SHIFT 0
262#define MII_VCT7_RESULTS_INVALID 0
263#define MII_VCT7_RESULTS_OK 1
264#define MII_VCT7_RESULTS_OPEN 2
265#define MII_VCT7_RESULTS_SAME_SHORT 3
266#define MII_VCT7_RESULTS_CROSS_SHORT 4
267#define MII_VCT7_RESULTS_BUSY 9
268
269#define MII_VCT7_CTRL 0x15
270#define MII_VCT7_CTRL_RUN_NOW BIT(15)
271#define MII_VCT7_CTRL_RUN_ANEG BIT(14)
272#define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
273#define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
274#define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
275#define MII_VCT7_CTRL_METERS BIT(10)
276#define MII_VCT7_CTRL_CENTIMETERS 0
277
8cf8b87b 278#define LPA_PAUSE_FIBER 0x180
6cfb3bcc
CAC
279#define LPA_PAUSE_ASYM_FIBER 0x100
280
2170fef7 281#define NB_FIBER_STATS 1
6cfb3bcc 282
00db8189
AF
283MODULE_DESCRIPTION("Marvell PHY driver");
284MODULE_AUTHOR("Andy Fleming");
285MODULE_LICENSE("GPL");
286
d2fa47d9
AL
287struct marvell_hw_stat {
288 const char *string;
289 u8 page;
290 u8 reg;
291 u8 bits;
292};
293
294static struct marvell_hw_stat marvell_hw_stats[] = {
2170fef7 295 { "phy_receive_errors_copper", 0, 21, 16},
d2fa47d9 296 { "phy_idle_errors", 0, 10, 8 },
2170fef7 297 { "phy_receive_errors_fiber", 1, 21, 16},
d2fa47d9
AL
298};
299
300struct marvell_priv {
301 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
0b04680f
AL
302 char *hwmon_name;
303 struct device *hwmon_dev;
0c9bcc1d 304 bool cable_test_tdr;
f2bc8ad3
AL
305 u32 first;
306 u32 last;
307 u32 step;
308 s8 pair;
d2fa47d9
AL
309};
310
424ca4c5 311static int marvell_read_page(struct phy_device *phydev)
6427bb2d 312{
424ca4c5 313 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
6427bb2d
AL
314}
315
424ca4c5 316static int marvell_write_page(struct phy_device *phydev, int page)
6427bb2d 317{
424ca4c5 318 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
6427bb2d
AL
319}
320
424ca4c5 321static int marvell_set_page(struct phy_device *phydev, int page)
53798328 322{
424ca4c5 323 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
53798328
AL
324}
325
00db8189
AF
326static int marvell_ack_interrupt(struct phy_device *phydev)
327{
328 int err;
329
330 /* Clear the interrupts by reading the reg */
331 err = phy_read(phydev, MII_M1011_IEVENT);
332
333 if (err < 0)
334 return err;
335
336 return 0;
337}
338
339static int marvell_config_intr(struct phy_device *phydev)
340{
341 int err;
342
1f6d0f26
IC
343 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
344 err = marvell_ack_interrupt(phydev);
345 if (err)
346 return err;
347
23beb38f
AL
348 err = phy_write(phydev, MII_M1011_IMASK,
349 MII_M1011_IMASK_INIT);
1f6d0f26 350 } else {
23beb38f
AL
351 err = phy_write(phydev, MII_M1011_IMASK,
352 MII_M1011_IMASK_CLEAR);
1f6d0f26
IC
353 if (err)
354 return err;
355
356 err = marvell_ack_interrupt(phydev);
357 }
00db8189
AF
358
359 return err;
360}
361
a0723b37
IC
362static irqreturn_t marvell_handle_interrupt(struct phy_device *phydev)
363{
364 int irq_status;
365
366 irq_status = phy_read(phydev, MII_M1011_IEVENT);
367 if (irq_status < 0) {
368 phy_error(phydev);
369 return IRQ_NONE;
370 }
371
372 if (!(irq_status & MII_M1011_IMASK_INIT))
373 return IRQ_NONE;
374
375 phy_trigger_machine(phydev);
376
377 return IRQ_HANDLED;
378}
379
239aa55b
DT
380static int marvell_set_polarity(struct phy_device *phydev, int polarity)
381{
feb938fa 382 u16 val;
239aa55b 383
239aa55b
DT
384 switch (polarity) {
385 case ETH_TP_MDI:
feb938fa 386 val = MII_M1011_PHY_SCR_MDI;
239aa55b
DT
387 break;
388 case ETH_TP_MDI_X:
feb938fa 389 val = MII_M1011_PHY_SCR_MDI_X;
239aa55b
DT
390 break;
391 case ETH_TP_MDI_AUTO:
392 case ETH_TP_MDI_INVALID:
393 default:
feb938fa 394 val = MII_M1011_PHY_SCR_AUTO_CROSS;
239aa55b
DT
395 break;
396 }
397
feb938fa
RK
398 return phy_modify_changed(phydev, MII_M1011_PHY_SCR,
399 MII_M1011_PHY_SCR_AUTO_CROSS, val);
239aa55b
DT
400}
401
00db8189
AF
402static int marvell_config_aneg(struct phy_device *phydev)
403{
d6ab9336 404 int changed = 0;
00db8189
AF
405 int err;
406
4e26c5c3 407 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
76884679
AF
408 if (err < 0)
409 return err;
410
d6ab9336
FF
411 changed = err;
412
76884679
AF
413 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
414 MII_M1111_PHY_LED_DIRECT);
415 if (err < 0)
416 return err;
00db8189
AF
417
418 err = genphy_config_aneg(phydev);
8ff44985
AV
419 if (err < 0)
420 return err;
00db8189 421
d6ab9336 422 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
0c3439bc 423 /* A write to speed/duplex bits (that is performed by
8ff44985
AV
424 * genphy_config_aneg() call above) must be followed by
425 * a software reset. Otherwise, the write has no effect.
426 */
34386344 427 err = genphy_soft_reset(phydev);
8ff44985
AV
428 if (err < 0)
429 return err;
430 }
431
432 return 0;
00db8189
AF
433}
434
f2899788
AL
435static int m88e1101_config_aneg(struct phy_device *phydev)
436{
437 int err;
438
439 /* This Marvell PHY has an errata which requires
440 * that certain registers get written in order
441 * to restart autonegotiation
442 */
34386344 443 err = genphy_soft_reset(phydev);
f2899788
AL
444 if (err < 0)
445 return err;
446
447 err = phy_write(phydev, 0x1d, 0x1f);
448 if (err < 0)
449 return err;
450
451 err = phy_write(phydev, 0x1e, 0x200c);
452 if (err < 0)
453 return err;
454
455 err = phy_write(phydev, 0x1d, 0x5);
456 if (err < 0)
457 return err;
458
459 err = phy_write(phydev, 0x1e, 0);
460 if (err < 0)
461 return err;
462
463 err = phy_write(phydev, 0x1e, 0x100);
464 if (err < 0)
465 return err;
466
467 return marvell_config_aneg(phydev);
468}
469
5cd119d9 470#if IS_ENABLED(CONFIG_OF_MDIO)
0c3439bc 471/* Set and/or override some configuration registers based on the
cf41a51d
DD
472 * marvell,reg-init property stored in the of_node for the phydev.
473 *
474 * marvell,reg-init = <reg-page reg mask value>,...;
475 *
476 * There may be one or more sets of <reg-page reg mask value>:
477 *
478 * reg-page: which register bank to use.
479 * reg: the register.
480 * mask: if non-zero, ANDed with existing register value.
481 * value: ORed with the masked value and written to the regiser.
482 *
483 */
484static int marvell_of_reg_init(struct phy_device *phydev)
485{
486 const __be32 *paddr;
424ca4c5 487 int len, i, saved_page, current_page, ret = 0;
cf41a51d 488
e5a03bfd 489 if (!phydev->mdio.dev.of_node)
cf41a51d
DD
490 return 0;
491
e5a03bfd
AL
492 paddr = of_get_property(phydev->mdio.dev.of_node,
493 "marvell,reg-init", &len);
cf41a51d
DD
494 if (!paddr || len < (4 * sizeof(*paddr)))
495 return 0;
496
424ca4c5 497 saved_page = phy_save_page(phydev);
cf41a51d 498 if (saved_page < 0)
424ca4c5 499 goto err;
cf41a51d
DD
500 current_page = saved_page;
501
cf41a51d
DD
502 len /= sizeof(*paddr);
503 for (i = 0; i < len - 3; i += 4) {
6427bb2d 504 u16 page = be32_to_cpup(paddr + i);
cf41a51d
DD
505 u16 reg = be32_to_cpup(paddr + i + 1);
506 u16 mask = be32_to_cpup(paddr + i + 2);
507 u16 val_bits = be32_to_cpup(paddr + i + 3);
508 int val;
509
6427bb2d
AL
510 if (page != current_page) {
511 current_page = page;
424ca4c5 512 ret = marvell_write_page(phydev, page);
cf41a51d
DD
513 if (ret < 0)
514 goto err;
515 }
516
517 val = 0;
518 if (mask) {
424ca4c5 519 val = __phy_read(phydev, reg);
cf41a51d
DD
520 if (val < 0) {
521 ret = val;
522 goto err;
523 }
524 val &= mask;
525 }
526 val |= val_bits;
527
424ca4c5 528 ret = __phy_write(phydev, reg, val);
cf41a51d
DD
529 if (ret < 0)
530 goto err;
cf41a51d
DD
531 }
532err:
424ca4c5 533 return phy_restore_page(phydev, saved_page, ret);
cf41a51d
DD
534}
535#else
536static int marvell_of_reg_init(struct phy_device *phydev)
537{
538 return 0;
539}
540#endif /* CONFIG_OF_MDIO */
541
864dc729 542static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
140bc929 543{
424ca4c5 544 int mscr;
864dc729
AL
545
546 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
424ca4c5
RK
547 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
548 MII_88E1121_PHY_MSCR_TX_DELAY;
864dc729 549 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
424ca4c5 550 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
864dc729 551 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
424ca4c5
RK
552 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
553 else
554 mscr = 0;
140bc929 555
9338c17e
PP
556 return phy_modify_paged_changed(phydev, MII_MARVELL_MSCR_PAGE,
557 MII_88E1121_PHY_MSCR_REG,
558 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
864dc729
AL
559}
560
561static int m88e1121_config_aneg(struct phy_device *phydev)
562{
d6ab9336 563 int changed = 0;
864dc729
AL
564 int err = 0;
565
566 if (phy_interface_is_rgmii(phydev)) {
567 err = m88e1121_config_aneg_rgmii_delays(phydev);
fea23fb5 568 if (err < 0)
864dc729
AL
569 return err;
570 }
571
9338c17e
PP
572 changed = err;
573
d6ab9336 574 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
140bc929
SP
575 if (err < 0)
576 return err;
577
9338c17e 578 changed |= err;
d6ab9336
FF
579
580 err = genphy_config_aneg(phydev);
140bc929
SP
581 if (err < 0)
582 return err;
583
4b1bd697 584 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
d6ab9336
FF
585 /* A software reset is used to ensure a "commit" of the
586 * changes is done.
587 */
588 err = genphy_soft_reset(phydev);
589 if (err < 0)
590 return err;
591 }
592
593 return 0;
140bc929
SP
594}
595
337ac9d5 596static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259 597{
424ca4c5 598 int err;
3ff1c259 599
424ca4c5
RK
600 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
601 MII_88E1318S_PHY_MSCR1_REG,
602 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
3ff1c259
CC
603 if (err < 0)
604 return err;
605
606 return m88e1121_config_aneg(phydev);
607}
608
78301ebe 609/**
3c1bcc86
AL
610 * linkmode_adv_to_fiber_adv_t
611 * @advertise: the linkmode advertisement settings
78301ebe 612 *
3c1bcc86
AL
613 * A small helper function that translates linkmode advertisement
614 * settings to phy autonegotiation advertisements for the MII_ADV
615 * register for fiber link.
78301ebe 616 */
3c1bcc86 617static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
78301ebe
CAC
618{
619 u32 result = 0;
620
3c1bcc86 621 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
20ecf424 622 result |= ADVERTISE_1000XHALF;
3c1bcc86 623 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
20ecf424 624 result |= ADVERTISE_1000XFULL;
78301ebe 625
3c1bcc86
AL
626 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
627 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
20ecf424 628 result |= ADVERTISE_1000XPSE_ASYM;
3c1bcc86 629 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
20ecf424 630 result |= ADVERTISE_1000XPAUSE;
78301ebe
CAC
631
632 return result;
633}
634
635/**
636 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
637 * @phydev: target phy_device struct
638 *
639 * Description: If auto-negotiation is enabled, we configure the
640 * advertising, and then restart auto-negotiation. If it is not
641 * enabled, then we write the BMCR. Adapted for fiber link in
642 * some Marvell's devices.
643 */
644static int marvell_config_aneg_fiber(struct phy_device *phydev)
645{
646 int changed = 0;
647 int err;
9f4bae70 648 u16 adv;
78301ebe
CAC
649
650 if (phydev->autoneg != AUTONEG_ENABLE)
651 return genphy_setup_forced(phydev);
652
653 /* Only allow advertising what this PHY supports */
3c1bcc86
AL
654 linkmode_and(phydev->advertising, phydev->advertising,
655 phydev->supported);
78301ebe 656
9f4bae70 657 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
78301ebe 658
9f4bae70
RK
659 /* Setup fiber advertisement */
660 err = phy_modify_changed(phydev, MII_ADVERTISE,
661 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
662 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
663 adv);
664 if (err < 0)
665 return err;
666 if (err > 0)
78301ebe 667 changed = 1;
78301ebe 668
b5abac2d 669 return genphy_check_and_restart_aneg(phydev, changed);
78301ebe
CAC
670}
671
1887023a
RH
672static int m88e1111_config_aneg(struct phy_device *phydev)
673{
674 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
675 int err;
676
677 if (extsr < 0)
678 return extsr;
679
680 /* If not using SGMII or copper 1000BaseX modes, use normal process.
681 * Steps below are only required for these modes.
682 */
683 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
684 (extsr & MII_M1111_HWCFG_MODE_MASK) !=
685 MII_M1111_HWCFG_MODE_COPPER_1000X_AN)
686 return marvell_config_aneg(phydev);
687
688 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
689 if (err < 0)
690 goto error;
691
692 /* Configure the copper link first */
693 err = marvell_config_aneg(phydev);
694 if (err < 0)
695 goto error;
696
1887023a
RH
697 /* Then the fiber link */
698 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
699 if (err < 0)
700 goto error;
701
06b334f0
RH
702 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
703 /* Do not touch the fiber advertisement if we're in copper->sgmii mode.
704 * Just ensure that SGMII-side autonegotiation is enabled.
705 * If we switched from some other mode to SGMII it may not be.
706 */
707 err = genphy_check_and_restart_aneg(phydev, false);
708 else
709 err = marvell_config_aneg_fiber(phydev);
1887023a
RH
710 if (err < 0)
711 goto error;
712
713 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
714
715error:
716 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
717 return err;
718}
719
10e24caa
MS
720static int m88e1510_config_aneg(struct phy_device *phydev)
721{
722 int err;
723
52295666 724 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe
CAC
725 if (err < 0)
726 goto error;
727
728 /* Configure the copper link first */
10e24caa
MS
729 err = m88e1318_config_aneg(phydev);
730 if (err < 0)
78301ebe 731 goto error;
10e24caa 732
de9c4e06
RK
733 /* Do not touch the fiber page if we're in copper->sgmii mode */
734 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
735 return 0;
736
78301ebe 737 /* Then the fiber link */
52295666 738 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
78301ebe
CAC
739 if (err < 0)
740 goto error;
741
742 err = marvell_config_aneg_fiber(phydev);
743 if (err < 0)
744 goto error;
745
52295666 746 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe
CAC
747
748error:
52295666 749 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe 750 return err;
79be1a1c
CG
751}
752
07777246
WD
753static void marvell_config_led(struct phy_device *phydev)
754{
755 u16 def_config;
756 int err;
757
758 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
759 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
760 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
761 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
762 def_config = MII_88E1121_PHY_LED_DEF;
763 break;
764 /* Default PHY LED config:
765 * LED[0] .. 1000Mbps Link
766 * LED[1] .. 100Mbps Link
767 * LED[2] .. Blink, Activity
768 */
769 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
a93f7fe1
JS
770 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
771 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
772 else
773 def_config = MII_88E1510_PHY_LED_DEF;
07777246
WD
774 break;
775 default:
776 return;
777 }
778
779 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
780 def_config);
781 if (err < 0)
ab2a605f 782 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
07777246
WD
783}
784
79be1a1c
CG
785static int marvell_config_init(struct phy_device *phydev)
786{
85bec4bc 787 /* Set default LED */
07777246
WD
788 marvell_config_led(phydev);
789
79be1a1c 790 /* Set registers from marvell,reg-init DT property */
10e24caa
MS
791 return marvell_of_reg_init(phydev);
792}
793
6b358aed
SH
794static int m88e3016_config_init(struct phy_device *phydev)
795{
fea23fb5 796 int ret;
6b358aed
SH
797
798 /* Enable Scrambler and Auto-Crossover */
fea23fb5 799 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
f102852f 800 MII_88E3016_DISABLE_SCRAMBLER,
fea23fb5
RK
801 MII_88E3016_AUTO_MDIX_CROSSOVER);
802 if (ret < 0)
803 return ret;
6b358aed 804
79be1a1c 805 return marvell_config_init(phydev);
6b358aed
SH
806}
807
865b813a
AL
808static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
809 u16 mode,
810 int fibre_copper_auto)
811{
865b813a 812 if (fibre_copper_auto)
fea23fb5 813 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
865b813a 814
fea23fb5 815 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
f102852f
RK
816 MII_M1111_HWCFG_MODE_MASK |
817 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
818 MII_M1111_HWCFG_FIBER_COPPER_RES,
fea23fb5 819 mode);
865b813a
AL
820}
821
61111598 822static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
895ee682 823{
fea23fb5 824 int delay;
895ee682 825
16d4d650
WL
826 switch (phydev->interface) {
827 case PHY_INTERFACE_MODE_RGMII_ID:
fea23fb5 828 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
16d4d650
WL
829 break;
830 case PHY_INTERFACE_MODE_RGMII_RXID:
fea23fb5 831 delay = MII_M1111_RGMII_RX_DELAY;
16d4d650
WL
832 break;
833 case PHY_INTERFACE_MODE_RGMII_TXID:
fea23fb5 834 delay = MII_M1111_RGMII_TX_DELAY;
16d4d650
WL
835 break;
836 default:
fea23fb5 837 delay = 0;
16d4d650 838 break;
e1dde8dc 839 }
895ee682 840
fea23fb5 841 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
f102852f 842 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
fea23fb5 843 delay);
61111598
AL
844}
845
846static int m88e1111_config_init_rgmii(struct phy_device *phydev)
847{
848 int temp;
849 int err;
850
851 err = m88e1111_config_init_rgmii_delays(phydev);
e1dde8dc
AL
852 if (err < 0)
853 return err;
9daf5a76 854
e1dde8dc
AL
855 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
856 if (temp < 0)
857 return temp;
895ee682 858
e1dde8dc 859 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 860
e1dde8dc
AL
861 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
862 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
863 else
864 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682 865
e1dde8dc
AL
866 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
867}
895ee682 868
e1dde8dc
AL
869static int m88e1111_config_init_sgmii(struct phy_device *phydev)
870{
871 int err;
4117b5be 872
865b813a
AL
873 err = m88e1111_config_init_hwcfg_mode(
874 phydev,
875 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
876 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
e1dde8dc
AL
877 if (err < 0)
878 return err;
07151bc9 879
e1dde8dc 880 /* make sure copper is selected */
52295666 881 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
e1dde8dc 882}
5f8cbc13 883
e1dde8dc
AL
884static int m88e1111_config_init_rtbi(struct phy_device *phydev)
885{
61111598 886 int err;
e1dde8dc 887
61111598 888 err = m88e1111_config_init_rgmii_delays(phydev);
fea23fb5 889 if (err < 0)
e1dde8dc
AL
890 return err;
891
865b813a
AL
892 err = m88e1111_config_init_hwcfg_mode(
893 phydev,
894 MII_M1111_HWCFG_MODE_RTBI,
895 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
e1dde8dc
AL
896 if (err < 0)
897 return err;
898
899 /* soft reset */
34386344 900 err = genphy_soft_reset(phydev);
e1dde8dc
AL
901 if (err < 0)
902 return err;
903
865b813a
AL
904 return m88e1111_config_init_hwcfg_mode(
905 phydev,
906 MII_M1111_HWCFG_MODE_RTBI,
907 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
e1dde8dc
AL
908}
909
1887023a
RH
910static int m88e1111_config_init_1000basex(struct phy_device *phydev)
911{
912 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
913 int err, mode;
914
915 if (extsr < 0)
916 return extsr;
917
918 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled */
919 mode = extsr & MII_M1111_HWCFG_MODE_MASK;
920 if (mode == MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN) {
921 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
922 MII_M1111_HWCFG_MODE_MASK |
923 MII_M1111_HWCFG_SERIAL_AN_BYPASS,
924 MII_M1111_HWCFG_MODE_COPPER_1000X_AN |
925 MII_M1111_HWCFG_SERIAL_AN_BYPASS);
926 if (err < 0)
927 return err;
928 }
929 return 0;
930}
931
e1dde8dc
AL
932static int m88e1111_config_init(struct phy_device *phydev)
933{
934 int err;
935
936 if (phy_interface_is_rgmii(phydev)) {
937 err = m88e1111_config_init_rgmii(phydev);
fea23fb5 938 if (err < 0)
5f8cbc13 939 return err;
e1dde8dc 940 }
5f8cbc13 941
e1dde8dc
AL
942 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
943 err = m88e1111_config_init_sgmii(phydev);
5f8cbc13
LYB
944 if (err < 0)
945 return err;
e1dde8dc 946 }
5f8cbc13 947
e1dde8dc
AL
948 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
949 err = m88e1111_config_init_rtbi(phydev);
5f8cbc13
LYB
950 if (err < 0)
951 return err;
952 }
953
1887023a
RH
954 if (phydev->interface == PHY_INTERFACE_MODE_1000BASEX) {
955 err = m88e1111_config_init_1000basex(phydev);
956 if (err < 0)
957 return err;
958 }
959
cf41a51d
DD
960 err = marvell_of_reg_init(phydev);
961 if (err < 0)
962 return err;
5f8cbc13 963
34386344 964 return genphy_soft_reset(phydev);
895ee682
KP
965}
966
5c6bc519
HK
967static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
968{
969 int val, cnt, enable;
970
971 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
972 if (val < 0)
973 return val;
974
975 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
976 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
977
978 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
979
980 return 0;
981}
982
983static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
984{
e7679c55 985 int val, err;
5c6bc519
HK
986
987 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
988 return -E2BIG;
989
e7679c55
MK
990 if (!cnt) {
991 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
992 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
993 } else {
994 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
995 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
5c6bc519 996
e7679c55
MK
997 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
998 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
999 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
1000 val);
1001 }
5c6bc519 1002
e7679c55
MK
1003 if (err < 0)
1004 return err;
1005
1006 return genphy_soft_reset(phydev);
5c6bc519
HK
1007}
1008
1009static int m88e1111_get_tunable(struct phy_device *phydev,
1010 struct ethtool_tunable *tuna, void *data)
1011{
1012 switch (tuna->id) {
1013 case ETHTOOL_PHY_DOWNSHIFT:
1014 return m88e1111_get_downshift(phydev, data);
1015 default:
1016 return -EOPNOTSUPP;
1017 }
1018}
1019
1020static int m88e1111_set_tunable(struct phy_device *phydev,
1021 struct ethtool_tunable *tuna, const void *data)
1022{
1023 switch (tuna->id) {
1024 case ETHTOOL_PHY_DOWNSHIFT:
1025 return m88e1111_set_downshift(phydev, *(const u8 *)data);
1026 default:
1027 return -EOPNOTSUPP;
1028 }
1029}
1030
911af5e1 1031static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
a3bdfce7
HK
1032{
1033 int val, cnt, enable;
1034
1035 val = phy_read(phydev, MII_M1011_PHY_SCR);
1036 if (val < 0)
1037 return val;
1038
1039 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
f8d975be 1040 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
a3bdfce7
HK
1041
1042 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1043
1044 return 0;
1045}
1046
911af5e1 1047static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
a3bdfce7 1048{
990875b2 1049 int val, err;
a3bdfce7
HK
1050
1051 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
1052 return -E2BIG;
1053
990875b2
MK
1054 if (!cnt) {
1055 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
1056 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
1057 } else {
1058 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
1059 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
a3bdfce7 1060
990875b2
MK
1061 err = phy_modify(phydev, MII_M1011_PHY_SCR,
1062 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
1063 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
1064 val);
1065 }
a3bdfce7 1066
990875b2
MK
1067 if (err < 0)
1068 return err;
1069
1070 return genphy_soft_reset(phydev);
a3bdfce7
HK
1071}
1072
911af5e1 1073static int m88e1011_get_tunable(struct phy_device *phydev,
a3bdfce7
HK
1074 struct ethtool_tunable *tuna, void *data)
1075{
1076 switch (tuna->id) {
1077 case ETHTOOL_PHY_DOWNSHIFT:
911af5e1 1078 return m88e1011_get_downshift(phydev, data);
a3bdfce7
HK
1079 default:
1080 return -EOPNOTSUPP;
1081 }
1082}
1083
911af5e1 1084static int m88e1011_set_tunable(struct phy_device *phydev,
a3bdfce7
HK
1085 struct ethtool_tunable *tuna, const void *data)
1086{
1087 switch (tuna->id) {
1088 case ETHTOOL_PHY_DOWNSHIFT:
911af5e1 1089 return m88e1011_set_downshift(phydev, *(const u8 *)data);
a3bdfce7
HK
1090 default:
1091 return -EOPNOTSUPP;
1092 }
1093}
1094
8385b1f0
MK
1095static int m88e1112_config_init(struct phy_device *phydev)
1096{
1097 int err;
1098
1099 err = m88e1011_set_downshift(phydev, 3);
1100 if (err < 0)
1101 return err;
1102
1103 return m88e1111_config_init(phydev);
1104}
1105
1106static int m88e1111gbe_config_init(struct phy_device *phydev)
1107{
1108 int err;
1109
1110 err = m88e1111_set_downshift(phydev, 3);
1111 if (err < 0)
1112 return err;
1113
1114 return m88e1111_config_init(phydev);
1115}
1116
1117static int marvell_1011gbe_config_init(struct phy_device *phydev)
1118{
1119 int err;
1120
1121 err = m88e1011_set_downshift(phydev, 3);
1122 if (err < 0)
1123 return err;
1124
1125 return marvell_config_init(phydev);
1126}
e2d861cc
HK
1127static int m88e1116r_config_init(struct phy_device *phydev)
1128{
1129 int err;
1130
1131 err = genphy_soft_reset(phydev);
1132 if (err < 0)
1133 return err;
1134
1135 msleep(500);
1136
1137 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1138 if (err < 0)
1139 return err;
1140
1141 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1142 if (err < 0)
1143 return err;
1144
911af5e1 1145 err = m88e1011_set_downshift(phydev, 8);
e2d861cc
HK
1146 if (err < 0)
1147 return err;
1148
1149 if (phy_interface_is_rgmii(phydev)) {
1150 err = m88e1121_config_aneg_rgmii_delays(phydev);
1151 if (err < 0)
1152 return err;
1153 }
1154
1155 err = genphy_soft_reset(phydev);
1156 if (err < 0)
1157 return err;
1158
1159 return marvell_config_init(phydev);
1160}
1161
dd9a122a
EH
1162static int m88e1318_config_init(struct phy_device *phydev)
1163{
1164 if (phy_interrupt_is_valid(phydev)) {
1165 int err = phy_modify_paged(
1166 phydev, MII_MARVELL_LED_PAGE,
1167 MII_88E1318S_PHY_LED_TCR,
1168 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1169 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1170 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1171 if (err < 0)
1172 return err;
1173 }
1174
07777246 1175 return marvell_config_init(phydev);
dd9a122a
EH
1176}
1177
407353ec
CG
1178static int m88e1510_config_init(struct phy_device *phydev)
1179{
1180 int err;
407353ec
CG
1181
1182 /* SGMII-to-Copper mode initialization */
1183 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1184 /* Select page 18 */
6427bb2d 1185 err = marvell_set_page(phydev, 18);
407353ec
CG
1186 if (err < 0)
1187 return err;
1188
1189 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
fea23fb5 1190 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
f102852f 1191 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
fea23fb5 1192 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
407353ec
CG
1193 if (err < 0)
1194 return err;
1195
1196 /* PHY reset is necessary after changing MODE[2:0] */
832913c3
YD
1197 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
1198 MII_88E1510_GEN_CTRL_REG_1_RESET);
407353ec
CG
1199 if (err < 0)
1200 return err;
1201
1202 /* Reset page selection */
52295666 1203 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
407353ec
CG
1204 if (err < 0)
1205 return err;
1206 }
8385b1f0
MK
1207 err = m88e1011_set_downshift(phydev, 3);
1208 if (err < 0)
1209 return err;
407353ec 1210
dd9a122a 1211 return m88e1318_config_init(phydev);
407353ec
CG
1212}
1213
605f196e
RM
1214static int m88e1118_config_aneg(struct phy_device *phydev)
1215{
1216 int err;
1217
6b42352b 1218 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
605f196e
RM
1219 if (err < 0)
1220 return err;
1221
6b42352b 1222 err = genphy_config_aneg(phydev);
605f196e
RM
1223 if (err < 0)
1224 return err;
1225
6b42352b 1226 return genphy_soft_reset(phydev);
605f196e
RM
1227}
1228
1229static int m88e1118_config_init(struct phy_device *phydev)
1230{
1231 int err;
1232
1233 /* Change address */
52295666 1234 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
605f196e
RM
1235 if (err < 0)
1236 return err;
1237
1238 /* Enable 1000 Mbit */
1239 err = phy_write(phydev, 0x15, 0x1070);
1240 if (err < 0)
1241 return err;
1242
1243 /* Change address */
52295666 1244 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
605f196e
RM
1245 if (err < 0)
1246 return err;
1247
00bf5ce4
RKO
1248 if (phy_interface_is_rgmii(phydev)) {
1249 err = m88e1121_config_aneg_rgmii_delays(phydev);
1250 if (err < 0)
1251 return err;
1252 }
1253
605f196e 1254 /* Adjust LED Control */
2f495c39
BH
1255 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1256 err = phy_write(phydev, 0x10, 0x1100);
1257 else
1258 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM
1259 if (err < 0)
1260 return err;
1261
cf41a51d
DD
1262 err = marvell_of_reg_init(phydev);
1263 if (err < 0)
1264 return err;
1265
605f196e 1266 /* Reset address */
52295666 1267 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
605f196e
RM
1268 if (err < 0)
1269 return err;
1270
34386344 1271 return genphy_soft_reset(phydev);
605f196e
RM
1272}
1273
90600732
DD
1274static int m88e1149_config_init(struct phy_device *phydev)
1275{
1276 int err;
1277
1278 /* Change address */
52295666 1279 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
90600732
DD
1280 if (err < 0)
1281 return err;
1282
1283 /* Enable 1000 Mbit */
1284 err = phy_write(phydev, 0x15, 0x1048);
1285 if (err < 0)
1286 return err;
1287
cf41a51d
DD
1288 err = marvell_of_reg_init(phydev);
1289 if (err < 0)
1290 return err;
1291
90600732 1292 /* Reset address */
52295666 1293 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
90600732
DD
1294 if (err < 0)
1295 return err;
1296
34386344 1297 return genphy_soft_reset(phydev);
90600732
DD
1298}
1299
e1dde8dc
AL
1300static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1301{
1302 int err;
e1dde8dc 1303
61111598 1304 err = m88e1111_config_init_rgmii_delays(phydev);
e1dde8dc
AL
1305 if (err < 0)
1306 return err;
1307
1308 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1309 err = phy_write(phydev, 0x1d, 0x0012);
1310 if (err < 0)
1311 return err;
1312
f102852f 1313 err = phy_modify(phydev, 0x1e, 0x0fc0,
fea23fb5
RK
1314 2 << 9 | /* 36 ohm */
1315 2 << 6); /* 39 ohm */
e1dde8dc
AL
1316 if (err < 0)
1317 return err;
1318
1319 err = phy_write(phydev, 0x1d, 0x3);
1320 if (err < 0)
1321 return err;
1322
1323 err = phy_write(phydev, 0x1e, 0x8000);
1324 }
1325 return err;
1326}
1327
1328static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1329{
865b813a
AL
1330 return m88e1111_config_init_hwcfg_mode(
1331 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1332 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
e1dde8dc
AL
1333}
1334
76884679
AF
1335static int m88e1145_config_init(struct phy_device *phydev)
1336{
1337 int err;
1338
1339 /* Take care of errata E0 & E1 */
1340 err = phy_write(phydev, 0x1d, 0x001b);
1341 if (err < 0)
1342 return err;
1343
1344 err = phy_write(phydev, 0x1e, 0x418f);
1345 if (err < 0)
1346 return err;
1347
1348 err = phy_write(phydev, 0x1d, 0x0016);
1349 if (err < 0)
1350 return err;
1351
1352 err = phy_write(phydev, 0x1e, 0xa2da);
1353 if (err < 0)
1354 return err;
1355
895ee682 1356 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
e1dde8dc 1357 err = m88e1145_config_init_rgmii(phydev);
76884679
AF
1358 if (err < 0)
1359 return err;
76884679
AF
1360 }
1361
b0224175 1362 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
e1dde8dc 1363 err = m88e1145_config_init_sgmii(phydev);
b0224175
VND
1364 if (err < 0)
1365 return err;
1366 }
8385b1f0
MK
1367 err = m88e1111_set_downshift(phydev, 3);
1368 if (err < 0)
1369 return err;
b0224175 1370
cf41a51d
DD
1371 err = marvell_of_reg_init(phydev);
1372 if (err < 0)
1373 return err;
1374
76884679
AF
1375 return 0;
1376}
00db8189 1377
69f42be8
HK
1378static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1379{
1380 int val;
1381
1382 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1383 if (val < 0)
1384 return val;
1385
1386 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1387 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1388 return 0;
1389 }
1390
1391 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1392
1393 switch (val) {
1394 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1395 *msecs = 0;
1396 break;
1397 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1398 *msecs = 10;
1399 break;
1400 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1401 *msecs = 20;
1402 break;
1403 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1404 *msecs = 40;
1405 break;
1406 default:
1407 return -EINVAL;
1408 }
1409
1410 return 0;
1411}
1412
1413static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1414{
1415 struct ethtool_eee eee;
1416 int val, ret;
1417
1418 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1419 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1420 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1421
1422 /* According to the Marvell data sheet EEE must be disabled for
1423 * Fast Link Down detection to work properly
1424 */
1425 ret = phy_ethtool_get_eee(phydev, &eee);
1426 if (!ret && eee.eee_enabled) {
1427 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1428 return -EBUSY;
1429 }
1430
1431 if (*msecs <= 5)
1432 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1433 else if (*msecs <= 15)
1434 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1435 else if (*msecs <= 30)
1436 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1437 else
1438 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1439
1440 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1441
1442 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1443 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1444 if (ret)
1445 return ret;
1446
1447 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1448 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1449}
1450
1451static int m88e1540_get_tunable(struct phy_device *phydev,
1452 struct ethtool_tunable *tuna, void *data)
1453{
1454 switch (tuna->id) {
1455 case ETHTOOL_PHY_FAST_LINK_DOWN:
1456 return m88e1540_get_fld(phydev, data);
a3bdfce7 1457 case ETHTOOL_PHY_DOWNSHIFT:
911af5e1 1458 return m88e1011_get_downshift(phydev, data);
69f42be8
HK
1459 default:
1460 return -EOPNOTSUPP;
1461 }
1462}
1463
1464static int m88e1540_set_tunable(struct phy_device *phydev,
1465 struct ethtool_tunable *tuna, const void *data)
1466{
1467 switch (tuna->id) {
1468 case ETHTOOL_PHY_FAST_LINK_DOWN:
1469 return m88e1540_set_fld(phydev, data);
a3bdfce7 1470 case ETHTOOL_PHY_DOWNSHIFT:
911af5e1 1471 return m88e1011_set_downshift(phydev, *(const u8 *)data);
69f42be8
HK
1472 default:
1473 return -EOPNOTSUPP;
1474 }
1475}
1476
8cbcdc1a
AL
1477/* The VOD can be out of specification on link up. Poke an
1478 * undocumented register, in an undocumented page, with a magic value
1479 * to fix this.
1480 */
1481static int m88e6390_errata(struct phy_device *phydev)
1482{
1483 int err;
1484
1485 err = phy_write(phydev, MII_BMCR,
1486 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1487 if (err)
1488 return err;
1489
1490 usleep_range(300, 400);
1491
1492 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1493 if (err)
1494 return err;
1495
1496 return genphy_soft_reset(phydev);
1497}
1498
1499static int m88e6390_config_aneg(struct phy_device *phydev)
1500{
1501 int err;
1502
1503 err = m88e6390_errata(phydev);
1504 if (err)
1505 return err;
1506
1507 return m88e1510_config_aneg(phydev);
1508}
1509
6cfb3bcc 1510/**
ab9cb729 1511 * fiber_lpa_mod_linkmode_lpa_t
c0ec3c27 1512 * @advertising: the linkmode advertisement settings
6cfb3bcc
CAC
1513 * @lpa: value of the MII_LPA register for fiber link
1514 *
ab9cb729
AL
1515 * A small helper function that translates MII_LPA bits to linkmode LP
1516 * advertisement settings. Other bits in advertising are left
1517 * unchanged.
6cfb3bcc 1518 */
ab9cb729 1519static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
6cfb3bcc 1520{
ab9cb729 1521 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
20ecf424 1522 advertising, lpa & LPA_1000XHALF);
ab9cb729
AL
1523
1524 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
20ecf424 1525 advertising, lpa & LPA_1000XFULL);
6cfb3bcc
CAC
1526}
1527
e1dde8dc 1528static int marvell_read_status_page_an(struct phy_device *phydev,
d2004e27 1529 int fiber, int status)
e1dde8dc 1530{
e1dde8dc 1531 int lpa;
fcf1f59a 1532 int err;
e1dde8dc 1533
3b72f84f
CG
1534 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1535 phydev->link = 0;
1536 return 0;
1537 }
1538
1539 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1540 phydev->duplex = DUPLEX_FULL;
1541 else
1542 phydev->duplex = DUPLEX_HALF;
1543
1544 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1545 case MII_M1011_PHY_STATUS_1000:
1546 phydev->speed = SPEED_1000;
1547 break;
1548
1549 case MII_M1011_PHY_STATUS_100:
1550 phydev->speed = SPEED_100;
1551 break;
1552
1553 default:
1554 phydev->speed = SPEED_10;
1555 break;
1556 }
1557
e1dde8dc 1558 if (!fiber) {
fcf1f59a
RK
1559 err = genphy_read_lpa(phydev);
1560 if (err < 0)
1561 return err;
e1dde8dc 1562
af006240 1563 phy_resolve_aneg_pause(phydev);
e1dde8dc 1564 } else {
fcf1f59a
RK
1565 lpa = phy_read(phydev, MII_LPA);
1566 if (lpa < 0)
1567 return lpa;
1568
e1dde8dc 1569 /* The fiber link is only 1000M capable */
ab9cb729 1570 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
e1dde8dc
AL
1571
1572 if (phydev->duplex == DUPLEX_FULL) {
1573 if (!(lpa & LPA_PAUSE_FIBER)) {
1574 phydev->pause = 0;
1575 phydev->asym_pause = 0;
1576 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1577 phydev->pause = 1;
1578 phydev->asym_pause = 1;
1579 } else {
1580 phydev->pause = 1;
1581 phydev->asym_pause = 0;
1582 }
1583 }
1584 }
fcf1f59a 1585
e1dde8dc
AL
1586 return 0;
1587}
1588
6cfb3bcc 1589/* marvell_read_status_page
be937f1f 1590 *
f0c88f9c 1591 * Description:
be937f1f
AS
1592 * Check the link, then figure out the current state
1593 * by comparing what we advertise with what the link partner
1594 * advertises. Start by checking the gigabit possibilities,
1595 * then move on to 10/100.
1596 */
6cfb3bcc 1597static int marvell_read_status_page(struct phy_device *phydev, int page)
be937f1f 1598{
d2004e27 1599 int status;
6cfb3bcc 1600 int fiber;
e1dde8dc 1601 int err;
be937f1f 1602
d2004e27
RK
1603 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1604 if (status < 0)
1605 return status;
1606
1607 /* Use the generic register for copper link status,
1608 * and the PHY status register for fiber link status.
0c3439bc 1609 */
d2004e27
RK
1610 if (page == MII_MARVELL_FIBER_PAGE) {
1611 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1612 } else {
1613 err = genphy_update_link(phydev);
1614 if (err)
1615 return err;
1616 }
1617
52295666 1618 if (page == MII_MARVELL_FIBER_PAGE)
6cfb3bcc
CAC
1619 fiber = 1;
1620 else
1621 fiber = 0;
1622
98f92831
RK
1623 linkmode_zero(phydev->lp_advertising);
1624 phydev->pause = 0;
1625 phydev->asym_pause = 0;
b82cf17f
RK
1626 phydev->speed = SPEED_UNKNOWN;
1627 phydev->duplex = DUPLEX_UNKNOWN;
4217a64e 1628 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
98f92831 1629
e1dde8dc 1630 if (phydev->autoneg == AUTONEG_ENABLE)
d2004e27 1631 err = marvell_read_status_page_an(phydev, fiber, status);
e1dde8dc 1632 else
98f92831 1633 err = genphy_read_status_fixed(phydev);
be937f1f 1634
e1dde8dc 1635 return err;
be937f1f
AS
1636}
1637
6cfb3bcc
CAC
1638/* marvell_read_status
1639 *
1640 * Some Marvell's phys have two modes: fiber and copper.
1641 * Both need status checked.
1642 * Description:
1643 * First, check the fiber link and status.
1644 * If the fiber link is down, check the copper link and status which
1645 * will be the default value if both link are down.
1646 */
1647static int marvell_read_status(struct phy_device *phydev)
1648{
1649 int err;
1650
1651 /* Check the fiber mode first */
3c1bcc86
AL
1652 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1653 phydev->supported) &&
a13c0652 1654 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
52295666 1655 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
6cfb3bcc
CAC
1656 if (err < 0)
1657 goto error;
1658
52295666 1659 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
6cfb3bcc
CAC
1660 if (err < 0)
1661 goto error;
1662
0c3439bc
AL
1663 /* If the fiber link is up, it is the selected and
1664 * used link. In this case, we need to stay in the
1665 * fiber page. Please to be careful about that, avoid
1666 * to restore Copper page in other functions which
1667 * could break the behaviour for some fiber phy like
1668 * 88E1512.
1669 */
6cfb3bcc
CAC
1670 if (phydev->link)
1671 return 0;
1672
1673 /* If fiber link is down, check and save copper mode state */
52295666 1674 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC
1675 if (err < 0)
1676 goto error;
1677 }
1678
52295666 1679 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC
1680
1681error:
52295666 1682 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC
1683 return err;
1684}
3758be3d
CAC
1685
1686/* marvell_suspend
1687 *
1688 * Some Marvell's phys have two modes: fiber and copper.
1689 * Both need to be suspended
1690 */
1691static int marvell_suspend(struct phy_device *phydev)
1692{
1693 int err;
1694
1695 /* Suspend the fiber mode first */
a296f3ae
KC
1696 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1697 phydev->supported)) {
52295666 1698 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
3758be3d
CAC
1699 if (err < 0)
1700 goto error;
1701
1702 /* With the page set, use the generic suspend */
1703 err = genphy_suspend(phydev);
1704 if (err < 0)
1705 goto error;
1706
1707 /* Then, the copper link */
52295666 1708 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC
1709 if (err < 0)
1710 goto error;
1711 }
1712
1713 /* With the page set, use the generic suspend */
1714 return genphy_suspend(phydev);
1715
1716error:
52295666 1717 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC
1718 return err;
1719}
1720
1721/* marvell_resume
1722 *
1723 * Some Marvell's phys have two modes: fiber and copper.
1724 * Both need to be resumed
1725 */
1726static int marvell_resume(struct phy_device *phydev)
1727{
1728 int err;
1729
1730 /* Resume the fiber mode first */
a296f3ae
KC
1731 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1732 phydev->supported)) {
52295666 1733 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
3758be3d
CAC
1734 if (err < 0)
1735 goto error;
1736
1737 /* With the page set, use the generic resume */
1738 err = genphy_resume(phydev);
1739 if (err < 0)
1740 goto error;
1741
1742 /* Then, the copper link */
52295666 1743 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC
1744 if (err < 0)
1745 goto error;
1746 }
1747
1748 /* With the page set, use the generic resume */
1749 return genphy_resume(phydev);
1750
1751error:
52295666 1752 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC
1753 return err;
1754}
1755
6b358aed
SH
1756static int marvell_aneg_done(struct phy_device *phydev)
1757{
1758 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
e69d9ed4 1759
6b358aed
SH
1760 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1761}
1762
23beb38f
AL
1763static void m88e1318_get_wol(struct phy_device *phydev,
1764 struct ethtool_wolinfo *wol)
3871c387 1765{
f4f9dcc3 1766 int ret;
424ca4c5 1767
6164659f 1768 wol->supported = WAKE_MAGIC | WAKE_PHY;
3871c387
MS
1769 wol->wolopts = 0;
1770
f4f9dcc3
JZ
1771 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1772 MII_88E1318S_PHY_WOL_CTRL);
6164659f
SYS
1773 if (ret < 0)
1774 return;
1775
1776 if (ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
3871c387 1777 wol->wolopts |= WAKE_MAGIC;
6164659f
SYS
1778
1779 if (ret & MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE)
1780 wol->wolopts |= WAKE_PHY;
3871c387
MS
1781}
1782
23beb38f
AL
1783static int m88e1318_set_wol(struct phy_device *phydev,
1784 struct ethtool_wolinfo *wol)
3871c387 1785{
424ca4c5 1786 int err = 0, oldpage;
3871c387 1787
424ca4c5
RK
1788 oldpage = phy_save_page(phydev);
1789 if (oldpage < 0)
1790 goto error;
3871c387 1791
6164659f 1792 if (wol->wolopts & (WAKE_MAGIC | WAKE_PHY)) {
3871c387 1793 /* Explicitly switch to page 0x00, just to be sure */
424ca4c5 1794 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
3871c387 1795 if (err < 0)
424ca4c5 1796 goto error;
3871c387 1797
b6a930fa
JH
1798 /* If WOL event happened once, the LED[2] interrupt pin
1799 * will not be cleared unless we reading the interrupt status
1800 * register. If interrupts are in use, the normal interrupt
1801 * handling will clear the WOL event. Clear the WOL event
1802 * before enabling it if !phy_interrupt_is_valid()
1803 */
1804 if (!phy_interrupt_is_valid(phydev))
e0a7328f 1805 __phy_read(phydev, MII_M1011_IEVENT);
b6a930fa 1806
3871c387 1807 /* Enable the WOL interrupt */
832913c3
YD
1808 err = __phy_set_bits(phydev, MII_88E1318S_PHY_CSIER,
1809 MII_88E1318S_PHY_CSIER_WOL_EIE);
3871c387 1810 if (err < 0)
424ca4c5 1811 goto error;
3871c387 1812
424ca4c5 1813 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
3871c387 1814 if (err < 0)
424ca4c5 1815 goto error;
3871c387
MS
1816
1817 /* Setup LED[2] as interrupt pin (active low) */
424ca4c5 1818 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
f102852f 1819 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
424ca4c5
RK
1820 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1821 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
3871c387 1822 if (err < 0)
424ca4c5 1823 goto error;
6164659f 1824 }
3871c387 1825
6164659f 1826 if (wol->wolopts & WAKE_MAGIC) {
424ca4c5 1827 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
3871c387 1828 if (err < 0)
424ca4c5 1829 goto error;
3871c387
MS
1830
1831 /* Store the device address for the magic packet */
424ca4c5 1832 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
3871c387
MS
1833 ((phydev->attached_dev->dev_addr[5] << 8) |
1834 phydev->attached_dev->dev_addr[4]));
1835 if (err < 0)
424ca4c5
RK
1836 goto error;
1837 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
3871c387
MS
1838 ((phydev->attached_dev->dev_addr[3] << 8) |
1839 phydev->attached_dev->dev_addr[2]));
1840 if (err < 0)
424ca4c5
RK
1841 goto error;
1842 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
3871c387
MS
1843 ((phydev->attached_dev->dev_addr[1] << 8) |
1844 phydev->attached_dev->dev_addr[0]));
1845 if (err < 0)
424ca4c5 1846 goto error;
3871c387
MS
1847
1848 /* Clear WOL status and enable magic packet matching */
832913c3
YD
1849 err = __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
1850 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1851 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
3871c387 1852 if (err < 0)
424ca4c5 1853 goto error;
3871c387 1854 } else {
424ca4c5 1855 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
3871c387 1856 if (err < 0)
424ca4c5 1857 goto error;
3871c387
MS
1858
1859 /* Clear WOL status and disable magic packet matching */
424ca4c5 1860 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
f102852f 1861 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
424ca4c5 1862 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
6164659f
SYS
1863 if (err < 0)
1864 goto error;
1865 }
1866
1867 if (wol->wolopts & WAKE_PHY) {
1868 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1869 if (err < 0)
1870 goto error;
1871
1872 /* Clear WOL status and enable link up event */
1873 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL, 0,
1874 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1875 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE);
1876 if (err < 0)
1877 goto error;
1878 } else {
1879 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1880 if (err < 0)
1881 goto error;
1882
1883 /* Clear WOL status and disable link up event */
1884 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1885 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE,
1886 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
3871c387 1887 if (err < 0)
424ca4c5 1888 goto error;
3871c387
MS
1889 }
1890
424ca4c5
RK
1891error:
1892 return phy_restore_page(phydev, oldpage, err);
3871c387
MS
1893}
1894
d2fa47d9
AL
1895static int marvell_get_sset_count(struct phy_device *phydev)
1896{
3c1bcc86
AL
1897 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1898 phydev->supported))
2170fef7
CAC
1899 return ARRAY_SIZE(marvell_hw_stats);
1900 else
1901 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
d2fa47d9
AL
1902}
1903
1904static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1905{
fdfdf867 1906 int count = marvell_get_sset_count(phydev);
d2fa47d9
AL
1907 int i;
1908
fdfdf867 1909 for (i = 0; i < count; i++) {
98409b2b
FF
1910 strlcpy(data + i * ETH_GSTRING_LEN,
1911 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
d2fa47d9
AL
1912 }
1913}
1914
d2fa47d9
AL
1915static u64 marvell_get_stat(struct phy_device *phydev, int i)
1916{
1917 struct marvell_hw_stat stat = marvell_hw_stats[i];
1918 struct marvell_priv *priv = phydev->priv;
424ca4c5 1919 int val;
321b4d4b 1920 u64 ret;
d2fa47d9 1921
424ca4c5 1922 val = phy_read_paged(phydev, stat.page, stat.reg);
d2fa47d9 1923 if (val < 0) {
6c3442f5 1924 ret = U64_MAX;
d2fa47d9
AL
1925 } else {
1926 val = val & ((1 << stat.bits) - 1);
1927 priv->stats[i] += val;
321b4d4b 1928 ret = priv->stats[i];
d2fa47d9
AL
1929 }
1930
321b4d4b 1931 return ret;
d2fa47d9
AL
1932}
1933
1934static void marvell_get_stats(struct phy_device *phydev,
1935 struct ethtool_stats *stats, u64 *data)
1936{
fdfdf867 1937 int count = marvell_get_sset_count(phydev);
d2fa47d9
AL
1938 int i;
1939
fdfdf867 1940 for (i = 0; i < count; i++)
d2fa47d9
AL
1941 data[i] = marvell_get_stat(phydev, i);
1942}
1943
893dfb14
MABI
1944static int m88e1510_loopback(struct phy_device *phydev, bool enable)
1945{
1946 int err;
1947
1948 if (enable) {
1949 u16 bmcr_ctl = 0, mscr2_ctl = 0;
1950
1951 if (phydev->speed == SPEED_1000)
1952 bmcr_ctl = BMCR_SPEED1000;
1953 else if (phydev->speed == SPEED_100)
1954 bmcr_ctl = BMCR_SPEED100;
1955
1956 if (phydev->duplex == DUPLEX_FULL)
1957 bmcr_ctl |= BMCR_FULLDPLX;
1958
1959 err = phy_write(phydev, MII_BMCR, bmcr_ctl);
1960 if (err < 0)
1961 return err;
1962
1963 if (phydev->speed == SPEED_1000)
1964 mscr2_ctl = BMCR_SPEED1000;
1965 else if (phydev->speed == SPEED_100)
1966 mscr2_ctl = BMCR_SPEED100;
1967
1968 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
1969 MII_88E1510_MSCR_2, BMCR_SPEED1000 |
1970 BMCR_SPEED100, mscr2_ctl);
1971 if (err < 0)
1972 return err;
1973
1974 /* Need soft reset to have speed configuration takes effect */
1975 err = genphy_soft_reset(phydev);
1976 if (err < 0)
1977 return err;
1978
1979 /* FIXME: Based on trial and error test, it seem 1G need to have
1980 * delay between soft reset and loopback enablement.
1981 */
1982 if (phydev->speed == SPEED_1000)
1983 msleep(1000);
1984
1985 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
1986 BMCR_LOOPBACK);
1987 } else {
1988 err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
1989 if (err < 0)
1990 return err;
1991
1992 return phy_config_aneg(phydev);
1993 }
1994}
1995
0c9bcc1d
AL
1996static int marvell_vct5_wait_complete(struct phy_device *phydev)
1997{
1998 int i;
1999 int val;
2000
2001 for (i = 0; i < 32; i++) {
a618e86d 2002 val = __phy_read(phydev, MII_VCT5_CTRL);
0c9bcc1d
AL
2003 if (val < 0)
2004 return val;
2005
2006 if (val & MII_VCT5_CTRL_COMPLETE)
2007 return 0;
0c9bcc1d
AL
2008 }
2009
2010 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
2011 return -ETIMEDOUT;
2012}
2013
2014static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
2015{
2016 int amplitude;
2017 int val;
2018 int reg;
2019
2020 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
a618e86d 2021 val = __phy_read(phydev, reg);
0c9bcc1d
AL
2022
2023 if (val < 0)
2024 return 0;
2025
2026 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
2027 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
2028
2029 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
2030 amplitude = -amplitude;
2031
2032 return 1000 * amplitude / 128;
2033}
2034
2035static u32 marvell_vct5_distance2cm(int distance)
2036{
2037 return distance * 805 / 10;
2038}
2039
f2bc8ad3
AL
2040static u32 marvell_vct5_cm2distance(int cm)
2041{
2042 return cm * 10 / 805;
2043}
2044
0c9bcc1d 2045static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
f2bc8ad3 2046 int distance, int pair)
0c9bcc1d 2047{
0c9bcc1d
AL
2048 u16 reg;
2049 int err;
f2bc8ad3
AL
2050 int mV;
2051 int i;
0c9bcc1d 2052
a618e86d
AL
2053 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
2054 distance);
0c9bcc1d
AL
2055 if (err)
2056 return err;
2057
2058 reg = MII_VCT5_CTRL_ENABLE |
2059 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2060 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2061 MII_VCT5_CTRL_SAMPLE_POINT |
2062 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
a618e86d 2063 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
0c9bcc1d
AL
2064 if (err)
2065 return err;
2066
2067 err = marvell_vct5_wait_complete(phydev);
2068 if (err)
2069 return err;
2070
f2bc8ad3
AL
2071 for (i = 0; i < 4; i++) {
2072 if (pair != PHY_PAIR_ALL && i != pair)
2073 continue;
0c9bcc1d 2074
f2bc8ad3
AL
2075 mV = marvell_vct5_amplitude(phydev, i);
2076 ethnl_cable_test_amplitude(phydev, i, mV);
2077 }
0c9bcc1d
AL
2078
2079 return 0;
2080}
2081
2082static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
2083{
f2bc8ad3 2084 struct marvell_priv *priv = phydev->priv;
0c9bcc1d 2085 int distance;
db8668a1 2086 u16 width;
a618e86d 2087 int page;
0c9bcc1d
AL
2088 int err;
2089 u16 reg;
2090
db8668a1
AL
2091 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
2092 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
2093 else
2094 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2095
0c9bcc1d
AL
2096 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2097 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
db8668a1 2098 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
0c9bcc1d
AL
2099
2100 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2101 MII_VCT5_TX_PULSE_CTRL, reg);
2102 if (err)
2103 return err;
2104
a618e86d
AL
2105 /* Reading the TDR data is very MDIO heavy. We need to optimize
2106 * access to keep the time to a minimum. So lock the bus once,
2107 * and don't release it until complete. We can then avoid having
2108 * to change the page for every access, greatly speeding things
2109 * up.
2110 */
2111 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
2112 if (page < 0)
830f5ce2 2113 goto restore_page;
a618e86d 2114
f2bc8ad3
AL
2115 for (distance = priv->first;
2116 distance <= priv->last;
2117 distance += priv->step) {
2118 err = marvell_vct5_amplitude_distance(phydev, distance,
2119 priv->pair);
0c9bcc1d 2120 if (err)
a618e86d 2121 goto restore_page;
db8668a1
AL
2122
2123 if (distance > TDR_SHORT_CABLE_LENGTH &&
2124 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
2125 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2126 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2127 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2128 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2129 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
2130 if (err)
2131 goto restore_page;
2132 }
0c9bcc1d
AL
2133 }
2134
a618e86d
AL
2135restore_page:
2136 return phy_restore_page(phydev, page, err);
0c9bcc1d
AL
2137}
2138
2139static int marvell_cable_test_start_common(struct phy_device *phydev)
fc879f72
AL
2140{
2141 int bmcr, bmsr, ret;
2142
2143 /* If auto-negotiation is enabled, but not complete, the cable
2144 * test never completes. So disable auto-neg.
2145 */
2146 bmcr = phy_read(phydev, MII_BMCR);
2147 if (bmcr < 0)
2148 return bmcr;
2149
2150 bmsr = phy_read(phydev, MII_BMSR);
2151
2152 if (bmsr < 0)
2153 return bmsr;
2154
2155 if (bmcr & BMCR_ANENABLE) {
832913c3 2156 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
fc879f72
AL
2157 if (ret < 0)
2158 return ret;
2159 ret = genphy_soft_reset(phydev);
2160 if (ret < 0)
2161 return ret;
2162 }
2163
2164 /* If the link is up, allow it some time to go down */
2165 if (bmsr & BMSR_LSTATUS)
2166 msleep(1500);
2167
0c9bcc1d
AL
2168 return 0;
2169}
2170
2171static int marvell_vct7_cable_test_start(struct phy_device *phydev)
2172{
2173 struct marvell_priv *priv = phydev->priv;
2174 int ret;
2175
2176 ret = marvell_cable_test_start_common(phydev);
2177 if (ret)
2178 return ret;
2179
2180 priv->cable_test_tdr = false;
2181
2182 /* Reset the VCT5 API control to defaults, otherwise
2183 * VCT7 does not work correctly.
2184 */
2185 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2186 MII_VCT5_CTRL,
2187 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2188 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2189 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
2190 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
2191 if (ret)
2192 return ret;
2193
2194 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2195 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
2196 if (ret)
2197 return ret;
2198
fc879f72
AL
2199 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2200 MII_VCT7_CTRL,
2201 MII_VCT7_CTRL_RUN_NOW |
2202 MII_VCT7_CTRL_CENTIMETERS);
2203}
2204
f2bc8ad3
AL
2205static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
2206 const struct phy_tdr_config *cfg)
0c9bcc1d
AL
2207{
2208 struct marvell_priv *priv = phydev->priv;
2209 int ret;
2210
f2bc8ad3
AL
2211 priv->cable_test_tdr = true;
2212 priv->first = marvell_vct5_cm2distance(cfg->first);
2213 priv->last = marvell_vct5_cm2distance(cfg->last);
2214 priv->step = marvell_vct5_cm2distance(cfg->step);
2215 priv->pair = cfg->pair;
2216
2217 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2218 return -EINVAL;
2219
2220 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2221 return -EINVAL;
2222
0c9bcc1d
AL
2223 /* Disable VCT7 */
2224 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2225 MII_VCT7_CTRL, 0);
2226 if (ret)
2227 return ret;
2228
2229 ret = marvell_cable_test_start_common(phydev);
2230 if (ret)
2231 return ret;
2232
0c9bcc1d
AL
2233 ret = ethnl_cable_test_pulse(phydev, 1000);
2234 if (ret)
2235 return ret;
2236
2237 return ethnl_cable_test_step(phydev,
f2bc8ad3
AL
2238 marvell_vct5_distance2cm(priv->first),
2239 marvell_vct5_distance2cm(priv->last),
2240 marvell_vct5_distance2cm(priv->step));
0c9bcc1d
AL
2241}
2242
fc879f72
AL
2243static int marvell_vct7_distance_to_length(int distance, bool meter)
2244{
2245 if (meter)
2246 distance *= 100;
2247
2248 return distance;
2249}
2250
2251static bool marvell_vct7_distance_valid(int result)
2252{
2253 switch (result) {
2254 case MII_VCT7_RESULTS_OPEN:
2255 case MII_VCT7_RESULTS_SAME_SHORT:
2256 case MII_VCT7_RESULTS_CROSS_SHORT:
2257 return true;
2258 }
2259 return false;
2260}
2261
2262static int marvell_vct7_report_length(struct phy_device *phydev,
2263 int pair, bool meter)
2264{
2265 int length;
2266 int ret;
2267
2268 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2269 MII_VCT7_PAIR_0_DISTANCE + pair);
2270 if (ret < 0)
2271 return ret;
2272
2273 length = marvell_vct7_distance_to_length(ret, meter);
2274
2275 ethnl_cable_test_fault_length(phydev, pair, length);
2276
2277 return 0;
2278}
2279
2280static int marvell_vct7_cable_test_report_trans(int result)
2281{
2282 switch (result) {
2283 case MII_VCT7_RESULTS_OK:
2284 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2285 case MII_VCT7_RESULTS_OPEN:
2286 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2287 case MII_VCT7_RESULTS_SAME_SHORT:
2288 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2289 case MII_VCT7_RESULTS_CROSS_SHORT:
2290 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2291 default:
2292 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2293 }
2294}
2295
2296static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2297{
2298 int pair0, pair1, pair2, pair3;
2299 bool meter;
2300 int ret;
2301
2302 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2303 MII_VCT7_RESULTS);
2304 if (ret < 0)
2305 return ret;
2306
2307 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2308 MII_VCT7_RESULTS_PAIR3_SHIFT;
2309 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2310 MII_VCT7_RESULTS_PAIR2_SHIFT;
2311 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2312 MII_VCT7_RESULTS_PAIR1_SHIFT;
2313 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2314 MII_VCT7_RESULTS_PAIR0_SHIFT;
2315
2316 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2317 marvell_vct7_cable_test_report_trans(pair0));
2318 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2319 marvell_vct7_cable_test_report_trans(pair1));
2320 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2321 marvell_vct7_cable_test_report_trans(pair2));
2322 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2323 marvell_vct7_cable_test_report_trans(pair3));
2324
2325 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2326 if (ret < 0)
2327 return ret;
2328
2329 meter = ret & MII_VCT7_CTRL_METERS;
2330
2331 if (marvell_vct7_distance_valid(pair0))
2332 marvell_vct7_report_length(phydev, 0, meter);
2333 if (marvell_vct7_distance_valid(pair1))
2334 marvell_vct7_report_length(phydev, 1, meter);
2335 if (marvell_vct7_distance_valid(pair2))
2336 marvell_vct7_report_length(phydev, 2, meter);
2337 if (marvell_vct7_distance_valid(pair3))
2338 marvell_vct7_report_length(phydev, 3, meter);
2339
2340 return 0;
2341}
2342
2343static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2344 bool *finished)
2345{
0c9bcc1d 2346 struct marvell_priv *priv = phydev->priv;
fc879f72
AL
2347 int ret;
2348
0c9bcc1d
AL
2349 if (priv->cable_test_tdr) {
2350 ret = marvell_vct5_amplitude_graph(phydev);
2351 *finished = true;
2352 return ret;
2353 }
2354
fc879f72
AL
2355 *finished = false;
2356
2357 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2358 MII_VCT7_CTRL);
2359
2360 if (ret < 0)
2361 return ret;
2362
2363 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2364 *finished = true;
2365
2366 return marvell_vct7_cable_test_report(phydev);
2367 }
2368
2369 return 0;
2370}
2371
0b04680f 2372#ifdef CONFIG_HWMON
41d26bf4 2373struct marvell_hwmon_ops {
a978f7c4 2374 int (*config)(struct phy_device *phydev);
41d26bf4
MB
2375 int (*get_temp)(struct phy_device *phydev, long *temp);
2376 int (*get_temp_critical)(struct phy_device *phydev, long *temp);
2377 int (*set_temp_critical)(struct phy_device *phydev, long temp);
2378 int (*get_temp_alarm)(struct phy_device *phydev, long *alarm);
2379};
2380
2381static const struct marvell_hwmon_ops *
2382to_marvell_hwmon_ops(const struct phy_device *phydev)
2383{
2384 return phydev->drv->driver_data;
2385}
2386
0b04680f
AL
2387static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2388{
975b388c 2389 int oldpage;
424ca4c5 2390 int ret = 0;
0b04680f
AL
2391 int val;
2392
2393 *temp = 0;
2394
424ca4c5
RK
2395 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2396 if (oldpage < 0)
2397 goto error;
975b388c 2398
0b04680f 2399 /* Enable temperature sensor */
424ca4c5 2400 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
0b04680f
AL
2401 if (ret < 0)
2402 goto error;
2403
424ca4c5
RK
2404 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2405 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
0b04680f
AL
2406 if (ret < 0)
2407 goto error;
2408
2409 /* Wait for temperature to stabilize */
2410 usleep_range(10000, 12000);
2411
424ca4c5 2412 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
0b04680f
AL
2413 if (val < 0) {
2414 ret = val;
2415 goto error;
2416 }
2417
2418 /* Disable temperature sensor */
424ca4c5
RK
2419 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2420 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
0b04680f
AL
2421 if (ret < 0)
2422 goto error;
2423
2424 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2425
2426error:
424ca4c5 2427 return phy_restore_page(phydev, oldpage, ret);
0b04680f
AL
2428}
2429
0b04680f
AL
2430static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2431{
2432 int ret;
2433
2434 *temp = 0;
2435
424ca4c5
RK
2436 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2437 MII_88E1510_TEMP_SENSOR);
0b04680f 2438 if (ret < 0)
424ca4c5 2439 return ret;
0b04680f
AL
2440
2441 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2442
424ca4c5 2443 return 0;
0b04680f
AL
2444}
2445
f0a45816 2446static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
0b04680f
AL
2447{
2448 int ret;
2449
2450 *temp = 0;
2451
424ca4c5
RK
2452 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2453 MII_88E1121_MISC_TEST);
0b04680f 2454 if (ret < 0)
424ca4c5 2455 return ret;
0b04680f
AL
2456
2457 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2458 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2459 /* convert to mC */
2460 *temp *= 1000;
2461
424ca4c5 2462 return 0;
0b04680f
AL
2463}
2464
f0a45816 2465static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
0b04680f 2466{
0b04680f
AL
2467 temp = temp / 1000;
2468 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
0b04680f 2469
424ca4c5
RK
2470 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2471 MII_88E1121_MISC_TEST,
2472 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2473 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
0b04680f
AL
2474}
2475
f0a45816 2476static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
0b04680f
AL
2477{
2478 int ret;
2479
2480 *alarm = false;
2481
424ca4c5
RK
2482 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2483 MII_88E1121_MISC_TEST);
0b04680f 2484 if (ret < 0)
424ca4c5 2485 return ret;
0b04680f 2486
424ca4c5 2487 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
0b04680f 2488
424ca4c5 2489 return 0;
0b04680f
AL
2490}
2491
fee2d546
AL
2492static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2493{
2494 int sum = 0;
2495 int oldpage;
2496 int ret = 0;
2497 int i;
2498
2499 *temp = 0;
2500
2501 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2502 if (oldpage < 0)
2503 goto error;
2504
2505 /* Enable temperature sensor */
2506 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2507 if (ret < 0)
2508 goto error;
2509
00218173 2510 ret &= ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
4f920c29 2511 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S;
fee2d546
AL
2512
2513 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2514 if (ret < 0)
2515 goto error;
2516
2517 /* Wait for temperature to stabilize */
2518 usleep_range(10000, 12000);
2519
2520 /* Reading the temperature sense has an errata. You need to read
2521 * a number of times and take an average.
2522 */
2523 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2524 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2525 if (ret < 0)
2526 goto error;
2527 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2528 }
2529
2530 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2531 *temp = (sum - 75) * 1000;
2532
2533 /* Disable temperature sensor */
2534 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2535 if (ret < 0)
2536 goto error;
2537
4f920c29
MB
2538 ret = ret & ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2539 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE;
fee2d546
AL
2540
2541 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2542
2543error:
2544 phy_restore_page(phydev, oldpage, ret);
2545
2546 return ret;
2547}
2548
a978f7c4
MB
2549static int m88e6393_get_temp(struct phy_device *phydev, long *temp)
2550{
2551 int err;
2552
2553 err = m88e1510_get_temp(phydev, temp);
2554
2555 /* 88E1510 measures T + 25, while the PHY on 88E6393X switch
2556 * T + 75, so we have to subtract another 50
2557 */
2558 *temp -= 50000;
2559
2560 return err;
2561}
2562
2563static int m88e6393_get_temp_critical(struct phy_device *phydev, long *temp)
2564{
2565 int ret;
2566
2567 *temp = 0;
2568
2569 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2570 MII_88E6390_TEMP_SENSOR);
2571 if (ret < 0)
2572 return ret;
2573
2574 *temp = (((ret & MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK) >>
2575 MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT) - 75) * 1000;
2576
2577 return 0;
2578}
2579
2580static int m88e6393_set_temp_critical(struct phy_device *phydev, long temp)
2581{
2582 temp = (temp / 1000) + 75;
2583
2584 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2585 MII_88E6390_TEMP_SENSOR,
2586 MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK,
2587 temp << MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT);
2588}
2589
2590static int m88e6393_hwmon_config(struct phy_device *phydev)
2591{
2592 int err;
2593
2594 err = m88e6393_set_temp_critical(phydev, 100000);
2595 if (err)
2596 return err;
2597
2598 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2599 MII_88E6390_MISC_TEST,
2600 MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK |
2601 MII_88E6393_MISC_TEST_SAMPLES_MASK |
2602 MII_88E6393_MISC_TEST_RATE_MASK,
2603 MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE |
2604 MII_88E6393_MISC_TEST_SAMPLES_2048 |
2605 MII_88E6393_MISC_TEST_RATE_2_3MS);
2606}
2607
41d26bf4
MB
2608static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
2609 u32 attr, int channel, long *temp)
fee2d546
AL
2610{
2611 struct phy_device *phydev = dev_get_drvdata(dev);
41d26bf4
MB
2612 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2613 int err = -EOPNOTSUPP;
fee2d546
AL
2614
2615 switch (attr) {
2616 case hwmon_temp_input:
41d26bf4
MB
2617 if (ops->get_temp)
2618 err = ops->get_temp(phydev, temp);
2619 break;
2620 case hwmon_temp_crit:
2621 if (ops->get_temp_critical)
2622 err = ops->get_temp_critical(phydev, temp);
2623 break;
2624 case hwmon_temp_max_alarm:
2625 if (ops->get_temp_alarm)
2626 err = ops->get_temp_alarm(phydev, temp);
2627 break;
2628 }
2629
2630 return err;
2631}
2632
2633static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
2634 u32 attr, int channel, long temp)
2635{
2636 struct phy_device *phydev = dev_get_drvdata(dev);
2637 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2638 int err = -EOPNOTSUPP;
2639
2640 switch (attr) {
2641 case hwmon_temp_crit:
2642 if (ops->set_temp_critical)
2643 err = ops->set_temp_critical(phydev, temp);
fee2d546 2644 break;
fee2d546
AL
2645 }
2646
2647 return err;
2648}
2649
41d26bf4
MB
2650static umode_t marvell_hwmon_is_visible(const void *data,
2651 enum hwmon_sensor_types type,
2652 u32 attr, int channel)
fee2d546 2653{
41d26bf4
MB
2654 const struct phy_device *phydev = data;
2655 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2656
fee2d546
AL
2657 if (type != hwmon_temp)
2658 return 0;
2659
2660 switch (attr) {
2661 case hwmon_temp_input:
41d26bf4
MB
2662 return ops->get_temp ? 0444 : 0;
2663 case hwmon_temp_max_alarm:
2664 return ops->get_temp_alarm ? 0444 : 0;
2665 case hwmon_temp_crit:
2666 return (ops->get_temp_critical ? 0444 : 0) |
2667 (ops->set_temp_critical ? 0200 : 0);
fee2d546
AL
2668 default:
2669 return 0;
2670 }
2671}
2672
41d26bf4
MB
2673static u32 marvell_hwmon_chip_config[] = {
2674 HWMON_C_REGISTER_TZ,
fee2d546
AL
2675 0
2676};
2677
41d26bf4
MB
2678static const struct hwmon_channel_info marvell_hwmon_chip = {
2679 .type = hwmon_chip,
2680 .config = marvell_hwmon_chip_config,
2681};
2682
2683/* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not
2684 * defined for all PHYs, because the hwmon code checks whether the attributes
2685 * exists via the .is_visible method
2686 */
2687static u32 marvell_hwmon_temp_config[] = {
2688 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2689 0
2690};
2691
2692static const struct hwmon_channel_info marvell_hwmon_temp = {
fee2d546 2693 .type = hwmon_temp,
41d26bf4 2694 .config = marvell_hwmon_temp_config,
fee2d546
AL
2695};
2696
41d26bf4
MB
2697static const struct hwmon_channel_info *marvell_hwmon_info[] = {
2698 &marvell_hwmon_chip,
2699 &marvell_hwmon_temp,
fee2d546
AL
2700 NULL
2701};
2702
41d26bf4
MB
2703static const struct hwmon_ops marvell_hwmon_hwmon_ops = {
2704 .is_visible = marvell_hwmon_is_visible,
2705 .read = marvell_hwmon_read,
2706 .write = marvell_hwmon_write,
fee2d546
AL
2707};
2708
41d26bf4
MB
2709static const struct hwmon_chip_info marvell_hwmon_chip_info = {
2710 .ops = &marvell_hwmon_hwmon_ops,
2711 .info = marvell_hwmon_info,
fee2d546
AL
2712};
2713
0b04680f
AL
2714static int marvell_hwmon_name(struct phy_device *phydev)
2715{
2716 struct marvell_priv *priv = phydev->priv;
2717 struct device *dev = &phydev->mdio.dev;
2718 const char *devname = dev_name(dev);
2719 size_t len = strlen(devname);
2720 int i, j;
2721
2722 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2723 if (!priv->hwmon_name)
2724 return -ENOMEM;
2725
2726 for (i = j = 0; i < len && devname[i]; i++) {
2727 if (isalnum(devname[i]))
2728 priv->hwmon_name[j++] = devname[i];
2729 }
2730
2731 return 0;
2732}
2733
41d26bf4 2734static int marvell_hwmon_probe(struct phy_device *phydev)
0b04680f 2735{
41d26bf4 2736 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
0b04680f
AL
2737 struct marvell_priv *priv = phydev->priv;
2738 struct device *dev = &phydev->mdio.dev;
2739 int err;
2740
41d26bf4
MB
2741 if (!ops)
2742 return 0;
2743
0b04680f
AL
2744 err = marvell_hwmon_name(phydev);
2745 if (err)
2746 return err;
2747
2748 priv->hwmon_dev = devm_hwmon_device_register_with_info(
41d26bf4 2749 dev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL);
a978f7c4
MB
2750 if (IS_ERR(priv->hwmon_dev))
2751 return PTR_ERR(priv->hwmon_dev);
0b04680f 2752
a978f7c4
MB
2753 if (ops->config)
2754 err = ops->config(phydev);
2755
2756 return err;
0b04680f
AL
2757}
2758
41d26bf4
MB
2759static const struct marvell_hwmon_ops m88e1121_hwmon_ops = {
2760 .get_temp = m88e1121_get_temp,
2761};
0b04680f 2762
41d26bf4
MB
2763static const struct marvell_hwmon_ops m88e1510_hwmon_ops = {
2764 .get_temp = m88e1510_get_temp,
2765 .get_temp_critical = m88e1510_get_temp_critical,
2766 .set_temp_critical = m88e1510_set_temp_critical,
2767 .get_temp_alarm = m88e1510_get_temp_alarm,
2768};
2769
2770static const struct marvell_hwmon_ops m88e6390_hwmon_ops = {
2771 .get_temp = m88e6390_get_temp,
2772};
2773
a978f7c4
MB
2774static const struct marvell_hwmon_ops m88e6393_hwmon_ops = {
2775 .config = m88e6393_hwmon_config,
2776 .get_temp = m88e6393_get_temp,
2777 .get_temp_critical = m88e6393_get_temp_critical,
2778 .set_temp_critical = m88e6393_set_temp_critical,
2779 .get_temp_alarm = m88e1510_get_temp_alarm,
2780};
2781
41d26bf4 2782#define DEF_MARVELL_HWMON_OPS(s) (&(s))
fee2d546 2783
0b04680f 2784#else
0b04680f 2785
41d26bf4 2786#define DEF_MARVELL_HWMON_OPS(s) NULL
fee2d546 2787
41d26bf4 2788static int marvell_hwmon_probe(struct phy_device *phydev)
fee2d546
AL
2789{
2790 return 0;
2791}
0b04680f
AL
2792#endif
2793
d2fa47d9
AL
2794static int marvell_probe(struct phy_device *phydev)
2795{
2796 struct marvell_priv *priv;
2797
e5a03bfd 2798 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
d2fa47d9
AL
2799 if (!priv)
2800 return -ENOMEM;
2801
2802 phydev->priv = priv;
2803
41d26bf4 2804 return marvell_hwmon_probe(phydev);
fee2d546
AL
2805}
2806
b697d9d3
IB
2807static int m88e1510_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
2808{
2809 struct phy_device *phydev = upstream;
2810 phy_interface_t interface;
2811 struct device *dev;
2812 int oldpage;
2813 int ret = 0;
2814 u16 mode;
2815
2816 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
2817
2818 dev = &phydev->mdio.dev;
2819
2820 sfp_parse_support(phydev->sfp_bus, id, supported);
2821 interface = sfp_select_interface(phydev->sfp_bus, supported);
2822
2823 dev_info(dev, "%s SFP module inserted\n", phy_modes(interface));
2824
2825 switch (interface) {
2826 case PHY_INTERFACE_MODE_1000BASEX:
2827 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X;
2828
2829 break;
2830 case PHY_INTERFACE_MODE_100BASEX:
2831 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX;
2832
2833 break;
2834 case PHY_INTERFACE_MODE_SGMII:
2835 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII;
2836
2837 break;
2838 default:
2839 dev_err(dev, "Incompatible SFP module inserted\n");
2840
2841 return -EINVAL;
2842 }
2843
2844 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
2845 if (oldpage < 0)
2846 goto error;
2847
2848 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
2849 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK, mode);
2850 if (ret < 0)
2851 goto error;
2852
2853 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
2854 MII_88E1510_GEN_CTRL_REG_1_RESET);
2855
2856error:
2857 return phy_restore_page(phydev, oldpage, ret);
2858}
2859
2860static void m88e1510_sfp_remove(void *upstream)
2861{
2862 struct phy_device *phydev = upstream;
2863 int oldpage;
2864 int ret = 0;
2865
2866 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
2867 if (oldpage < 0)
2868 goto error;
2869
2870 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
2871 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
2872 MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII);
2873 if (ret < 0)
2874 goto error;
2875
2876 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
2877 MII_88E1510_GEN_CTRL_REG_1_RESET);
2878
2879error:
2880 phy_restore_page(phydev, oldpage, ret);
2881}
2882
2883static const struct sfp_upstream_ops m88e1510_sfp_ops = {
2884 .module_insert = m88e1510_sfp_insert,
2885 .module_remove = m88e1510_sfp_remove,
2886 .attach = phy_sfp_attach,
2887 .detach = phy_sfp_detach,
2888};
2889
2890static int m88e1510_probe(struct phy_device *phydev)
2891{
2892 int err;
2893
2894 err = marvell_probe(phydev);
2895 if (err)
2896 return err;
2897
2898 return phy_sfp_probe(phydev, &m88e1510_sfp_ops);
2899}
2900
e5479239
OJ
2901static struct phy_driver marvell_drivers[] = {
2902 {
2f495c39
BH
2903 .phy_id = MARVELL_PHY_ID_88E1101,
2904 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239 2905 .name = "Marvell 88E1101",
dcdecdcf 2906 /* PHY_GBIT_FEATURES */
18702414 2907 .probe = marvell_probe,
ef0f9545
MK
2908 .config_init = marvell_config_init,
2909 .config_aneg = m88e1101_config_aneg,
ef0f9545 2910 .config_intr = marvell_config_intr,
a0723b37 2911 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
2912 .resume = genphy_resume,
2913 .suspend = genphy_suspend,
424ca4c5
RK
2914 .read_page = marvell_read_page,
2915 .write_page = marvell_write_page,
d2fa47d9
AL
2916 .get_sset_count = marvell_get_sset_count,
2917 .get_strings = marvell_get_strings,
2918 .get_stats = marvell_get_stats,
e5479239 2919 },
85cfb534 2920 {
2f495c39
BH
2921 .phy_id = MARVELL_PHY_ID_88E1112,
2922 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534 2923 .name = "Marvell 88E1112",
dcdecdcf 2924 /* PHY_GBIT_FEATURES */
d2fa47d9 2925 .probe = marvell_probe,
8385b1f0 2926 .config_init = m88e1112_config_init,
ef0f9545 2927 .config_aneg = marvell_config_aneg,
ef0f9545 2928 .config_intr = marvell_config_intr,
a0723b37 2929 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
2930 .resume = genphy_resume,
2931 .suspend = genphy_suspend,
424ca4c5
RK
2932 .read_page = marvell_read_page,
2933 .write_page = marvell_write_page,
d2fa47d9
AL
2934 .get_sset_count = marvell_get_sset_count,
2935 .get_strings = marvell_get_strings,
2936 .get_stats = marvell_get_stats,
262caf47
HK
2937 .get_tunable = m88e1011_get_tunable,
2938 .set_tunable = m88e1011_set_tunable,
85cfb534 2939 },
e5479239 2940 {
2f495c39
BH
2941 .phy_id = MARVELL_PHY_ID_88E1111,
2942 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239 2943 .name = "Marvell 88E1111",
dcdecdcf 2944 /* PHY_GBIT_FEATURES */
d2fa47d9 2945 .probe = marvell_probe,
8385b1f0 2946 .config_init = m88e1111gbe_config_init,
1887023a
RH
2947 .config_aneg = m88e1111_config_aneg,
2948 .read_status = marvell_read_status,
1887023a 2949 .config_intr = marvell_config_intr,
a0723b37 2950 .handle_interrupt = marvell_handle_interrupt,
1887023a
RH
2951 .resume = genphy_resume,
2952 .suspend = genphy_suspend,
2953 .read_page = marvell_read_page,
2954 .write_page = marvell_write_page,
2955 .get_sset_count = marvell_get_sset_count,
2956 .get_strings = marvell_get_strings,
2957 .get_stats = marvell_get_stats,
2958 .get_tunable = m88e1111_get_tunable,
2959 .set_tunable = m88e1111_set_tunable,
2960 },
2961 {
2962 .phy_id = MARVELL_PHY_ID_88E1111_FINISAR,
2963 .phy_id_mask = MARVELL_PHY_ID_MASK,
2964 .name = "Marvell 88E1111 (Finisar)",
2965 /* PHY_GBIT_FEATURES */
2966 .probe = marvell_probe,
8385b1f0 2967 .config_init = m88e1111gbe_config_init,
1887023a 2968 .config_aneg = m88e1111_config_aneg,
ef0f9545 2969 .read_status = marvell_read_status,
ef0f9545 2970 .config_intr = marvell_config_intr,
a0723b37 2971 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
2972 .resume = genphy_resume,
2973 .suspend = genphy_suspend,
424ca4c5
RK
2974 .read_page = marvell_read_page,
2975 .write_page = marvell_write_page,
d2fa47d9
AL
2976 .get_sset_count = marvell_get_sset_count,
2977 .get_strings = marvell_get_strings,
2978 .get_stats = marvell_get_stats,
5c6bc519
HK
2979 .get_tunable = m88e1111_get_tunable,
2980 .set_tunable = m88e1111_set_tunable,
e5479239 2981 },
605f196e 2982 {
2f495c39
BH
2983 .phy_id = MARVELL_PHY_ID_88E1118,
2984 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e 2985 .name = "Marvell 88E1118",
dcdecdcf 2986 /* PHY_GBIT_FEATURES */
d2fa47d9 2987 .probe = marvell_probe,
ef0f9545
MK
2988 .config_init = m88e1118_config_init,
2989 .config_aneg = m88e1118_config_aneg,
ef0f9545 2990 .config_intr = marvell_config_intr,
a0723b37 2991 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
2992 .resume = genphy_resume,
2993 .suspend = genphy_suspend,
424ca4c5
RK
2994 .read_page = marvell_read_page,
2995 .write_page = marvell_write_page,
d2fa47d9
AL
2996 .get_sset_count = marvell_get_sset_count,
2997 .get_strings = marvell_get_strings,
2998 .get_stats = marvell_get_stats,
605f196e 2999 },
140bc929 3000 {
2f495c39
BH
3001 .phy_id = MARVELL_PHY_ID_88E1121R,
3002 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929 3003 .name = "Marvell 88E1121R",
41d26bf4 3004 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops),
dcdecdcf 3005 /* PHY_GBIT_FEATURES */
41d26bf4 3006 .probe = marvell_probe,
8385b1f0 3007 .config_init = marvell_1011gbe_config_init,
ef0f9545
MK
3008 .config_aneg = m88e1121_config_aneg,
3009 .read_status = marvell_read_status,
ef0f9545 3010 .config_intr = marvell_config_intr,
a0723b37 3011 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3012 .resume = genphy_resume,
3013 .suspend = genphy_suspend,
424ca4c5
RK
3014 .read_page = marvell_read_page,
3015 .write_page = marvell_write_page,
d2fa47d9
AL
3016 .get_sset_count = marvell_get_sset_count,
3017 .get_strings = marvell_get_strings,
3018 .get_stats = marvell_get_stats,
911af5e1
HK
3019 .get_tunable = m88e1011_get_tunable,
3020 .set_tunable = m88e1011_set_tunable,
140bc929 3021 },
3ff1c259 3022 {
337ac9d5 3023 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 3024 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 3025 .name = "Marvell 88E1318S",
dcdecdcf 3026 /* PHY_GBIT_FEATURES */
d2fa47d9 3027 .probe = marvell_probe,
ef0f9545
MK
3028 .config_init = m88e1318_config_init,
3029 .config_aneg = m88e1318_config_aneg,
3030 .read_status = marvell_read_status,
ef0f9545 3031 .config_intr = marvell_config_intr,
a0723b37 3032 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3033 .get_wol = m88e1318_get_wol,
3034 .set_wol = m88e1318_set_wol,
3035 .resume = genphy_resume,
3036 .suspend = genphy_suspend,
424ca4c5
RK
3037 .read_page = marvell_read_page,
3038 .write_page = marvell_write_page,
d2fa47d9
AL
3039 .get_sset_count = marvell_get_sset_count,
3040 .get_strings = marvell_get_strings,
3041 .get_stats = marvell_get_stats,
3ff1c259 3042 },
e5479239 3043 {
2f495c39
BH
3044 .phy_id = MARVELL_PHY_ID_88E1145,
3045 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239 3046 .name = "Marvell 88E1145",
dcdecdcf 3047 /* PHY_GBIT_FEATURES */
d2fa47d9 3048 .probe = marvell_probe,
ef0f9545
MK
3049 .config_init = m88e1145_config_init,
3050 .config_aneg = m88e1101_config_aneg,
ef0f9545 3051 .config_intr = marvell_config_intr,
a0723b37 3052 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3053 .resume = genphy_resume,
3054 .suspend = genphy_suspend,
424ca4c5
RK
3055 .read_page = marvell_read_page,
3056 .write_page = marvell_write_page,
d2fa47d9
AL
3057 .get_sset_count = marvell_get_sset_count,
3058 .get_strings = marvell_get_strings,
3059 .get_stats = marvell_get_stats,
a319fb52
HK
3060 .get_tunable = m88e1111_get_tunable,
3061 .set_tunable = m88e1111_set_tunable,
ac8c635a 3062 },
90600732
DD
3063 {
3064 .phy_id = MARVELL_PHY_ID_88E1149R,
3065 .phy_id_mask = MARVELL_PHY_ID_MASK,
3066 .name = "Marvell 88E1149R",
dcdecdcf 3067 /* PHY_GBIT_FEATURES */
d2fa47d9 3068 .probe = marvell_probe,
ef0f9545
MK
3069 .config_init = m88e1149_config_init,
3070 .config_aneg = m88e1118_config_aneg,
ef0f9545 3071 .config_intr = marvell_config_intr,
a0723b37 3072 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3073 .resume = genphy_resume,
3074 .suspend = genphy_suspend,
424ca4c5
RK
3075 .read_page = marvell_read_page,
3076 .write_page = marvell_write_page,
d2fa47d9
AL
3077 .get_sset_count = marvell_get_sset_count,
3078 .get_strings = marvell_get_strings,
3079 .get_stats = marvell_get_stats,
90600732 3080 },
ac8c635a 3081 {
2f495c39
BH
3082 .phy_id = MARVELL_PHY_ID_88E1240,
3083 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a 3084 .name = "Marvell 88E1240",
dcdecdcf 3085 /* PHY_GBIT_FEATURES */
d2fa47d9 3086 .probe = marvell_probe,
8385b1f0 3087 .config_init = m88e1112_config_init,
ef0f9545 3088 .config_aneg = marvell_config_aneg,
ef0f9545 3089 .config_intr = marvell_config_intr,
a0723b37 3090 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3091 .resume = genphy_resume,
3092 .suspend = genphy_suspend,
424ca4c5
RK
3093 .read_page = marvell_read_page,
3094 .write_page = marvell_write_page,
d2fa47d9
AL
3095 .get_sset_count = marvell_get_sset_count,
3096 .get_strings = marvell_get_strings,
3097 .get_stats = marvell_get_stats,
65ad85f6
MK
3098 .get_tunable = m88e1011_get_tunable,
3099 .set_tunable = m88e1011_set_tunable,
ac8c635a 3100 },
3da09a51
MS
3101 {
3102 .phy_id = MARVELL_PHY_ID_88E1116R,
3103 .phy_id_mask = MARVELL_PHY_ID_MASK,
3104 .name = "Marvell 88E1116R",
dcdecdcf 3105 /* PHY_GBIT_FEATURES */
d2fa47d9 3106 .probe = marvell_probe,
ef0f9545 3107 .config_init = m88e1116r_config_init,
ef0f9545 3108 .config_intr = marvell_config_intr,
a0723b37 3109 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3110 .resume = genphy_resume,
3111 .suspend = genphy_suspend,
424ca4c5
RK
3112 .read_page = marvell_read_page,
3113 .write_page = marvell_write_page,
d2fa47d9
AL
3114 .get_sset_count = marvell_get_sset_count,
3115 .get_strings = marvell_get_strings,
3116 .get_stats = marvell_get_stats,
262caf47
HK
3117 .get_tunable = m88e1011_get_tunable,
3118 .set_tunable = m88e1011_set_tunable,
3da09a51 3119 },
10e24caa
MS
3120 {
3121 .phy_id = MARVELL_PHY_ID_88E1510,
3122 .phy_id_mask = MARVELL_PHY_ID_MASK,
3123 .name = "Marvell 88E1510",
41d26bf4 3124 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
719655a1 3125 .features = PHY_GBIT_FIBRE_FEATURES,
fc879f72 3126 .flags = PHY_POLL_CABLE_TEST,
b697d9d3 3127 .probe = m88e1510_probe,
ef0f9545
MK
3128 .config_init = m88e1510_config_init,
3129 .config_aneg = m88e1510_config_aneg,
3130 .read_status = marvell_read_status,
ef0f9545 3131 .config_intr = marvell_config_intr,
a0723b37 3132 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3133 .get_wol = m88e1318_get_wol,
3134 .set_wol = m88e1318_set_wol,
3135 .resume = marvell_resume,
3136 .suspend = marvell_suspend,
424ca4c5
RK
3137 .read_page = marvell_read_page,
3138 .write_page = marvell_write_page,
d2fa47d9
AL
3139 .get_sset_count = marvell_get_sset_count,
3140 .get_strings = marvell_get_strings,
3141 .get_stats = marvell_get_stats,
893dfb14 3142 .set_loopback = m88e1510_loopback,
262caf47
HK
3143 .get_tunable = m88e1011_get_tunable,
3144 .set_tunable = m88e1011_set_tunable,
fc879f72 3145 .cable_test_start = marvell_vct7_cable_test_start,
0c9bcc1d 3146 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
fc879f72 3147 .cable_test_get_status = marvell_vct7_cable_test_get_status,
10e24caa 3148 },
819ec8e1
AL
3149 {
3150 .phy_id = MARVELL_PHY_ID_88E1540,
3151 .phy_id_mask = MARVELL_PHY_ID_MASK,
3152 .name = "Marvell 88E1540",
41d26bf4 3153 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
dcdecdcf 3154 /* PHY_GBIT_FEATURES */
fc879f72 3155 .flags = PHY_POLL_CABLE_TEST,
41d26bf4 3156 .probe = marvell_probe,
8385b1f0 3157 .config_init = marvell_1011gbe_config_init,
ef0f9545
MK
3158 .config_aneg = m88e1510_config_aneg,
3159 .read_status = marvell_read_status,
ef0f9545 3160 .config_intr = marvell_config_intr,
a0723b37 3161 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3162 .resume = genphy_resume,
3163 .suspend = genphy_suspend,
424ca4c5
RK
3164 .read_page = marvell_read_page,
3165 .write_page = marvell_write_page,
d2fa47d9
AL
3166 .get_sset_count = marvell_get_sset_count,
3167 .get_strings = marvell_get_strings,
3168 .get_stats = marvell_get_stats,
69f42be8
HK
3169 .get_tunable = m88e1540_get_tunable,
3170 .set_tunable = m88e1540_set_tunable,
fc879f72 3171 .cable_test_start = marvell_vct7_cable_test_start,
0c9bcc1d 3172 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
fc879f72 3173 .cable_test_get_status = marvell_vct7_cable_test_get_status,
819ec8e1 3174 },
60f06fde
AL
3175 {
3176 .phy_id = MARVELL_PHY_ID_88E1545,
3177 .phy_id_mask = MARVELL_PHY_ID_MASK,
3178 .name = "Marvell 88E1545",
41d26bf4
MB
3179 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3180 .probe = marvell_probe,
dcdecdcf 3181 /* PHY_GBIT_FEATURES */
fc879f72 3182 .flags = PHY_POLL_CABLE_TEST,
8385b1f0 3183 .config_init = marvell_1011gbe_config_init,
ef0f9545
MK
3184 .config_aneg = m88e1510_config_aneg,
3185 .read_status = marvell_read_status,
ef0f9545 3186 .config_intr = marvell_config_intr,
a0723b37 3187 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3188 .resume = genphy_resume,
3189 .suspend = genphy_suspend,
424ca4c5
RK
3190 .read_page = marvell_read_page,
3191 .write_page = marvell_write_page,
60f06fde
AL
3192 .get_sset_count = marvell_get_sset_count,
3193 .get_strings = marvell_get_strings,
3194 .get_stats = marvell_get_stats,
262caf47
HK
3195 .get_tunable = m88e1540_get_tunable,
3196 .set_tunable = m88e1540_set_tunable,
fc879f72 3197 .cable_test_start = marvell_vct7_cable_test_start,
0c9bcc1d 3198 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
fc879f72 3199 .cable_test_get_status = marvell_vct7_cable_test_get_status,
60f06fde 3200 },
6b358aed
SH
3201 {
3202 .phy_id = MARVELL_PHY_ID_88E3016,
3203 .phy_id_mask = MARVELL_PHY_ID_MASK,
3204 .name = "Marvell 88E3016",
dcdecdcf 3205 /* PHY_BASIC_FEATURES */
d2fa47d9 3206 .probe = marvell_probe,
ef0f9545
MK
3207 .config_init = m88e3016_config_init,
3208 .aneg_done = marvell_aneg_done,
3209 .read_status = marvell_read_status,
ef0f9545 3210 .config_intr = marvell_config_intr,
a0723b37 3211 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3212 .resume = genphy_resume,
3213 .suspend = genphy_suspend,
424ca4c5
RK
3214 .read_page = marvell_read_page,
3215 .write_page = marvell_write_page,
d2fa47d9
AL
3216 .get_sset_count = marvell_get_sset_count,
3217 .get_strings = marvell_get_strings,
3218 .get_stats = marvell_get_stats,
6b358aed 3219 },
e4cf8a38 3220 {
1fe976d3 3221 .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
e4cf8a38 3222 .phy_id_mask = MARVELL_PHY_ID_MASK,
1fe976d3 3223 .name = "Marvell 88E6341 Family",
41d26bf4 3224 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
1fe976d3
PR
3225 /* PHY_GBIT_FEATURES */
3226 .flags = PHY_POLL_CABLE_TEST,
41d26bf4 3227 .probe = marvell_probe,
8385b1f0 3228 .config_init = marvell_1011gbe_config_init,
1fe976d3
PR
3229 .config_aneg = m88e6390_config_aneg,
3230 .read_status = marvell_read_status,
3231 .config_intr = marvell_config_intr,
3232 .handle_interrupt = marvell_handle_interrupt,
3233 .resume = genphy_resume,
3234 .suspend = genphy_suspend,
3235 .read_page = marvell_read_page,
3236 .write_page = marvell_write_page,
3237 .get_sset_count = marvell_get_sset_count,
3238 .get_strings = marvell_get_strings,
3239 .get_stats = marvell_get_stats,
3240 .get_tunable = m88e1540_get_tunable,
3241 .set_tunable = m88e1540_set_tunable,
3242 .cable_test_start = marvell_vct7_cable_test_start,
3243 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3244 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3245 },
3246 {
3247 .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
3248 .phy_id_mask = MARVELL_PHY_ID_MASK,
3249 .name = "Marvell 88E6390 Family",
41d26bf4 3250 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops),
dcdecdcf 3251 /* PHY_GBIT_FEATURES */
fc879f72 3252 .flags = PHY_POLL_CABLE_TEST,
41d26bf4 3253 .probe = marvell_probe,
8385b1f0 3254 .config_init = marvell_1011gbe_config_init,
ef0f9545
MK
3255 .config_aneg = m88e6390_config_aneg,
3256 .read_status = marvell_read_status,
ef0f9545 3257 .config_intr = marvell_config_intr,
a0723b37 3258 .handle_interrupt = marvell_handle_interrupt,
ef0f9545
MK
3259 .resume = genphy_resume,
3260 .suspend = genphy_suspend,
424ca4c5
RK
3261 .read_page = marvell_read_page,
3262 .write_page = marvell_write_page,
e4cf8a38
AL
3263 .get_sset_count = marvell_get_sset_count,
3264 .get_strings = marvell_get_strings,
3265 .get_stats = marvell_get_stats,
69f42be8
HK
3266 .get_tunable = m88e1540_get_tunable,
3267 .set_tunable = m88e1540_set_tunable,
fc879f72 3268 .cable_test_start = marvell_vct7_cable_test_start,
0c9bcc1d 3269 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
fc879f72 3270 .cable_test_get_status = marvell_vct7_cable_test_get_status,
e4cf8a38 3271 },
a978f7c4
MB
3272 {
3273 .phy_id = MARVELL_PHY_ID_88E6393_FAMILY,
3274 .phy_id_mask = MARVELL_PHY_ID_MASK,
3275 .name = "Marvell 88E6393 Family",
3276 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6393_hwmon_ops),
3277 /* PHY_GBIT_FEATURES */
3278 .flags = PHY_POLL_CABLE_TEST,
3279 .probe = marvell_probe,
8385b1f0 3280 .config_init = marvell_1011gbe_config_init,
a978f7c4
MB
3281 .config_aneg = m88e1510_config_aneg,
3282 .read_status = marvell_read_status,
3283 .config_intr = marvell_config_intr,
3284 .handle_interrupt = marvell_handle_interrupt,
3285 .resume = genphy_resume,
3286 .suspend = genphy_suspend,
3287 .read_page = marvell_read_page,
3288 .write_page = marvell_write_page,
3289 .get_sset_count = marvell_get_sset_count,
3290 .get_strings = marvell_get_strings,
3291 .get_stats = marvell_get_stats,
3292 .get_tunable = m88e1540_get_tunable,
3293 .set_tunable = m88e1540_set_tunable,
3294 .cable_test_start = marvell_vct7_cable_test_start,
3295 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3296 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3297 },
a602ea86
MK
3298 {
3299 .phy_id = MARVELL_PHY_ID_88E1340S,
3300 .phy_id_mask = MARVELL_PHY_ID_MASK,
3301 .name = "Marvell 88E1340S",
41d26bf4
MB
3302 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3303 .probe = marvell_probe,
a602ea86 3304 /* PHY_GBIT_FEATURES */
8385b1f0 3305 .config_init = marvell_1011gbe_config_init,
a602ea86
MK
3306 .config_aneg = m88e1510_config_aneg,
3307 .read_status = marvell_read_status,
a602ea86 3308 .config_intr = marvell_config_intr,
a0723b37 3309 .handle_interrupt = marvell_handle_interrupt,
a602ea86
MK
3310 .resume = genphy_resume,
3311 .suspend = genphy_suspend,
3312 .read_page = marvell_read_page,
3313 .write_page = marvell_write_page,
3314 .get_sset_count = marvell_get_sset_count,
3315 .get_strings = marvell_get_strings,
3316 .get_stats = marvell_get_stats,
3317 .get_tunable = m88e1540_get_tunable,
3318 .set_tunable = m88e1540_set_tunable,
3319 },
f59babf9
MK
3320 {
3321 .phy_id = MARVELL_PHY_ID_88E1548P,
3322 .phy_id_mask = MARVELL_PHY_ID_MASK,
3323 .name = "Marvell 88E1548P",
41d26bf4
MB
3324 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3325 .probe = marvell_probe,
f59babf9 3326 .features = PHY_GBIT_FIBRE_FEATURES,
8385b1f0 3327 .config_init = marvell_1011gbe_config_init,
f59babf9
MK
3328 .config_aneg = m88e1510_config_aneg,
3329 .read_status = marvell_read_status,
f59babf9 3330 .config_intr = marvell_config_intr,
a0723b37 3331 .handle_interrupt = marvell_handle_interrupt,
f59babf9
MK
3332 .resume = genphy_resume,
3333 .suspend = genphy_suspend,
3334 .read_page = marvell_read_page,
3335 .write_page = marvell_write_page,
3336 .get_sset_count = marvell_get_sset_count,
3337 .get_strings = marvell_get_strings,
3338 .get_stats = marvell_get_stats,
3339 .get_tunable = m88e1540_get_tunable,
3340 .set_tunable = m88e1540_set_tunable,
3341 },
00db8189
AF
3342};
3343
50fd7150 3344module_phy_driver(marvell_drivers);
4e4f10f6 3345
cf93c945 3346static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS
3347 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3348 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3349 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1887023a 3350 { MARVELL_PHY_ID_88E1111_FINISAR, MARVELL_PHY_ID_MASK },
f5e1cabf
MS
3351 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3352 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3353 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3354 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3355 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3356 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 3357 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 3358 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
819ec8e1 3359 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
60f06fde 3360 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
6b358aed 3361 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1fe976d3
PR
3362 { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
3363 { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
a978f7c4 3364 { MARVELL_PHY_ID_88E6393_FAMILY, MARVELL_PHY_ID_MASK },
a602ea86 3365 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
f59babf9 3366 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
4e4f10f6
DW
3367 { }
3368};
3369
3370MODULE_DEVICE_TABLE(mdio, marvell_tbl);