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net/mlx4_core: Fix the slave_id out-of-range test in mlx4_eq_int
[people/ms/linux.git] / include / linux / mlx4 / device.h
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225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
60063497 40#include <linux/atomic.h>
225c7b1f 41
0b7ca5a9
YP		 42#define MAX_MSIX_P_PORT 17
43#define MAX_MSIX 64
44#define MSIX_LEGACY_SZ 4
45#define MIN_MSIX_P_PORT 5
46
225c7b1f
RD		 47enum {
48 MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8 49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
623ed84b
JM		 50 MLX4_FLAG_MASTER = 1 << 2,
51 MLX4_FLAG_SLAVE = 1 << 3,
52 MLX4_FLAG_SRIOV = 1 << 4,
225c7b1f
RD		 53};
54
55enum {
56 MLX4_MAX_PORTS = 2
57};
58
cd9281d8
JM		 59enum {
60 MLX4_BOARD_ID_LEN = 64
61};
62
623ed84b
JM		 63enum {
64 MLX4_MAX_NUM_PF = 16,
65 MLX4_MAX_NUM_VF = 64,
66 MLX4_MFUNC_MAX = 80,
67 MLX4_MFUNC_EQ_NUM = 4,
68 MLX4_MFUNC_MAX_EQES = 8,
69 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
70};
71
225c7b1f 72enum {
52eafc68
OG		 73 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
74 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
75 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
012a8ff5 76 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
52eafc68
OG		 77 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
78 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
79 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
80 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
81 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
82 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
83 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
84 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
85 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
86 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
87 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
88 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
ccf86321
OG		 89 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
90 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
f3a9d1f2 91 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
559a9f1d
OD		 92 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
93 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
ccf86321
OG		 94 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
95 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
f2a3f6a3 96 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
58a60168
YP		 97 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
98 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55
225c7b1f
RD		 99};
100
b3416f44
SP		 101enum {
102 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
103 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
104 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2
105};
106
97285b78
MA		 107#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
108
95d04f07
RD		 109enum {
110 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
111 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
112 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
113 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
114 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
115};
116
225c7b1f
RD		 117enum mlx4_event {
118 MLX4_EVENT_TYPE_COMP = 0x00,
119 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
120 MLX4_EVENT_TYPE_COMM_EST = 0x02,
121 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
122 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
123 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
124 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
125 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
126 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
127 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
128 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
129 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
130 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
131 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
132 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
133 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
134 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
623ed84b
JM		 135 MLX4_EVENT_TYPE_CMD = 0x0a,
136 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
137 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
5984be90 138 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
623ed84b
JM		 139 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
140 MLX4_EVENT_TYPE_NONE = 0xff,
225c7b1f
RD		 141};
142
143enum {
144 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
145 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
146};
147
5984be90
JM		 148enum {
149 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
150};
151
225c7b1f
RD		 152enum {
153 MLX4_PERM_LOCAL_READ = 1 << 10,
154 MLX4_PERM_LOCAL_WRITE = 1 << 11,
155 MLX4_PERM_REMOTE_READ = 1 << 12,
156 MLX4_PERM_REMOTE_WRITE = 1 << 13,
157 MLX4_PERM_ATOMIC = 1 << 14
158};
159
160enum {
161 MLX4_OPCODE_NOP = 0x00,
162 MLX4_OPCODE_SEND_INVAL = 0x01,
163 MLX4_OPCODE_RDMA_WRITE = 0x08,
164 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
165 MLX4_OPCODE_SEND = 0x0a,
166 MLX4_OPCODE_SEND_IMM = 0x0b,
167 MLX4_OPCODE_LSO = 0x0e,
168 MLX4_OPCODE_RDMA_READ = 0x10,
169 MLX4_OPCODE_ATOMIC_CS = 0x11,
170 MLX4_OPCODE_ATOMIC_FA = 0x12,
6fa8f719
VS		 171 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
172 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
225c7b1f
RD		 173 MLX4_OPCODE_BIND_MW = 0x18,
174 MLX4_OPCODE_FMR = 0x19,
175 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
176 MLX4_OPCODE_CONFIG_CMD = 0x1f,
177
178 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
179 MLX4_RECV_OPCODE_SEND = 0x01,
180 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
181 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
182
183 MLX4_CQE_OPCODE_ERROR = 0x1e,
184 MLX4_CQE_OPCODE_RESIZE = 0x16,
185};
186
187enum {
188 MLX4_STAT_RATE_OFFSET = 5
189};
190
da995a8a 191enum mlx4_protocol {
0345584e
YP		 192 MLX4_PROT_IB_IPV6 = 0,
193 MLX4_PROT_ETH,
194 MLX4_PROT_IB_IPV4,
195 MLX4_PROT_FCOE
da995a8a
AS		 196};
197
29bdc883
VS		 198enum {
199 MLX4_MTT_FLAG_PRESENT = 1
200};
201
93fc9e1b
YP		 202enum mlx4_qp_region {
203 MLX4_QP_REGION_FW = 0,
204 MLX4_QP_REGION_ETH_ADDR,
205 MLX4_QP_REGION_FC_ADDR,
206 MLX4_QP_REGION_FC_EXCH,
207 MLX4_NUM_QP_REGION
208};
209
7ff93f8b 210enum mlx4_port_type {
623ed84b 211 MLX4_PORT_TYPE_NONE = 0,
27bf91d6
YP		 212 MLX4_PORT_TYPE_IB = 1,
213 MLX4_PORT_TYPE_ETH = 2,
214 MLX4_PORT_TYPE_AUTO = 3
7ff93f8b
YP		 215};
216
2a2336f8
YP		 217enum mlx4_special_vlan_idx {
218 MLX4_NO_VLAN_IDX = 0,
219 MLX4_VLAN_MISS_IDX,
220 MLX4_VLAN_REGULAR
221};
222
0345584e
YP		 223enum mlx4_steer_type {
224 MLX4_MC_STEER = 0,
225 MLX4_UC_STEER,
226 MLX4_NUM_STEERS
227};
228
93fc9e1b
YP		 229enum {
230 MLX4_NUM_FEXCH = 64 * 1024,
231};
232
5a0fd094
EC		 233enum {
234 MLX4_MAX_FAST_REG_PAGES = 511,
235};
236
ea54b10c
JM		 237static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
238{
239 return (major << 32) | (minor << 16) | subminor;
240}
241
225c7b1f
RD		 242struct mlx4_caps {
243 u64 fw_ver;
623ed84b 244 u32 function;
225c7b1f 245 int num_ports;
5ae2a7a8 246 int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49 247 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
9a5aa622 248 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
b79acb49
YP		 249 u64 def_mac[MLX4_MAX_PORTS + 1];
250 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8
RD		 251 int gid_table_len[MLX4_MAX_PORTS + 1];
252 int pkey_table_len[MLX4_MAX_PORTS + 1];
7699517d
YP		 253 int trans_type[MLX4_MAX_PORTS + 1];
254 int vendor_oui[MLX4_MAX_PORTS + 1];
255 int wavelength[MLX4_MAX_PORTS + 1];
256 u64 trans_code[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 257 int local_ca_ack_delay;
258 int num_uars;
f5311ac1 259 u32 uar_page_size;
225c7b1f
RD		 260 int bf_reg_size;
261 int bf_regs_per_page;
262 int max_sq_sg;
263 int max_rq_sg;
264 int num_qps;
265 int max_wqes;
266 int max_sq_desc_sz;
267 int max_rq_desc_sz;
268 int max_qp_init_rdma;
269 int max_qp_dest_rdma;
225c7b1f
RD		 270 int sqp_start;
271 int num_srqs;
272 int max_srq_wqes;
273 int max_srq_sge;
274 int reserved_srqs;
275 int num_cqs;
276 int max_cqes;
277 int reserved_cqs;
278 int num_eqs;
279 int reserved_eqs;
b8dd786f 280 int num_comp_vectors;
0b7ca5a9 281 int comp_pool;
225c7b1f 282 int num_mpts;
a5bbe892 283 int max_fmr_maps;
2b8fb286 284 int num_mtts;
225c7b1f
RD		 285 int fmr_reserved_mtts;
286 int reserved_mtts;
287 int reserved_mrws;
288 int reserved_uars;
289 int num_mgms;
290 int num_amgms;
291 int reserved_mcgs;
292 int num_qp_per_mgm;
293 int num_pds;
294 int reserved_pds;
012a8ff5
SH		 295 int max_xrcds;
296 int reserved_xrcds;
225c7b1f 297 int mtt_entry_sz;
149983af 298 u32 max_msg_sz;
225c7b1f 299 u32 page_size_cap;
52eafc68 300 u64 flags;
b3416f44 301 u64 flags2;
95d04f07
RD		 302 u32 bmme_flags;
303 u32 reserved_lkey;
225c7b1f 304 u16 stat_rate_support;
5ae2a7a8 305 u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e 306 int max_gso_sz;
b3416f44 307 int max_rss_tbl_sz;
93fc9e1b
YP		 308 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
309 int reserved_qps;
310 int reserved_qps_base[MLX4_NUM_QP_REGION];
311 int log_num_macs;
312 int log_num_vlans;
313 int log_num_prios;
7ff93f8b
YP		 314 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
315 u8 supported_type[MLX4_MAX_PORTS + 1];
8d0fc7b6
YP		 316 u8 suggested_type[MLX4_MAX_PORTS + 1];
317 u8 default_sense[MLX4_MAX_PORTS + 1];
65dab25d 318 u32 port_mask[MLX4_MAX_PORTS + 1];
27bf91d6 319 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
f2a3f6a3 320 u32 max_counters;
096335b3 321 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 322};
323
324struct mlx4_buf_list {
325 void *buf;
326 dma_addr_t map;
327};
328
329struct mlx4_buf {
b57aacfa
RD		 330 struct mlx4_buf_list direct;
331 struct mlx4_buf_list *page_list;
225c7b1f
RD		 332 int nbufs;
333 int npages;
334 int page_shift;
335};
336
337struct mlx4_mtt {
2b8fb286 338 u32 offset;
225c7b1f
RD		 339 int order;
340 int page_shift;
341};
342
6296883c
YP		 343enum {
344 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
345};
346
347struct mlx4_db_pgdir {
348 struct list_head list;
349 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
350 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
351 unsigned long *bits[2];
352 __be32 *db_page;
353 dma_addr_t db_dma;
354};
355
356struct mlx4_ib_user_db_page;
357
358struct mlx4_db {
359 __be32 *db;
360 union {
361 struct mlx4_db_pgdir *pgdir;
362 struct mlx4_ib_user_db_page *user_page;
363 } u;
364 dma_addr_t dma;
365 int index;
366 int order;
367};
368
38ae6a53
YP		 369struct mlx4_hwq_resources {
370 struct mlx4_db db;
371 struct mlx4_mtt mtt;
372 struct mlx4_buf buf;
373};
374
225c7b1f
RD		 375struct mlx4_mr {
376 struct mlx4_mtt mtt;
377 u64 iova;
378 u64 size;
379 u32 key;
380 u32 pd;
381 u32 access;
382 int enabled;
383};
384
8ad11fb6
JM		 385struct mlx4_fmr {
386 struct mlx4_mr mr;
387 struct mlx4_mpt_entry *mpt;
388 __be64 *mtts;
389 dma_addr_t dma_handle;
390 int max_pages;
391 int max_maps;
392 int maps;
393 u8 page_shift;
394};
395
225c7b1f
RD		 396struct mlx4_uar {
397 unsigned long pfn;
398 int index;
c1b43dca
EC		 399 struct list_head bf_list;
400 unsigned free_bf_bmap;
401 void __iomem *map;
402 void __iomem *bf_map;
403};
404
405struct mlx4_bf {
406 unsigned long offset;
407 int buf_size;
408 struct mlx4_uar *uar;
409 void __iomem *reg;
225c7b1f
RD		 410};
411
412struct mlx4_cq {
413 void (*comp) (struct mlx4_cq *);
414 void (*event) (struct mlx4_cq *, enum mlx4_event);
415
416 struct mlx4_uar *uar;
417
418 u32 cons_index;
419
420 __be32 *set_ci_db;
421 __be32 *arm_db;
422 int arm_sn;
423
424 int cqn;
b8dd786f 425 unsigned vector;
225c7b1f
RD		 426
427 atomic_t refcount;
428 struct completion free;
429};
430
431struct mlx4_qp {
432 void (*event) (struct mlx4_qp *, enum mlx4_event);
433
434 int qpn;
435
436 atomic_t refcount;
437 struct completion free;
438};
439
440struct mlx4_srq {
441 void (*event) (struct mlx4_srq *, enum mlx4_event);
442
443 int srqn;
444 int max;
445 int max_gs;
446 int wqe_shift;
447
448 atomic_t refcount;
449 struct completion free;
450};
451
452struct mlx4_av {
453 __be32 port_pd;
454 u8 reserved1;
455 u8 g_slid;
456 __be16 dlid;
457 u8 reserved2;
458 u8 gid_index;
459 u8 stat_rate;
460 u8 hop_limit;
461 __be32 sl_tclass_flowlabel;
462 u8 dgid[16];
463};
464
fa417f7b
EC		 465struct mlx4_eth_av {
466 __be32 port_pd;
467 u8 reserved1;
468 u8 smac_idx;
469 u16 reserved2;
470 u8 reserved3;
471 u8 gid_index;
472 u8 stat_rate;
473 u8 hop_limit;
474 __be32 sl_tclass_flowlabel;
475 u8 dgid[16];
476 u32 reserved4[2];
477 __be16 vlan;
478 u8 mac[6];
479};
480
481union mlx4_ext_av {
482 struct mlx4_av ib;
483 struct mlx4_eth_av eth;
484};
485
f2a3f6a3
OG		 486struct mlx4_counter {
487 u8 reserved1[3];
488 u8 counter_mode;
489 __be32 num_ifc;
490 u32 reserved2[2];
491 __be64 rx_frames;
492 __be64 rx_bytes;
493 __be64 tx_frames;
494 __be64 tx_bytes;
495};
496
225c7b1f
RD		 497struct mlx4_dev {
498 struct pci_dev *pdev;
499 unsigned long flags;
623ed84b 500 unsigned long num_slaves;
225c7b1f
RD		 501 struct mlx4_caps caps;
502 struct radix_tree_root qp_table_tree;
725c8999 503 u8 rev_id;
cd9281d8 504 char board_id[MLX4_BOARD_ID_LEN];
ab9c17a0 505 int num_vfs;
225c7b1f
RD		 506};
507
508struct mlx4_init_port_param {
509 int set_guid0;
510 int set_node_guid;
511 int set_si_guid;
512 u16 mtu;
513 int port_width_cap;
514 u16 vl_cap;
515 u16 max_gid;
516 u16 max_pkey;
517 u64 guid0;
518 u64 node_guid;
519 u64 si_guid;
520};
521
7ff93f8b
YP		 522#define mlx4_foreach_port(port, dev, type) \
523 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
65dab25d 524 if ((type) == (dev)->caps.port_mask[(port)])
7ff93f8b 525
65dab25d
JM		 526#define mlx4_foreach_ib_transport_port(port, dev) \
527 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
528 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
529 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
623ed84b
JM		 530
531static inline int mlx4_is_master(struct mlx4_dev *dev)
532{
533 return dev->flags & MLX4_FLAG_MASTER;
534}
535
536static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
537{
538 return (qpn < dev->caps.sqp_start + 8);
539}
fa417f7b 540
623ed84b
JM		 541static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
542{
543 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
544}
545
546static inline int mlx4_is_slave(struct mlx4_dev *dev)
547{
548 return dev->flags & MLX4_FLAG_SLAVE;
549}
fa417f7b 550
225c7b1f
RD		 551int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
552 struct mlx4_buf *buf);
553void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1c69fc2a
RD		 554static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
555{
313abe55 556 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
b57aacfa 557 return buf->direct.buf + offset;
1c69fc2a 558 else
b57aacfa 559 return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a
RD		 560 (offset & (PAGE_SIZE - 1));
561}
225c7b1f
RD		 562
563int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
564void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
012a8ff5
SH		 565int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
566void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
225c7b1f
RD		 567
568int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
569void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
c1b43dca
EC		 570int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
571void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
225c7b1f
RD		 572
573int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
574 struct mlx4_mtt *mtt);
575void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
576u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
577
578int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
579 int npages, int page_shift, struct mlx4_mr *mr);
580void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
581int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
582int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
583 int start_index, int npages, u64 *page_list);
584int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
585 struct mlx4_buf *buf);
586
6296883c
YP		 587int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
588void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
589
38ae6a53
YP		 590int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
591 int size, int max_direct);
592void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
593 int size);
594
225c7b1f 595int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
e463c7b1 596 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
b8dd786f 597 unsigned vector, int collapsed);
225c7b1f
RD		 598void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
599
a3cdcbfa
YP		 600int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
601void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
602
603int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
225c7b1f
RD		 604void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
605
18abd5ea
SH		 606int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
607 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
225c7b1f
RD		 608void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
609int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
65541cb7 610int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
225c7b1f 611
5ae2a7a8 612int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f
RD		 613int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
614
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EE		 615int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
616 int block_mcast_loopback, enum mlx4_protocol prot);
617int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
618 enum mlx4_protocol prot);
521e575b 619int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
da995a8a
AS		 620 int block_mcast_loopback, enum mlx4_protocol protocol);
621int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
622 enum mlx4_protocol protocol);
1679200f
YP		 623int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
624int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
625int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
626int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
627int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
628
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EE		 629int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
630void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
631int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
632int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
633void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
93ece0c1 634void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
9a9a232a
YP		 635int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
636 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
637int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
638 u8 promisc);
e5395e92
AV		 639int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
640int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
641 u8 *pg, u16 *ratelimit);
4c3eb3ca 642int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
2a2336f8
YP		 643int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
644void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
645
8ad11fb6
JM		 646int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
647 int npages, u64 iova, u32 *lkey, u32 *rkey);
648int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
649 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
650int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
651void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
652 u32 *lkey, u32 *rkey);
653int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
654int mlx4_SYNC_TPT(struct mlx4_dev *dev);
e7c1c2c4 655int mlx4_test_interrupts(struct mlx4_dev *dev);
0b7ca5a9
YP		 656int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
657void mlx4_release_eq(struct mlx4_dev *dev, int vec);
8ad11fb6 658
14c07b13
YP		 659int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
660int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
661
f2a3f6a3
OG		 662int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
663void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
664
225c7b1f 665#endif /* MLX4_DEVICE_H */
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