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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[people/ms/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
25adc137
DH		 40#include <sound/hdaudio.h>
41#include <sound/hda_i915.h>
84eb01be
TI		 42#include "hda_codec.h"
43#include "hda_local.h"
1835a0f9 44#include "hda_jack.h"
84eb01be 45
0ebaa24c
TI		 46static bool static_hdmi_pcm;
47module_param(static_hdmi_pcm, bool, 0644);
48MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
49
7639a06c
TI		 50#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 53#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
432ac1a2 54#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
e2656412 55 || is_skylake(codec) || is_broxton(codec))
75dcbe4d 56
7639a06c
TI		 57#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
58#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 59#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 60
384a48d7
SW		 61struct hdmi_spec_per_cvt {
62 hda_nid_t cvt_nid;
63 int assigned;
64 unsigned int channels_min;
65 unsigned int channels_max;
66 u32 rates;
67 u64 formats;
68 unsigned int maxbps;
69};
079d88cc 70
4eea3091
TI		 71/* max. connections to a widget */
72#define HDA_MAX_CONNECTIONS 32
73
384a48d7
SW		 74struct hdmi_spec_per_pin {
75 hda_nid_t pin_nid;
76 int num_mux_nids;
77 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 78 int mux_idx;
1df5a06a 79 hda_nid_t cvt_nid;
744626da
WF		 80
81 struct hda_codec *codec;
384a48d7 82 struct hdmi_eld sink_eld;
a4e9a38b 83 struct mutex lock;
744626da 84 struct delayed_work work;
92c69e79 85 struct snd_kcontrol *eld_ctl;
c6e8453e 86 int repoll_count;
b054087d
TI		 87 bool setup; /* the stream has been set up by prepare callback */
88 int channels; /* current number of channels */
1a6003b5 89 bool non_pcm;
d45e6889
TI		 90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 92#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 93 struct snd_info_entry *proc_entry;
94#endif
384a48d7 95};
079d88cc 96
307229d2
AH		 97struct cea_channel_speaker_allocation;
98
99/* operations used by generic code that can be overridden by patches */
100struct hdmi_ops {
101 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
102 unsigned char *buf, int *eld_size);
103
104 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
105 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
106 int asp_slot);
107 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
108 int asp_slot, int channel);
109
110 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
111 int ca, int active_channels, int conn_type);
112
113 /* enable/disable HBR (HD passthrough) */
114 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
115
116 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
117 hda_nid_t pin_nid, u32 stream_tag, int format);
118
119 /* Helpers for producing the channel map TLVs. These can be overridden
120 * for devices that have non-standard mapping requirements. */
121 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
122 int channels);
123 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
124 unsigned int *chmap, int channels);
125
126 /* check that the user-given chmap is supported */
127 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
128};
129
384a48d7
SW		 130struct hdmi_spec {
131 int num_cvts;
bce0d2a8
TI		 132 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
133 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 134
384a48d7 135 int num_pins;
bce0d2a8 136 struct snd_array pins; /* struct hdmi_spec_per_pin */
bbbc7e85 137 struct hda_pcm *pcm_rec[16];
d45e6889 138 unsigned int channels_max; /* max over all cvts */
079d88cc 139
4bd038f9 140 struct hdmi_eld temp_eld;
307229d2 141 struct hdmi_ops ops;
75fae117
SW		 142
143 bool dyn_pin_out;
144
079d88cc 145 /*
5a613584 146 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 147 */
148 struct hda_multi_out multiout;
d0b1252d 149 struct hda_pcm_stream pcm_playback;
25adc137
DH		 150
151 /* i915/powerwell (Haswell+/Valleyview+) specific */
152 struct i915_audio_component_audio_ops i915_audio_ops;
079d88cc
WF		 153};
154
155
156struct hdmi_audio_infoframe {
157 u8 type; /* 0x84 */
158 u8 ver; /* 0x01 */
159 u8 len; /* 0x0a */
160
53d7d69d
WF		 161 u8 checksum;
162
079d88cc
WF		 163 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
164 u8 SS01_SF24;
165 u8 CXT04;
166 u8 CA;
167 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 168};
169
170struct dp_audio_infoframe {
171 u8 type; /* 0x84 */
172 u8 len; /* 0x1b */
173 u8 ver; /* 0x11 << 2 */
174
175 u8 CC02_CT47; /* match with HDMI infoframe from this on */
176 u8 SS01_SF24;
177 u8 CXT04;
178 u8 CA;
179 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 180};
181
2b203dbb
TI		 182union audio_infoframe {
183 struct hdmi_audio_infoframe hdmi;
184 struct dp_audio_infoframe dp;
185 u8 bytes[0];
186};
187
079d88cc
WF		 188/*
189 * CEA speaker placement:
190 *
191 * FLH FCH FRH
192 * FLW FL FLC FC FRC FR FRW
193 *
194 * LFE
195 * TC
196 *
197 * RL RLC RC RRC RR
198 *
199 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
200 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
201 */
202enum cea_speaker_placement {
203 FL = (1 << 0), /* Front Left */
204 FC = (1 << 1), /* Front Center */
205 FR = (1 << 2), /* Front Right */
206 FLC = (1 << 3), /* Front Left Center */
207 FRC = (1 << 4), /* Front Right Center */
208 RL = (1 << 5), /* Rear Left */
209 RC = (1 << 6), /* Rear Center */
210 RR = (1 << 7), /* Rear Right */
211 RLC = (1 << 8), /* Rear Left Center */
212 RRC = (1 << 9), /* Rear Right Center */
213 LFE = (1 << 10), /* Low Frequency Effect */
214 FLW = (1 << 11), /* Front Left Wide */
215 FRW = (1 << 12), /* Front Right Wide */
216 FLH = (1 << 13), /* Front Left High */
217 FCH = (1 << 14), /* Front Center High */
218 FRH = (1 << 15), /* Front Right High */
219 TC = (1 << 16), /* Top Center */
220};
221
222/*
223 * ELD SA bits in the CEA Speaker Allocation data block
224 */
225static int eld_speaker_allocation_bits[] = {
226 [0] = FL | FR,
227 [1] = LFE,
228 [2] = FC,
229 [3] = RL | RR,
230 [4] = RC,
231 [5] = FLC | FRC,
232 [6] = RLC | RRC,
233 /* the following are not defined in ELD yet */
234 [7] = FLW | FRW,
235 [8] = FLH | FRH,
236 [9] = TC,
237 [10] = FCH,
238};
239
240struct cea_channel_speaker_allocation {
241 int ca_index;
242 int speakers[8];
243
244 /* derived values, just for convenience */
245 int channels;
246 int spk_mask;
247};
248
249/*
250 * ALSA sequence is:
251 *
252 * surround40 surround41 surround50 surround51 surround71
253 * ch0 front left = = = =
254 * ch1 front right = = = =
255 * ch2 rear left = = = =
256 * ch3 rear right = = = =
257 * ch4 LFE center center center
258 * ch5 LFE LFE
259 * ch6 side left
260 * ch7 side right
261 *
262 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
263 */
264static int hdmi_channel_mapping[0x32][8] = {
265 /* stereo */
266 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
267 /* 2.1 */
268 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
269 /* Dolby Surround */
270 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
271 /* surround40 */
272 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
273 /* 4ch */
274 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
275 /* surround41 */
9396d317 276 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 277 /* surround50 */
278 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
279 /* surround51 */
280 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
281 /* 7.1 */
282 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
283};
284
285/*
286 * This is an ordered list!
287 *
288 * The preceding ones have better chances to be selected by
53d7d69d 289 * hdmi_channel_allocation().
079d88cc
WF		 290 */
291static struct cea_channel_speaker_allocation channel_allocations[] = {
292/* channel: 7 6 5 4 3 2 1 0 */
293{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
294 /* 2.1 */
295{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
296 /* Dolby Surround */
297{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
298 /* surround40 */
299{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
300 /* surround41 */
301{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
302 /* surround50 */
303{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
304 /* surround51 */
305{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
306 /* 6.1 */
307{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
308 /* surround71 */
309{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
310
311{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
312{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
313{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
314{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
315{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
316{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
317{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
318{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
319{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
320{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
321{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
322{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
323{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
324{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
325{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
326{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
327{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
328{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
329{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
330{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
331{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
332{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
333{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
334{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
335{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
336{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
337{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
338{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
339{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
340{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
341{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
342{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
343{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
344{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
345{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
346{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
347{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
348{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
349{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
350{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
351{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
352};
353
354
355/*
356 * HDMI routines
357 */
358
bce0d2a8
TI		 359#define get_pin(spec, idx) \
360 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
361#define get_cvt(spec, idx) \
362 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
bbbc7e85 363#define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
bce0d2a8 364
4e76a883 365static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 366{
4e76a883 367 struct hdmi_spec *spec = codec->spec;
384a48d7 368 int pin_idx;
079d88cc 369
384a48d7 370 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 371 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 372 return pin_idx;
079d88cc 373
4e76a883 374 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 375 return -EINVAL;
376}
377
4e76a883 378static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 379 struct hda_pcm_stream *hinfo)
380{
4e76a883 381 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 382 int pin_idx;
383
384 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 385 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 386 return pin_idx;
387
4e76a883 388 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 389 return -EINVAL;
390}
391
4e76a883 392static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 393{
4e76a883 394 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 395 int cvt_idx;
396
397 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 398 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 399 return cvt_idx;
400
4e76a883 401 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 402 return -EINVAL;
403}
404
14bc52b8
PLB		 405static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
406 struct snd_ctl_elem_info *uinfo)
407{
408 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 409 struct hdmi_spec *spec = codec->spec;
a4e9a38b 410 struct hdmi_spec_per_pin *per_pin;
68e03de9 411 struct hdmi_eld *eld;
14bc52b8
PLB		 412 int pin_idx;
413
14bc52b8
PLB		 414 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
415
416 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 417 per_pin = get_pin(spec, pin_idx);
418 eld = &per_pin->sink_eld;
68e03de9 419
a4e9a38b 420 mutex_lock(&per_pin->lock);
68e03de9 421 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 422 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 423
424 return 0;
425}
426
427static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
429{
430 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 431 struct hdmi_spec *spec = codec->spec;
a4e9a38b 432 struct hdmi_spec_per_pin *per_pin;
68e03de9 433 struct hdmi_eld *eld;
14bc52b8
PLB		 434 int pin_idx;
435
14bc52b8 436 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 437 per_pin = get_pin(spec, pin_idx);
438 eld = &per_pin->sink_eld;
68e03de9 439
a4e9a38b 440 mutex_lock(&per_pin->lock);
68e03de9 441 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 442 mutex_unlock(&per_pin->lock);
68e03de9
DH		 443 snd_BUG();
444 return -EINVAL;
445 }
446
447 memset(ucontrol->value.bytes.data, 0,
448 ARRAY_SIZE(ucontrol->value.bytes.data));
449 if (eld->eld_valid)
450 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
451 eld->eld_size);
a4e9a38b 452 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 453
454 return 0;
455}
456
457static struct snd_kcontrol_new eld_bytes_ctl = {
458 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
459 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
460 .name = "ELD",
461 .info = hdmi_eld_ctl_info,
462 .get = hdmi_eld_ctl_get,
463};
464
465static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
466 int device)
467{
468 struct snd_kcontrol *kctl;
469 struct hdmi_spec *spec = codec->spec;
470 int err;
471
472 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
473 if (!kctl)
474 return -ENOMEM;
475 kctl->private_value = pin_idx;
476 kctl->id.device = device;
477
bce0d2a8 478 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 479 if (err < 0)
480 return err;
481
bce0d2a8 482 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 483 return 0;
484}
485
079d88cc
WF		 486#ifdef BE_PARANOID
487static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
488 int *packet_index, int *byte_index)
489{
490 int val;
491
492 val = snd_hda_codec_read(codec, pin_nid, 0,
493 AC_VERB_GET_HDMI_DIP_INDEX, 0);
494
495 *packet_index = val >> 5;
496 *byte_index = val & 0x1f;
497}
498#endif
499
500static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
501 int packet_index, int byte_index)
502{
503 int val;
504
505 val = (packet_index << 5) | (byte_index & 0x1f);
506
507 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
508}
509
510static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
511 unsigned char val)
512{
513 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
514}
515
384a48d7 516static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 517{
75fae117
SW		 518 struct hdmi_spec *spec = codec->spec;
519 int pin_out;
520
079d88cc
WF		 521 /* Unmute */
522 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
523 snd_hda_codec_write(codec, pin_nid, 0,
524 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 525
526 if (spec->dyn_pin_out)
527 /* Disable pin out until stream is active */
528 pin_out = 0;
529 else
530 /* Enable pin out: some machines with GM965 gets broken output
531 * when the pin is disabled or changed while using with HDMI
532 */
533 pin_out = PIN_OUT;
534
079d88cc 535 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 536 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 537}
538
384a48d7 539static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 540{
384a48d7 541 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 542 AC_VERB_GET_CVT_CHAN_COUNT, 0);
543}
544
545static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 546 hda_nid_t cvt_nid, int chs)
079d88cc 547{
384a48d7
SW		 548 if (chs != hdmi_get_channel_count(codec, cvt_nid))
549 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 550 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
551}
552
a4e9a38b
TI		 553/*
554 * ELD proc files
555 */
556
cd6a6503 557#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 558static void print_eld_info(struct snd_info_entry *entry,
559 struct snd_info_buffer *buffer)
560{
561 struct hdmi_spec_per_pin *per_pin = entry->private_data;
562
563 mutex_lock(&per_pin->lock);
564 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
565 mutex_unlock(&per_pin->lock);
566}
567
568static void write_eld_info(struct snd_info_entry *entry,
569 struct snd_info_buffer *buffer)
570{
571 struct hdmi_spec_per_pin *per_pin = entry->private_data;
572
573 mutex_lock(&per_pin->lock);
574 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
575 mutex_unlock(&per_pin->lock);
576}
577
578static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
579{
580 char name[32];
581 struct hda_codec *codec = per_pin->codec;
582 struct snd_info_entry *entry;
583 int err;
584
585 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 586 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 587 if (err < 0)
588 return err;
589
590 snd_info_set_text_ops(entry, per_pin, print_eld_info);
591 entry->c.text.write = write_eld_info;
592 entry->mode |= S_IWUSR;
593 per_pin->proc_entry = entry;
594
595 return 0;
596}
597
598static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
599{
1947a114 600 if (!per_pin->codec->bus->shutdown) {
c560a679 601 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 602 per_pin->proc_entry = NULL;
603 }
604}
605#else
b55447a7
TI		 606static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
607 int index)
a4e9a38b
TI		 608{
609 return 0;
610}
b55447a7 611static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 612{
613}
614#endif
079d88cc
WF		 615
616/*
617 * Channel mapping routines
618 */
619
620/*
621 * Compute derived values in channel_allocations[].
622 */
623static void init_channel_allocations(void)
624{
625 int i, j;
626 struct cea_channel_speaker_allocation *p;
627
628 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
629 p = channel_allocations + i;
630 p->channels = 0;
631 p->spk_mask = 0;
632 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
633 if (p->speakers[j]) {
634 p->channels++;
635 p->spk_mask |= p->speakers[j];
636 }
637 }
638}
639
72357c78
WX		 640static int get_channel_allocation_order(int ca)
641{
642 int i;
643
644 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
645 if (channel_allocations[i].ca_index == ca)
646 break;
647 }
648 return i;
649}
650
079d88cc
WF		 651/*
652 * The transformation takes two steps:
653 *
654 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
655 * spk_mask => (channel_allocations[]) => ai->CA
656 *
657 * TODO: it could select the wrong CA from multiple candidates.
658*/
79514d47
TI		 659static int hdmi_channel_allocation(struct hda_codec *codec,
660 struct hdmi_eld *eld, int channels)
079d88cc 661{
079d88cc 662 int i;
53d7d69d 663 int ca = 0;
079d88cc 664 int spk_mask = 0;
079d88cc
WF		 665 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
666
667 /*
668 * CA defaults to 0 for basic stereo audio
669 */
670 if (channels <= 2)
671 return 0;
672
079d88cc
WF		 673 /*
674 * expand ELD's speaker allocation mask
675 *
676 * ELD tells the speaker mask in a compact(paired) form,
677 * expand ELD's notions to match the ones used by Audio InfoFrame.
678 */
679 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 680 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 681 spk_mask |= eld_speaker_allocation_bits[i];
682 }
683
684 /* search for the first working match in the CA table */
685 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
686 if (channels == channel_allocations[i].channels &&
687 (spk_mask & channel_allocations[i].spk_mask) ==
688 channel_allocations[i].spk_mask) {
53d7d69d 689 ca = channel_allocations[i].ca_index;
079d88cc
WF		 690 break;
691 }
692 }
693
18e39186
AH		 694 if (!ca) {
695 /* if there was no match, select the regular ALSA channel
696 * allocation with the matching number of channels */
697 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
698 if (channels == channel_allocations[i].channels) {
699 ca = channel_allocations[i].ca_index;
700 break;
701 }
702 }
703 }
704
1613d6b4 705 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
79514d47 706 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 707 ca, channels, buf);
079d88cc 708
53d7d69d 709 return ca;
079d88cc
WF		 710}
711
712static void hdmi_debug_channel_mapping(struct hda_codec *codec,
713 hda_nid_t pin_nid)
714{
715#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 716 struct hdmi_spec *spec = codec->spec;
079d88cc 717 int i;
307229d2 718 int channel;
079d88cc
WF		 719
720 for (i = 0; i < 8; i++) {
307229d2 721 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 722 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 723 channel, i);
079d88cc
WF		 724 }
725#endif
726}
727
d45e6889 728static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 729 hda_nid_t pin_nid,
433968da 730 bool non_pcm,
53d7d69d 731 int ca)
079d88cc 732{
307229d2 733 struct hdmi_spec *spec = codec->spec;
90f28002 734 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 735 int i;
079d88cc 736 int err;
72357c78 737 int order;
433968da 738 int non_pcm_mapping[8];
079d88cc 739
72357c78 740 order = get_channel_allocation_order(ca);
90f28002 741 ch_alloc = &channel_allocations[order];
433968da 742
079d88cc 743 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 744 int hdmi_slot = 0;
745 /* fill actual channel mappings in ALSA channel (i) order */
746 for (i = 0; i < ch_alloc->channels; i++) {
747 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
748 hdmi_slot++; /* skip zero slots */
749
750 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
751 }
752 /* fill the rest of the slots with ALSA channel 0xf */
753 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
754 if (!ch_alloc->speakers[7 - hdmi_slot])
755 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 756 }
757
433968da 758 if (non_pcm) {
90f28002 759 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 760 non_pcm_mapping[i] = (i << 4) | i;
433968da 761 for (; i < 8; i++)
11f7c52d 762 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 763 }
764
079d88cc 765 for (i = 0; i < 8; i++) {
307229d2
AH		 766 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
767 int hdmi_slot = slotsetup & 0x0f;
768 int channel = (slotsetup & 0xf0) >> 4;
769 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 770 if (err) {
4e76a883 771 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 772 break;
773 }
774 }
079d88cc
WF		 775}
776
d45e6889
TI		 777struct channel_map_table {
778 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 779 int spk_mask; /* speaker position bit mask */
780};
781
782static struct channel_map_table map_tables[] = {
a5b7d510
AH		 783 { SNDRV_CHMAP_FL, FL },
784 { SNDRV_CHMAP_FR, FR },
785 { SNDRV_CHMAP_RL, RL },
786 { SNDRV_CHMAP_RR, RR },
787 { SNDRV_CHMAP_LFE, LFE },
788 { SNDRV_CHMAP_FC, FC },
789 { SNDRV_CHMAP_RLC, RLC },
790 { SNDRV_CHMAP_RRC, RRC },
791 { SNDRV_CHMAP_RC, RC },
792 { SNDRV_CHMAP_FLC, FLC },
793 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 794 { SNDRV_CHMAP_TFL, FLH },
795 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 796 { SNDRV_CHMAP_FLW, FLW },
797 { SNDRV_CHMAP_FRW, FRW },
798 { SNDRV_CHMAP_TC, TC },
94908a39 799 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 800 {} /* terminator */
801};
802
803/* from ALSA API channel position to speaker bit mask */
804static int to_spk_mask(unsigned char c)
805{
806 struct channel_map_table *t = map_tables;
807 for (; t->map; t++) {
808 if (t->map == c)
809 return t->spk_mask;
810 }
811 return 0;
812}
813
814/* from ALSA API channel position to CEA slot */
a5b7d510 815static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 816{
a5b7d510
AH		 817 int mask = to_spk_mask(pos);
818 int i;
d45e6889 819
a5b7d510
AH		 820 if (mask) {
821 for (i = 0; i < 8; i++) {
822 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
823 return i;
824 }
d45e6889 825 }
a5b7d510
AH		 826
827 return -1;
d45e6889
TI		 828}
829
830/* from speaker bit mask to ALSA API channel position */
831static int spk_to_chmap(int spk)
832{
833 struct channel_map_table *t = map_tables;
834 for (; t->map; t++) {
835 if (t->spk_mask == spk)
836 return t->map;
837 }
838 return 0;
839}
840
a5b7d510
AH		 841/* from CEA slot to ALSA API channel position */
842static int from_cea_slot(int ordered_ca, unsigned char slot)
843{
844 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
845
846 return spk_to_chmap(mask);
847}
848
d45e6889
TI		 849/* get the CA index corresponding to the given ALSA API channel map */
850static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
851{
852 int i, spks = 0, spk_mask = 0;
853
854 for (i = 0; i < chs; i++) {
855 int mask = to_spk_mask(map[i]);
856 if (mask) {
857 spk_mask |= mask;
858 spks++;
859 }
860 }
861
862 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
863 if ((chs == channel_allocations[i].channels ||
864 spks == channel_allocations[i].channels) &&
865 (spk_mask & channel_allocations[i].spk_mask) ==
866 channel_allocations[i].spk_mask)
867 return channel_allocations[i].ca_index;
868 }
869 return -1;
870}
871
872/* set up the channel slots for the given ALSA API channel map */
873static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
874 hda_nid_t pin_nid,
a5b7d510
AH		 875 int chs, unsigned char *map,
876 int ca)
d45e6889 877{
307229d2 878 struct hdmi_spec *spec = codec->spec;
a5b7d510 879 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 880 int alsa_pos, hdmi_slot;
881 int assignments[8] = {[0 ... 7] = 0xf};
882
883 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
884
a5b7d510 885 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 886
887 if (hdmi_slot < 0)
888 continue; /* unassigned channel */
889
890 assignments[hdmi_slot] = alsa_pos;
891 }
892
893 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 894 int err;
11f7c52d 895
307229d2
AH		 896 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
897 assignments[hdmi_slot]);
d45e6889
TI		 898 if (err)
899 return -EINVAL;
900 }
901 return 0;
902}
903
904/* store ALSA API channel map from the current default map */
905static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
906{
907 int i;
56cac413 908 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 909 for (i = 0; i < 8; i++) {
56cac413 910 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 911 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 912 else
913 map[i] = 0;
914 }
915}
916
917static void hdmi_setup_channel_mapping(struct hda_codec *codec,
918 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 919 int channels, unsigned char *map,
920 bool chmap_set)
d45e6889 921{
20608731 922 if (!non_pcm && chmap_set) {
d45e6889 923 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 924 channels, map, ca);
d45e6889
TI		 925 } else {
926 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
927 hdmi_setup_fake_chmap(map, ca);
928 }
980b2495
AH		 929
930 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 931}
079d88cc 932
307229d2
AH		 933static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
934 int asp_slot, int channel)
935{
936 return snd_hda_codec_write(codec, pin_nid, 0,
937 AC_VERB_SET_HDMI_CHAN_SLOT,
938 (channel << 4) | asp_slot);
939}
940
941static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
942 int asp_slot)
943{
944 return (snd_hda_codec_read(codec, pin_nid, 0,
945 AC_VERB_GET_HDMI_CHAN_SLOT,
946 asp_slot) & 0xf0) >> 4;
947}
948
079d88cc
WF		 949/*
950 * Audio InfoFrame routines
951 */
952
953/*
954 * Enable Audio InfoFrame Transmission
955 */
956static void hdmi_start_infoframe_trans(struct hda_codec *codec,
957 hda_nid_t pin_nid)
958{
959 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
960 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
961 AC_DIPXMIT_BEST);
962}
963
964/*
965 * Disable Audio InfoFrame Transmission
966 */
967static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
968 hda_nid_t pin_nid)
969{
970 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
971 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
972 AC_DIPXMIT_DISABLE);
973}
974
975static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
976{
977#ifdef CONFIG_SND_DEBUG_VERBOSE
978 int i;
979 int size;
980
981 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 982 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 983
984 for (i = 0; i < 8; i++) {
985 size = snd_hda_codec_read(codec, pin_nid, 0,
986 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 987 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 988 }
989#endif
990}
991
992static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
993{
994#ifdef BE_PARANOID
995 int i, j;
996 int size;
997 int pi, bi;
998 for (i = 0; i < 8; i++) {
999 size = snd_hda_codec_read(codec, pin_nid, 0,
1000 AC_VERB_GET_HDMI_DIP_SIZE, i);
1001 if (size == 0)
1002 continue;
1003
1004 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1005 for (j = 1; j < 1000; j++) {
1006 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1007 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1008 if (pi != i)
4e76a883 1009 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1010 bi, pi, i);
1011 if (bi == 0) /* byte index wrapped around */
1012 break;
1013 }
4e76a883 1014 codec_dbg(codec,
079d88cc
WF		 1015 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1016 i, size, j);
1017 }
1018#endif
1019}
1020
53d7d69d 1021static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1022{
53d7d69d 1023 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1024 u8 sum = 0;
1025 int i;
1026
53d7d69d 1027 hdmi_ai->checksum = 0;
079d88cc 1028
53d7d69d 1029 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1030 sum += bytes[i];
1031
53d7d69d 1032 hdmi_ai->checksum = -sum;
079d88cc
WF		 1033}
1034
1035static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1036 hda_nid_t pin_nid,
53d7d69d 1037 u8 *dip, int size)
079d88cc 1038{
079d88cc
WF		 1039 int i;
1040
1041 hdmi_debug_dip_size(codec, pin_nid);
1042 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1043
079d88cc 1044 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1045 for (i = 0; i < size; i++)
1046 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1047}
1048
1049static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1050 u8 *dip, int size)
079d88cc 1051{
079d88cc
WF		 1052 u8 val;
1053 int i;
1054
1055 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1056 != AC_DIPXMIT_BEST)
1057 return false;
1058
1059 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1060 for (i = 0; i < size; i++) {
079d88cc
WF		 1061 val = snd_hda_codec_read(codec, pin_nid, 0,
1062 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1063 if (val != dip[i])
079d88cc
WF		 1064 return false;
1065 }
1066
1067 return true;
1068}
1069
307229d2
AH		 1070static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1071 hda_nid_t pin_nid,
1072 int ca, int active_channels,
1073 int conn_type)
1074{
1075 union audio_infoframe ai;
1076
caaf5ef9 1077 memset(&ai, 0, sizeof(ai));
307229d2
AH		 1078 if (conn_type == 0) { /* HDMI */
1079 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1080
1081 hdmi_ai->type = 0x84;
1082 hdmi_ai->ver = 0x01;
1083 hdmi_ai->len = 0x0a;
1084 hdmi_ai->CC02_CT47 = active_channels - 1;
1085 hdmi_ai->CA = ca;
1086 hdmi_checksum_audio_infoframe(hdmi_ai);
1087 } else if (conn_type == 1) { /* DisplayPort */
1088 struct dp_audio_infoframe *dp_ai = &ai.dp;
1089
1090 dp_ai->type = 0x84;
1091 dp_ai->len = 0x1b;
1092 dp_ai->ver = 0x11 << 2;
1093 dp_ai->CC02_CT47 = active_channels - 1;
1094 dp_ai->CA = ca;
1095 } else {
4e76a883 1096 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1097 pin_nid);
1098 return;
1099 }
1100
1101 /*
1102 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1103 * sizeof(*dp_ai) to avoid partial match/update problems when
1104 * the user switches between HDMI/DP monitors.
1105 */
1106 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1107 sizeof(ai))) {
4e76a883
TI		 1108 codec_dbg(codec,
1109 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1110 pin_nid,
1111 active_channels, ca);
1112 hdmi_stop_infoframe_trans(codec, pin_nid);
1113 hdmi_fill_audio_infoframe(codec, pin_nid,
1114 ai.bytes, sizeof(ai));
1115 hdmi_start_infoframe_trans(codec, pin_nid);
1116 }
1117}
1118
b054087d
TI		 1119static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1120 struct hdmi_spec_per_pin *per_pin,
1121 bool non_pcm)
079d88cc 1122{
307229d2 1123 struct hdmi_spec *spec = codec->spec;
384a48d7 1124 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1125 int channels = per_pin->channels;
1df5a06a 1126 int active_channels;
384a48d7 1127 struct hdmi_eld *eld;
1df5a06a 1128 int ca, ordered_ca;
079d88cc 1129
b054087d
TI		 1130 if (!channels)
1131 return;
1132
75dcbe4d 1133 if (is_haswell_plus(codec))
58f7d28d
ML		 1134 snd_hda_codec_write(codec, pin_nid, 0,
1135 AC_VERB_SET_AMP_GAIN_MUTE,
1136 AMP_OUT_UNMUTE);
1137
bce0d2a8 1138 eld = &per_pin->sink_eld;
079d88cc 1139
d45e6889
TI		 1140 if (!non_pcm && per_pin->chmap_set)
1141 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1142 else
79514d47 1143 ca = hdmi_channel_allocation(codec, eld, channels);
d45e6889
TI		 1144 if (ca < 0)
1145 ca = 0;
384a48d7 1146
1df5a06a
AH		 1147 ordered_ca = get_channel_allocation_order(ca);
1148 active_channels = channel_allocations[ordered_ca].channels;
1149
1150 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1151
39edac70
AH		 1152 /*
1153 * always configure channel mapping, it may have been changed by the
1154 * user in the meantime
1155 */
1156 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1157 channels, per_pin->chmap,
1158 per_pin->chmap_set);
1159
307229d2
AH		 1160 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1161 eld->info.conn_type);
433968da 1162
1a6003b5 1163 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1164}
1165
079d88cc
WF		 1166/*
1167 * Unsolicited events
1168 */
1169
efe47108 1170static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1171
1a4f69d5 1172static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
079d88cc
WF		 1173{
1174 struct hdmi_spec *spec = codec->spec;
1a4f69d5
TI		 1175 int pin_idx = pin_nid_to_pin_index(codec, nid);
1176
20ce9029
DH		 1177 if (pin_idx < 0)
1178 return;
20ce9029
DH		 1179 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1180 snd_hda_jack_report_sync(codec);
1181}
1182
1a4f69d5
TI		 1183static void jack_callback(struct hda_codec *codec,
1184 struct hda_jack_callback *jack)
1185{
1186 check_presence_and_report(codec, jack->tbl->nid);
1187}
1188
20ce9029
DH		 1189static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1190{
3a93897e 1191 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1192 struct hda_jack_tbl *jack;
2e59e5ab 1193 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1194
1195 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1196 if (!jack)
1197 return;
3a93897e 1198 jack->jack_dirty = 1;
079d88cc 1199
4e76a883 1200 codec_dbg(codec,
2e59e5ab 1201 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1202 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1203 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1204
1a4f69d5 1205 check_presence_and_report(codec, jack->nid);
079d88cc
WF		 1206}
1207
1208static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1209{
1210 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1211 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1212 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1213 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1214
4e76a883 1215 codec_info(codec,
e9ea8e8f 1216 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1217 codec->addr,
079d88cc
WF		 1218 tag,
1219 subtag,
1220 cp_state,
1221 cp_ready);
1222
1223 /* TODO */
1224 if (cp_state)
1225 ;
1226 if (cp_ready)
1227 ;
1228}
1229
1230
1231static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1232{
079d88cc
WF		 1233 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1234 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1235
3a93897e 1236 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1237 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1238 return;
1239 }
1240
1241 if (subtag == 0)
1242 hdmi_intrinsic_event(codec, res);
1243 else
1244 hdmi_non_intrinsic_event(codec, res);
1245}
1246
58f7d28d 1247static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1248 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1249{
58f7d28d 1250 int pwr;
83f26ad2 1251
53b434f0
WX		 1252 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1253 * thus pins could only choose converter 0 for use. Make sure the
1254 * converters are in correct power state */
fd678cac 1255 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1256 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1257
fd678cac 1258 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1259 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1260 AC_PWRST_D0);
1261 msleep(40);
1262 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1263 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1264 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1265 }
83f26ad2
DH		 1266}
1267
079d88cc
WF		 1268/*
1269 * Callbacks
1270 */
1271
92f10b3f
TI		 1272/* HBR should be Non-PCM, 8 channels */
1273#define is_hbr_format(format) \
1274 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1275
307229d2
AH		 1276static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1277 bool hbr)
079d88cc 1278{
307229d2 1279 int pinctl, new_pinctl;
83f26ad2 1280
384a48d7
SW		 1281 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1282 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1283 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1284
13122e6e
AH		 1285 if (pinctl < 0)
1286 return hbr ? -EINVAL : 0;
1287
ea87d1c4 1288 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1289 if (hbr)
ea87d1c4
AH		 1290 new_pinctl |= AC_PINCTL_EPT_HBR;
1291 else
1292 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1293
4e76a883
TI		 1294 codec_dbg(codec,
1295 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1296 pin_nid,
ea87d1c4
AH		 1297 pinctl == new_pinctl ? "" : "new-",
1298 new_pinctl);
1299
1300 if (pinctl != new_pinctl)
384a48d7 1301 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1302 AC_VERB_SET_PIN_WIDGET_CONTROL,
1303 new_pinctl);
307229d2
AH		 1304 } else if (hbr)
1305 return -EINVAL;
ea87d1c4 1306
307229d2
AH		 1307 return 0;
1308}
1309
1310static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1311 hda_nid_t pin_nid, u32 stream_tag, int format)
1312{
1313 struct hdmi_spec *spec = codec->spec;
1314 int err;
1315
75dcbe4d 1316 if (is_haswell_plus(codec))
307229d2
AH		 1317 haswell_verify_D0(codec, cvt_nid, pin_nid);
1318
1319 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1320
1321 if (err) {
4e76a883 1322 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1323 return err;
ea87d1c4 1324 }
079d88cc 1325
384a48d7 1326 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1327 return 0;
079d88cc
WF		 1328}
1329
7ef166b8
WX		 1330static int hdmi_choose_cvt(struct hda_codec *codec,
1331 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1332{
1333 struct hdmi_spec *spec = codec->spec;
384a48d7 1334 struct hdmi_spec_per_pin *per_pin;
384a48d7 1335 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1336 int cvt_idx, mux_idx = 0;
bbbe3390 1337
bce0d2a8 1338 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1339
1340 /* Dynamically assign converter to stream */
1341 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1342 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1343
384a48d7
SW		 1344 /* Must not already be assigned */
1345 if (per_cvt->assigned)
1346 continue;
1347 /* Must be in pin's mux's list of converters */
1348 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1349 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1350 break;
1351 /* Not in mux list */
1352 if (mux_idx == per_pin->num_mux_nids)
1353 continue;
1354 break;
1355 }
7ef166b8 1356
384a48d7
SW		 1357 /* No free converters */
1358 if (cvt_idx == spec->num_cvts)
1359 return -ENODEV;
1360
2df6742f
ML		 1361 per_pin->mux_idx = mux_idx;
1362
7ef166b8
WX		 1363 if (cvt_id)
1364 *cvt_id = cvt_idx;
1365 if (mux_id)
1366 *mux_id = mux_idx;
1367
1368 return 0;
1369}
1370
2df6742f
ML		 1371/* Assure the pin select the right convetor */
1372static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1373 struct hdmi_spec_per_pin *per_pin)
1374{
1375 hda_nid_t pin_nid = per_pin->pin_nid;
1376 int mux_idx, curr;
1377
1378 mux_idx = per_pin->mux_idx;
1379 curr = snd_hda_codec_read(codec, pin_nid, 0,
1380 AC_VERB_GET_CONNECT_SEL, 0);
1381 if (curr != mux_idx)
1382 snd_hda_codec_write_cache(codec, pin_nid, 0,
1383 AC_VERB_SET_CONNECT_SEL,
1384 mux_idx);
1385}
1386
300016b9
ML		 1387/* Intel HDMI workaround to fix audio routing issue:
1388 * For some Intel display codecs, pins share the same connection list.
1389 * So a conveter can be selected by multiple pins and playback on any of these
1390 * pins will generate sound on the external display, because audio flows from
1391 * the same converter to the display pipeline. Also muting one pin may make
1392 * other pins have no sound output.
1393 * So this function assures that an assigned converter for a pin is not selected
1394 * by any other pins.
1395 */
1396static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1397 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1398{
1399 struct hdmi_spec *spec = codec->spec;
7639a06c 1400 hda_nid_t nid;
f82d7d16
ML		 1401 int cvt_idx, curr;
1402 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1403
f82d7d16 1404 /* configure all pins, including "no physical connection" ones */
7639a06c 1405 for_each_hda_codec_node(nid, codec) {
f82d7d16
ML		 1406 unsigned int wid_caps = get_wcaps(codec, nid);
1407 unsigned int wid_type = get_wcaps_type(wid_caps);
1408
1409 if (wid_type != AC_WID_PIN)
1410 continue;
7ef166b8 1411
f82d7d16 1412 if (nid == pin_nid)
7ef166b8
WX		 1413 continue;
1414
f82d7d16 1415 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1416 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1417 if (curr != mux_idx)
1418 continue;
7ef166b8 1419
f82d7d16
ML		 1420 /* choose an unassigned converter. The conveters in the
1421 * connection list are in the same order as in the codec.
1422 */
1423 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1424 per_cvt = get_cvt(spec, cvt_idx);
1425 if (!per_cvt->assigned) {
4e76a883
TI		 1426 codec_dbg(codec,
1427 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1428 cvt_idx, nid);
1429 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1430 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1431 cvt_idx);
1432 break;
1433 }
7ef166b8
WX		 1434 }
1435 }
1436}
1437
1438/*
1439 * HDA PCM callbacks
1440 */
1441static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1442 struct hda_codec *codec,
1443 struct snd_pcm_substream *substream)
1444{
1445 struct hdmi_spec *spec = codec->spec;
1446 struct snd_pcm_runtime *runtime = substream->runtime;
1447 int pin_idx, cvt_idx, mux_idx = 0;
1448 struct hdmi_spec_per_pin *per_pin;
1449 struct hdmi_eld *eld;
1450 struct hdmi_spec_per_cvt *per_cvt = NULL;
1451 int err;
1452
1453 /* Validate hinfo */
4e76a883 1454 pin_idx = hinfo_to_pin_index(codec, hinfo);
7ef166b8
WX		 1455 if (snd_BUG_ON(pin_idx < 0))
1456 return -EINVAL;
1457 per_pin = get_pin(spec, pin_idx);
1458 eld = &per_pin->sink_eld;
1459
1460 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1461 if (err < 0)
1462 return err;
1463
1464 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1465 /* Claim converter */
1466 per_cvt->assigned = 1;
1df5a06a 1467 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1468 hinfo->nid = per_cvt->cvt_nid;
1469
bddee96b 1470 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1471 AC_VERB_SET_CONNECT_SEL,
1472 mux_idx);
7ef166b8
WX		 1473
1474 /* configure unused pins to choose other converters */
ca2e7224 1475 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
300016b9 1476 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1477
384a48d7 1478 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1479
2def8172 1480 /* Initially set the converter's capabilities */
384a48d7
SW		 1481 hinfo->channels_min = per_cvt->channels_min;
1482 hinfo->channels_max = per_cvt->channels_max;
1483 hinfo->rates = per_cvt->rates;
1484 hinfo->formats = per_cvt->formats;
1485 hinfo->maxbps = per_cvt->maxbps;
2def8172 1486
384a48d7 1487 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1488 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1489 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1490 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1491 !hinfo->rates || !hinfo->formats) {
1492 per_cvt->assigned = 0;
1493 hinfo->nid = 0;
1494 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1495 return -ENODEV;
2ad779b7 1496 }
bbbe3390 1497 }
2def8172
SW		 1498
1499 /* Store the updated parameters */
639cef0e
TI		 1500 runtime->hw.channels_min = hinfo->channels_min;
1501 runtime->hw.channels_max = hinfo->channels_max;
1502 runtime->hw.formats = hinfo->formats;
1503 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1504
1505 snd_pcm_hw_constraint_step(substream->runtime, 0,
1506 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1507 return 0;
1508}
1509
079d88cc
WF		 1510/*
1511 * HDA/HDMI auto parsing
1512 */
384a48d7 1513static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1514{
1515 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1516 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1517 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1518
1519 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1520 codec_warn(codec,
1521 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1522 pin_nid, get_wcaps(codec, pin_nid));
1523 return -EINVAL;
1524 }
1525
384a48d7
SW		 1526 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1527 per_pin->mux_nids,
1528 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1529
1530 return 0;
1531}
1532
efe47108 1533static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1534{
464837a7 1535 struct hda_jack_tbl *jack;
744626da 1536 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1537 struct hdmi_spec *spec = codec->spec;
1538 struct hdmi_eld *eld = &spec->temp_eld;
1539 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1540 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1541 /*
1542 * Always execute a GetPinSense verb here, even when called from
1543 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1544 * response's PD bit is not the real PD value, but indicates that
1545 * the real PD value changed. An older version of the HD-audio
1546 * specification worked this way. Hence, we just ignore the data in
1547 * the unsolicited response to avoid custom WARs.
1548 */
da4a7a39 1549 int present;
4bd038f9
DH		 1550 bool update_eld = false;
1551 bool eld_changed = false;
efe47108 1552 bool ret;
079d88cc 1553
664c7155 1554 snd_hda_power_up_pm(codec);
da4a7a39
DH		 1555 present = snd_hda_pin_sense(codec, pin_nid);
1556
a4e9a38b 1557 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1558 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1559 if (pin_eld->monitor_present)
1560 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1561 else
1562 eld->eld_valid = false;
079d88cc 1563
4e76a883 1564 codec_dbg(codec,
384a48d7 1565 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1566 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1567
4bd038f9 1568 if (eld->eld_valid) {
307229d2 1569 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1570 &eld->eld_size) < 0)
4bd038f9 1571 eld->eld_valid = false;
1613d6b4
DH		 1572 else {
1573 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
79514d47 1574 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1575 eld->eld_size) < 0)
4bd038f9 1576 eld->eld_valid = false;
1613d6b4
DH		 1577 }
1578
4bd038f9 1579 if (eld->eld_valid) {
79514d47 1580 snd_hdmi_show_eld(codec, &eld->info);
4bd038f9 1581 update_eld = true;
1613d6b4 1582 }
c6e8453e 1583 else if (repoll) {
2f35c630
TI		 1584 schedule_delayed_work(&per_pin->work,
1585 msecs_to_jiffies(300));
cbbaa603 1586 goto unlock;
744626da
WF		 1587 }
1588 }
4bd038f9 1589
6acce400 1590 if (pin_eld->eld_valid != eld->eld_valid)
92c69e79 1591 eld_changed = true;
6acce400
AH		 1592
1593 if (pin_eld->eld_valid && !eld->eld_valid)
1594 update_eld = true;
1595
4bd038f9 1596 if (update_eld) {
b054087d 1597 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1598 pin_eld->eld_valid = eld->eld_valid;
6acce400 1599 if (pin_eld->eld_size != eld->eld_size ||
92c69e79 1600 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
6acce400 1601 eld->eld_size) != 0) {
4bd038f9
DH		 1602 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1603 eld->eld_size);
6acce400
AH		 1604 eld_changed = true;
1605 }
4bd038f9
DH		 1606 pin_eld->eld_size = eld->eld_size;
1607 pin_eld->info = eld->info;
b054087d 1608
7342017f
AH		 1609 /*
1610 * Re-setup pin and infoframe. This is needed e.g. when
1611 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1612 * - transcoder can change during stream playback on Haswell
b4f75aea 1613 * and this can make HW reset converter selection on a pin.
b054087d 1614 */
b4f75aea 1615 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
ca2e7224
LY		 1616 if (is_haswell_plus(codec) ||
1617 is_valleyview_plus(codec)) {
b4f75aea
ML		 1618 intel_verify_pin_cvt_connect(codec, per_pin);
1619 intel_not_share_assigned_cvt(codec, pin_nid,
1620 per_pin->mux_idx);
1621 }
1622
b054087d
TI		 1623 hdmi_setup_audio_infoframe(codec, per_pin,
1624 per_pin->non_pcm);
b4f75aea 1625 }
4bd038f9 1626 }
92c69e79
DH		 1627
1628 if (eld_changed)
6efdd851 1629 snd_ctl_notify(codec->card,
92c69e79
DH		 1630 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1631 &per_pin->eld_ctl->id);
cbbaa603 1632 unlock:
aff747eb 1633 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1634
1635 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1636 if (jack)
1637 jack->block_report = !ret;
1638
a4e9a38b 1639 mutex_unlock(&per_pin->lock);
664c7155 1640 snd_hda_power_down_pm(codec);
efe47108 1641 return ret;
079d88cc
WF		 1642}
1643
744626da
WF		 1644static void hdmi_repoll_eld(struct work_struct *work)
1645{
1646 struct hdmi_spec_per_pin *per_pin =
1647 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1648
c6e8453e
WF		 1649 if (per_pin->repoll_count++ > 6)
1650 per_pin->repoll_count = 0;
1651
efe47108
TI		 1652 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1653 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1654}
1655
c88d4e84
TI		 1656static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1657 hda_nid_t nid);
1658
079d88cc
WF		 1659static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1660{
1661 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1662 unsigned int caps, config;
1663 int pin_idx;
1664 struct hdmi_spec_per_pin *per_pin;
07acecc1 1665 int err;
079d88cc 1666
efc2f8de 1667 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1668 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1669 return 0;
1670
efc2f8de 1671 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1672 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1673 return 0;
1674
75dcbe4d 1675 if (is_haswell_plus(codec))
c88d4e84
TI		 1676 intel_haswell_fixup_connect_list(codec, pin_nid);
1677
384a48d7 1678 pin_idx = spec->num_pins;
bce0d2a8
TI		 1679 per_pin = snd_array_new(&spec->pins);
1680 if (!per_pin)
1681 return -ENOMEM;
384a48d7
SW		 1682
1683 per_pin->pin_nid = pin_nid;
1a6003b5 1684 per_pin->non_pcm = false;
079d88cc 1685
384a48d7
SW		 1686 err = hdmi_read_pin_conn(codec, pin_idx);
1687 if (err < 0)
1688 return err;
079d88cc 1689
079d88cc
WF		 1690 spec->num_pins++;
1691
384a48d7 1692 return 0;
079d88cc
WF		 1693}
1694
384a48d7 1695static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1696{
1697 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1698 struct hdmi_spec_per_cvt *per_cvt;
1699 unsigned int chans;
1700 int err;
079d88cc 1701
384a48d7
SW		 1702 chans = get_wcaps(codec, cvt_nid);
1703 chans = get_wcaps_channels(chans);
1704
bce0d2a8
TI		 1705 per_cvt = snd_array_new(&spec->cvts);
1706 if (!per_cvt)
1707 return -ENOMEM;
384a48d7
SW		 1708
1709 per_cvt->cvt_nid = cvt_nid;
1710 per_cvt->channels_min = 2;
d45e6889 1711 if (chans <= 16) {
384a48d7 1712 per_cvt->channels_max = chans;
d45e6889
TI		 1713 if (chans > spec->channels_max)
1714 spec->channels_max = chans;
1715 }
384a48d7
SW		 1716
1717 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1718 &per_cvt->rates,
1719 &per_cvt->formats,
1720 &per_cvt->maxbps);
1721 if (err < 0)
1722 return err;
1723
bce0d2a8
TI		 1724 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1725 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1726 spec->num_cvts++;
079d88cc
WF		 1727
1728 return 0;
1729}
1730
1731static int hdmi_parse_codec(struct hda_codec *codec)
1732{
1733 hda_nid_t nid;
1734 int i, nodes;
1735
7639a06c 1736 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1737 if (!nid || nodes < 0) {
4e76a883 1738 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1739 return -EINVAL;
1740 }
1741
1742 for (i = 0; i < nodes; i++, nid++) {
1743 unsigned int caps;
1744 unsigned int type;
1745
efc2f8de 1746 caps = get_wcaps(codec, nid);
079d88cc
WF		 1747 type = get_wcaps_type(caps);
1748
1749 if (!(caps & AC_WCAP_DIGITAL))
1750 continue;
1751
1752 switch (type) {
1753 case AC_WID_AUD_OUT:
384a48d7 1754 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1755 break;
1756 case AC_WID_PIN:
3eaead57 1757 hdmi_add_pin(codec, nid);
079d88cc
WF		 1758 break;
1759 }
1760 }
1761
079d88cc
WF		 1762 return 0;
1763}
1764
84eb01be
TI		 1765/*
1766 */
1a6003b5
TI		 1767static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1768{
1769 struct hda_spdif_out *spdif;
1770 bool non_pcm;
1771
1772 mutex_lock(&codec->spdif_mutex);
1773 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1774 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1775 mutex_unlock(&codec->spdif_mutex);
1776 return non_pcm;
1777}
1778
ddd621fb
LY		 1779/* There is a fixed mapping between audio pin node and display port
1780 * on current Intel platforms:
1781 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
1782 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
1783 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
1784 */
1785static int intel_pin2port(hda_nid_t pin_nid)
1786{
1787 return pin_nid - 4;
1788}
1a6003b5 1789
84eb01be
TI		 1790/*
1791 * HDMI callbacks
1792 */
1793
1794static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1795 struct hda_codec *codec,
1796 unsigned int stream_tag,
1797 unsigned int format,
1798 struct snd_pcm_substream *substream)
1799{
384a48d7
SW		 1800 hda_nid_t cvt_nid = hinfo->nid;
1801 struct hdmi_spec *spec = codec->spec;
4e76a883 1802 int pin_idx = hinfo_to_pin_index(codec, hinfo);
b054087d
TI		 1803 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1804 hda_nid_t pin_nid = per_pin->pin_nid;
ddd621fb
LY		 1805 struct snd_pcm_runtime *runtime = substream->runtime;
1806 struct i915_audio_component *acomp = codec->bus->core.audio_component;
1a6003b5 1807 bool non_pcm;
75fae117 1808 int pinctl;
1a6003b5 1809
ca2e7224 1810 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2df6742f
ML		 1811 /* Verify pin:cvt selections to avoid silent audio after S3.
1812 * After S3, the audio driver restores pin:cvt selections
1813 * but this can happen before gfx is ready and such selection
1814 * is overlooked by HW. Thus multiple pins can share a same
1815 * default convertor and mute control will affect each other,
1816 * which can cause a resumed audio playback become silent
1817 * after S3.
1818 */
1819 intel_verify_pin_cvt_connect(codec, per_pin);
1820 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1821 }
1822
ddd621fb
LY		 1823 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1824 /* Todo: add DP1.2 MST audio support later */
1825 if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
1826 acomp->ops->sync_audio_rate(acomp->dev,
1827 intel_pin2port(pin_nid),
1828 runtime->rate);
1829
1a6003b5 1830 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1831 mutex_lock(&per_pin->lock);
b054087d
TI		 1832 per_pin->channels = substream->runtime->channels;
1833 per_pin->setup = true;
384a48d7 1834
b054087d 1835 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1836 mutex_unlock(&per_pin->lock);
84eb01be 1837
75fae117
SW		 1838 if (spec->dyn_pin_out) {
1839 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1840 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1841 snd_hda_codec_write(codec, pin_nid, 0,
1842 AC_VERB_SET_PIN_WIDGET_CONTROL,
1843 pinctl | PIN_OUT);
1844 }
1845
307229d2 1846 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1847}
1848
8dfaa573
TI		 1849static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1850 struct hda_codec *codec,
1851 struct snd_pcm_substream *substream)
1852{
1853 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1854 return 0;
1855}
1856
f2ad24fa
TI		 1857static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1858 struct hda_codec *codec,
1859 struct snd_pcm_substream *substream)
384a48d7
SW		 1860{
1861 struct hdmi_spec *spec = codec->spec;
1862 int cvt_idx, pin_idx;
1863 struct hdmi_spec_per_cvt *per_cvt;
1864 struct hdmi_spec_per_pin *per_pin;
75fae117 1865 int pinctl;
384a48d7 1866
384a48d7 1867 if (hinfo->nid) {
4e76a883 1868 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1869 if (snd_BUG_ON(cvt_idx < 0))
1870 return -EINVAL;
bce0d2a8 1871 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1872
1873 snd_BUG_ON(!per_cvt->assigned);
1874 per_cvt->assigned = 0;
1875 hinfo->nid = 0;
1876
4e76a883 1877 pin_idx = hinfo_to_pin_index(codec, hinfo);
384a48d7
SW		 1878 if (snd_BUG_ON(pin_idx < 0))
1879 return -EINVAL;
bce0d2a8 1880 per_pin = get_pin(spec, pin_idx);
384a48d7 1881
75fae117
SW		 1882 if (spec->dyn_pin_out) {
1883 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1884 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1885 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1886 AC_VERB_SET_PIN_WIDGET_CONTROL,
1887 pinctl & ~PIN_OUT);
1888 }
1889
384a48d7 1890 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1891
a4e9a38b 1892 mutex_lock(&per_pin->lock);
d45e6889
TI		 1893 per_pin->chmap_set = false;
1894 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1895
1896 per_pin->setup = false;
1897 per_pin->channels = 0;
a4e9a38b 1898 mutex_unlock(&per_pin->lock);
384a48d7 1899 }
d45e6889 1900
384a48d7
SW		 1901 return 0;
1902}
1903
1904static const struct hda_pcm_ops generic_ops = {
1905 .open = hdmi_pcm_open,
f2ad24fa 1906 .close = hdmi_pcm_close,
384a48d7 1907 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1908 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1909};
1910
d45e6889
TI		 1911/*
1912 * ALSA API channel-map control callbacks
1913 */
1914static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1915 struct snd_ctl_elem_info *uinfo)
1916{
1917 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1918 struct hda_codec *codec = info->private_data;
1919 struct hdmi_spec *spec = codec->spec;
1920 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1921 uinfo->count = spec->channels_max;
1922 uinfo->value.integer.min = 0;
1923 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1924 return 0;
1925}
1926
307229d2
AH		 1927static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1928 int channels)
1929{
1930 /* If the speaker allocation matches the channel count, it is OK.*/
1931 if (cap->channels != channels)
1932 return -1;
1933
1934 /* all channels are remappable freely */
1935 return SNDRV_CTL_TLVT_CHMAP_VAR;
1936}
1937
1938static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1939 unsigned int *chmap, int channels)
1940{
1941 int count = 0;
1942 int c;
1943
1944 for (c = 7; c >= 0; c--) {
1945 int spk = cap->speakers[c];
1946 if (!spk)
1947 continue;
1948
1949 chmap[count++] = spk_to_chmap(spk);
1950 }
1951
1952 WARN_ON(count != channels);
1953}
1954
d45e6889
TI		 1955static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1956 unsigned int size, unsigned int __user *tlv)
1957{
1958 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1959 struct hda_codec *codec = info->private_data;
1960 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1961 unsigned int __user *dst;
1962 int chs, count = 0;
1963
1964 if (size < 8)
1965 return -ENOMEM;
1966 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1967 return -EFAULT;
1968 size -= 8;
1969 dst = tlv + 2;
498dab3a 1970 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1971 int i;
d45e6889
TI		 1972 struct cea_channel_speaker_allocation *cap;
1973 cap = channel_allocations;
1974 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1975 int chs_bytes = chs * 4;
307229d2
AH		 1976 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1977 unsigned int tlv_chmap[8];
1978
1979 if (type < 0)
d45e6889 1980 continue;
d45e6889
TI		 1981 if (size < 8)
1982 return -ENOMEM;
307229d2 1983 if (put_user(type, dst) ||
d45e6889
TI		 1984 put_user(chs_bytes, dst + 1))
1985 return -EFAULT;
1986 dst += 2;
1987 size -= 8;
1988 count += 8;
1989 if (size < chs_bytes)
1990 return -ENOMEM;
1991 size -= chs_bytes;
1992 count += chs_bytes;
307229d2
AH		 1993 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1994 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1995 return -EFAULT;
1996 dst += chs;
d45e6889
TI		 1997 }
1998 }
1999 if (put_user(count, tlv + 1))
2000 return -EFAULT;
2001 return 0;
2002}
2003
2004static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2005 struct snd_ctl_elem_value *ucontrol)
2006{
2007 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2008 struct hda_codec *codec = info->private_data;
2009 struct hdmi_spec *spec = codec->spec;
2010 int pin_idx = kcontrol->private_value;
bce0d2a8 2011 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 2012 int i;
2013
2014 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2015 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2016 return 0;
2017}
2018
2019static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2020 struct snd_ctl_elem_value *ucontrol)
2021{
2022 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2023 struct hda_codec *codec = info->private_data;
2024 struct hdmi_spec *spec = codec->spec;
2025 int pin_idx = kcontrol->private_value;
bce0d2a8 2026 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 2027 unsigned int ctl_idx;
2028 struct snd_pcm_substream *substream;
2029 unsigned char chmap[8];
307229d2 2030 int i, err, ca, prepared = 0;
d45e6889
TI		 2031
2032 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2033 substream = snd_pcm_chmap_substream(info, ctl_idx);
2034 if (!substream || !substream->runtime)
6f54c361 2035 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 2036 switch (substream->runtime->status->state) {
2037 case SNDRV_PCM_STATE_OPEN:
2038 case SNDRV_PCM_STATE_SETUP:
2039 break;
2040 case SNDRV_PCM_STATE_PREPARED:
2041 prepared = 1;
2042 break;
2043 default:
2044 return -EBUSY;
2045 }
2046 memset(chmap, 0, sizeof(chmap));
2047 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2048 chmap[i] = ucontrol->value.integer.value[i];
2049 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2050 return 0;
2051 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2052 if (ca < 0)
2053 return -EINVAL;
307229d2
AH		 2054 if (spec->ops.chmap_validate) {
2055 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2056 if (err)
2057 return err;
2058 }
a4e9a38b 2059 mutex_lock(&per_pin->lock);
d45e6889
TI		 2060 per_pin->chmap_set = true;
2061 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2062 if (prepared)
b054087d 2063 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 2064 mutex_unlock(&per_pin->lock);
d45e6889
TI		 2065
2066 return 0;
2067}
2068
84eb01be
TI		 2069static int generic_hdmi_build_pcms(struct hda_codec *codec)
2070{
2071 struct hdmi_spec *spec = codec->spec;
384a48d7 2072 int pin_idx;
84eb01be 2073
384a48d7
SW		 2074 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2075 struct hda_pcm *info;
84eb01be 2076 struct hda_pcm_stream *pstr;
bce0d2a8 2077
bbbc7e85 2078 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
bce0d2a8
TI		 2079 if (!info)
2080 return -ENOMEM;
bbbc7e85 2081 spec->pcm_rec[pin_idx] = info;
84eb01be 2082 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2083 info->own_chmap = true;
384a48d7 2084
84eb01be 2085 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2086 pstr->substreams = 1;
2087 pstr->ops = generic_ops;
2088 /* other pstr fields are set in open */
84eb01be
TI		 2089 }
2090
2091 return 0;
2092}
2093
0b6c49b5
DH		 2094static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2095{
31ef2257 2096 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2097 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2098 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2099 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
909cadc6 2100 bool phantom_jack;
0b6c49b5 2101
31ef2257
TI		 2102 if (pcmdev > 0)
2103 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
909cadc6
TI		 2104 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2105 if (phantom_jack)
30efd8de
DH		 2106 strncat(hdmi_str, " Phantom",
2107 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 2108
909cadc6
TI		 2109 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2110 phantom_jack);
0b6c49b5
DH		 2111}
2112
84eb01be
TI		 2113static int generic_hdmi_build_controls(struct hda_codec *codec)
2114{
2115 struct hdmi_spec *spec = codec->spec;
2116 int err;
384a48d7 2117 int pin_idx;
84eb01be 2118
384a48d7 2119 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2120 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2121
2122 err = generic_hdmi_build_jack(codec, pin_idx);
2123 if (err < 0)
2124 return err;
2125
dcda5806
TI		 2126 err = snd_hda_create_dig_out_ctls(codec,
2127 per_pin->pin_nid,
2128 per_pin->mux_nids[0],
2129 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2130 if (err < 0)
2131 return err;
384a48d7 2132 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2133
2134 /* add control for ELD Bytes */
bce0d2a8
TI		 2135 err = hdmi_create_eld_ctl(codec, pin_idx,
2136 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2137
2138 if (err < 0)
2139 return err;
31ef2257 2140
82b1d73f 2141 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2142 }
2143
d45e6889
TI		 2144 /* add channel maps */
2145 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bbbc7e85 2146 struct hda_pcm *pcm;
d45e6889
TI		 2147 struct snd_pcm_chmap *chmap;
2148 struct snd_kcontrol *kctl;
2149 int i;
2ca320e2 2150
bbbc7e85
TI		 2151 pcm = spec->pcm_rec[pin_idx];
2152 if (!pcm || !pcm->pcm)
2ca320e2 2153 break;
bbbc7e85 2154 err = snd_pcm_add_chmap_ctls(pcm->pcm,
d45e6889
TI		 2155 SNDRV_PCM_STREAM_PLAYBACK,
2156 NULL, 0, pin_idx, &chmap);
2157 if (err < 0)
2158 return err;
2159 /* override handlers */
2160 chmap->private_data = codec;
2161 kctl = chmap->kctl;
2162 for (i = 0; i < kctl->count; i++)
2163 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2164 kctl->info = hdmi_chmap_ctl_info;
2165 kctl->get = hdmi_chmap_ctl_get;
2166 kctl->put = hdmi_chmap_ctl_put;
2167 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2168 }
2169
84eb01be
TI		 2170 return 0;
2171}
2172
8b8d654b 2173static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2174{
2175 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2176 int pin_idx;
2177
2178 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2179 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2180
744626da 2181 per_pin->codec = codec;
a4e9a38b 2182 mutex_init(&per_pin->lock);
744626da 2183 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2184 eld_proc_new(per_pin, pin_idx);
84eb01be 2185 }
8b8d654b
TI		 2186 return 0;
2187}
2188
2189static int generic_hdmi_init(struct hda_codec *codec)
2190{
2191 struct hdmi_spec *spec = codec->spec;
2192 int pin_idx;
2193
2194 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2195 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2196 hda_nid_t pin_nid = per_pin->pin_nid;
2197
2198 hdmi_init_pin(codec, pin_nid);
62f949bf 2199 snd_hda_jack_detect_enable_callback(codec, pin_nid,
20ce9029 2200 codec->jackpoll_interval > 0 ? jack_callback : NULL);
8b8d654b 2201 }
84eb01be
TI		 2202 return 0;
2203}
2204
bce0d2a8
TI		 2205static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2206{
2207 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2208 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2209}
2210
2211static void hdmi_array_free(struct hdmi_spec *spec)
2212{
2213 snd_array_free(&spec->pins);
2214 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2215}
2216
84eb01be
TI		 2217static void generic_hdmi_free(struct hda_codec *codec)
2218{
2219 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2220 int pin_idx;
2221
25adc137
DH		 2222 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2223 snd_hdac_i915_register_notifier(NULL);
2224
384a48d7 2225 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2226 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2227
2f35c630 2228 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2229 eld_proc_free(per_pin);
384a48d7 2230 }
84eb01be 2231
bce0d2a8 2232 hdmi_array_free(spec);
84eb01be
TI		 2233 kfree(spec);
2234}
2235
28cb72e5
WX		 2236#ifdef CONFIG_PM
2237static int generic_hdmi_resume(struct hda_codec *codec)
2238{
2239 struct hdmi_spec *spec = codec->spec;
2240 int pin_idx;
2241
a2833683 2242 codec->patch_ops.init(codec);
eeecd9d1 2243 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2244
2245 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2246 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2247 hdmi_present_sense(per_pin, 1);
2248 }
2249 return 0;
2250}
2251#endif
2252
fb79e1e0 2253static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2254 .init = generic_hdmi_init,
2255 .free = generic_hdmi_free,
2256 .build_pcms = generic_hdmi_build_pcms,
2257 .build_controls = generic_hdmi_build_controls,
2258 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2259#ifdef CONFIG_PM
2260 .resume = generic_hdmi_resume,
2261#endif
84eb01be
TI		 2262};
2263
307229d2
AH		 2264static const struct hdmi_ops generic_standard_hdmi_ops = {
2265 .pin_get_eld = snd_hdmi_get_eld,
2266 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2267 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2268 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2269 .pin_hbr_setup = hdmi_pin_hbr_setup,
2270 .setup_stream = hdmi_setup_stream,
2271 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2272 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2273};
2274
6ffe168f 2275
c88d4e84
TI		 2276static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2277 hda_nid_t nid)
2278{
2279 struct hdmi_spec *spec = codec->spec;
2280 hda_nid_t conns[4];
2281 int nconns;
6ffe168f 2282
c88d4e84
TI		 2283 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2284 if (nconns == spec->num_cvts &&
2285 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2286 return;
2287
c88d4e84 2288 /* override pins connection list */
4e76a883 2289 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2290 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2291}
2292
1611a9c9
ML		 2293#define INTEL_VENDOR_NID 0x08
2294#define INTEL_GET_VENDOR_VERB 0xf81
2295#define INTEL_SET_VENDOR_VERB 0x781
2296#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2297#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2298
2299static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2300 bool update_tree)
1611a9c9
ML		 2301{
2302 unsigned int vendor_param;
2303
1611a9c9
ML		 2304 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2305 INTEL_GET_VENDOR_VERB, 0);
2306 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2307 return;
2308
2309 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2310 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2311 INTEL_SET_VENDOR_VERB, vendor_param);
2312 if (vendor_param == -1)
2313 return;
2314
17df3f55
TI		 2315 if (update_tree)
2316 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2317}
2318
c88d4e84
TI		 2319static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2320{
2321 unsigned int vendor_param;
2322
2323 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2324 INTEL_GET_VENDOR_VERB, 0);
2325 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2326 return;
2327
2328 /* enable DP1.2 mode */
2329 vendor_param |= INTEL_EN_DP12;
a551d914 2330 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
c88d4e84
TI		 2331 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2332 INTEL_SET_VENDOR_VERB, vendor_param);
2333}
2334
17df3f55
TI		 2335/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2336 * Otherwise you may get severe h/w communication errors.
2337 */
2338static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2339 unsigned int power_state)
2340{
2341 if (power_state == AC_PWRST_D0) {
2342 intel_haswell_enable_all_pins(codec, false);
2343 intel_haswell_fixup_enable_dp12(codec);
2344 }
c88d4e84 2345
17df3f55
TI		 2346 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2347 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2348}
6ffe168f 2349
f0675d4a 2350static void intel_pin_eld_notify(void *audio_ptr, int port)
25adc137
DH		 2351{
2352 struct hda_codec *codec = audio_ptr;
2353 int pin_nid = port + 0x04;
2354
8ae743e8
TI		 2355 /* skip notification during system suspend (but not in runtime PM);
2356 * the state will be updated at resume
2357 */
2358 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2359 return;
2360
25adc137
DH		 2361 check_presence_and_report(codec, pin_nid);
2362}
2363
84eb01be
TI		 2364static int patch_generic_hdmi(struct hda_codec *codec)
2365{
2366 struct hdmi_spec *spec;
84eb01be
TI		 2367
2368 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2369 if (spec == NULL)
2370 return -ENOMEM;
2371
307229d2 2372 spec->ops = generic_standard_hdmi_ops;
84eb01be 2373 codec->spec = spec;
bce0d2a8 2374 hdmi_array_init(spec, 4);
6ffe168f 2375
75dcbe4d 2376 if (is_haswell_plus(codec)) {
17df3f55 2377 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2378 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2379 }
6ffe168f 2380
2bd1f73f
ML		 2381 /* For Valleyview/Cherryview, only the display codec is in the display
2382 * power well and can use link_power ops to request/release the power.
2383 * For Haswell/Broadwell, the controller is also in the power well and
2384 * can cover the codec power request, and so need not set this flag.
2385 * For previous platforms, there is no such power well feature.
2386 */
ff9d8859
LH		 2387 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2388 is_broxton(codec))
2bd1f73f
ML		 2389 codec->core.link_power_control = 1;
2390
25adc137 2391 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
5b8620bb 2392 codec->depop_delay = 0;
25adc137
DH		 2393 spec->i915_audio_ops.audio_ptr = codec;
2394 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2395 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2396 }
5b8620bb 2397
84eb01be
TI		 2398 if (hdmi_parse_codec(codec) < 0) {
2399 codec->spec = NULL;
2400 kfree(spec);
2401 return -EINVAL;
2402 }
2403 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2404 if (is_haswell_plus(codec)) {
17df3f55 2405 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2406 codec->dp_mst = true;
2407 }
17df3f55 2408
2377c3c3
LH		 2409 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2410 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2411 codec->auto_runtime_pm = 1;
2412
8b8d654b 2413 generic_hdmi_init_per_pins(codec);
84eb01be 2414
84eb01be
TI		 2415 init_channel_allocations();
2416
2417 return 0;
2418}
2419
3aaf8980
SW		 2420/*
2421 * Shared non-generic implementations
2422 */
2423
2424static int simple_playback_build_pcms(struct hda_codec *codec)
2425{
2426 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2427 struct hda_pcm *info;
8ceb332d
TI		 2428 unsigned int chans;
2429 struct hda_pcm_stream *pstr;
bce0d2a8 2430 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2431
bce0d2a8
TI		 2432 per_cvt = get_cvt(spec, 0);
2433 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2434 chans = get_wcaps_channels(chans);
3aaf8980 2435
bbbc7e85 2436 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2437 if (!info)
2438 return -ENOMEM;
bbbc7e85 2439 spec->pcm_rec[0] = info;
8ceb332d
TI		 2440 info->pcm_type = HDA_PCM_TYPE_HDMI;
2441 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2442 *pstr = spec->pcm_playback;
bce0d2a8 2443 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2444 if (pstr->channels_max <= 2 && chans && chans <= 16)
2445 pstr->channels_max = chans;
3aaf8980
SW		 2446
2447 return 0;
2448}
2449
4b6ace9e
TI		 2450/* unsolicited event for jack sensing */
2451static void simple_hdmi_unsol_event(struct hda_codec *codec,
2452 unsigned int res)
2453{
9dd8cf12 2454 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2455 snd_hda_jack_report_sync(codec);
2456}
2457
2458/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2459 * as long as spec->pins[] is set correctly
2460 */
2461#define simple_hdmi_build_jack generic_hdmi_build_jack
2462
3aaf8980
SW		 2463static int simple_playback_build_controls(struct hda_codec *codec)
2464{
2465 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2466 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2467 int err;
3aaf8980 2468
bce0d2a8 2469 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2470 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2471 per_cvt->cvt_nid,
2472 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2473 if (err < 0)
2474 return err;
2475 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2476}
2477
4f0110ce
TI		 2478static int simple_playback_init(struct hda_codec *codec)
2479{
2480 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2481 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2482 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2483
2484 snd_hda_codec_write(codec, pin, 0,
2485 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2486 /* some codecs require to unmute the pin */
2487 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2488 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2489 AMP_OUT_UNMUTE);
62f949bf 2490 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2491 return 0;
2492}
2493
3aaf8980
SW		 2494static void simple_playback_free(struct hda_codec *codec)
2495{
2496 struct hdmi_spec *spec = codec->spec;
2497
bce0d2a8 2498 hdmi_array_free(spec);
3aaf8980
SW		 2499 kfree(spec);
2500}
2501
84eb01be
TI		 2502/*
2503 * Nvidia specific implementations
2504 */
2505
2506#define Nv_VERB_SET_Channel_Allocation 0xF79
2507#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2508#define Nv_VERB_SET_Audio_Protection_On 0xF98
2509#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2510
2511#define nvhdmi_master_con_nid_7x 0x04
2512#define nvhdmi_master_pin_nid_7x 0x05
2513
fb79e1e0 2514static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2515 /*front, rear, clfe, rear_surr */
2516 0x6, 0x8, 0xa, 0xc,
2517};
2518
ceaa86ba
TI		 2519static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2520 /* set audio protect on */
2521 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2522 /* enable digital output on pin widget */
2523 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2524 {} /* terminator */
2525};
2526
2527static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2528 /* set audio protect on */
2529 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2530 /* enable digital output on pin widget */
2531 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2532 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2533 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2534 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2535 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2536 {} /* terminator */
2537};
2538
2539#ifdef LIMITED_RATE_FMT_SUPPORT
2540/* support only the safe format and rate */
2541#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2542#define SUPPORTED_MAXBPS 16
2543#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2544#else
2545/* support all rates and formats */
2546#define SUPPORTED_RATES \
2547 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2548 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2549 SNDRV_PCM_RATE_192000)
2550#define SUPPORTED_MAXBPS 24
2551#define SUPPORTED_FORMATS \
2552 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2553#endif
2554
ceaa86ba
TI		 2555static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2556{
2557 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2558 return 0;
2559}
2560
2561static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2562{
ceaa86ba 2563 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2564 return 0;
2565}
2566
393004b2
ND		 2567static unsigned int channels_2_6_8[] = {
2568 2, 6, 8
2569};
2570
2571static unsigned int channels_2_8[] = {
2572 2, 8
2573};
2574
2575static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2576 .count = ARRAY_SIZE(channels_2_6_8),
2577 .list = channels_2_6_8,
2578 .mask = 0,
2579};
2580
2581static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2582 .count = ARRAY_SIZE(channels_2_8),
2583 .list = channels_2_8,
2584 .mask = 0,
2585};
2586
84eb01be
TI		 2587static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2588 struct hda_codec *codec,
2589 struct snd_pcm_substream *substream)
2590{
2591 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2592 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2593
b9a94a9c 2594 switch (codec->preset->vendor_id) {
393004b2
ND		 2595 case 0x10de0002:
2596 case 0x10de0003:
2597 case 0x10de0005:
2598 case 0x10de0006:
2599 hw_constraints_channels = &hw_constraints_2_8_channels;
2600 break;
2601 case 0x10de0007:
2602 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2603 break;
2604 default:
2605 break;
2606 }
2607
2608 if (hw_constraints_channels != NULL) {
2609 snd_pcm_hw_constraint_list(substream->runtime, 0,
2610 SNDRV_PCM_HW_PARAM_CHANNELS,
2611 hw_constraints_channels);
ad09fc9d
TI		 2612 } else {
2613 snd_pcm_hw_constraint_step(substream->runtime, 0,
2614 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2615 }
2616
84eb01be
TI		 2617 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2618}
2619
2620static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2621 struct hda_codec *codec,
2622 struct snd_pcm_substream *substream)
2623{
2624 struct hdmi_spec *spec = codec->spec;
2625 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2626}
2627
2628static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2629 struct hda_codec *codec,
2630 unsigned int stream_tag,
2631 unsigned int format,
2632 struct snd_pcm_substream *substream)
2633{
2634 struct hdmi_spec *spec = codec->spec;
2635 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2636 stream_tag, format, substream);
2637}
2638
d0b1252d
TI		 2639static const struct hda_pcm_stream simple_pcm_playback = {
2640 .substreams = 1,
2641 .channels_min = 2,
2642 .channels_max = 2,
2643 .ops = {
2644 .open = simple_playback_pcm_open,
2645 .close = simple_playback_pcm_close,
2646 .prepare = simple_playback_pcm_prepare
2647 },
2648};
2649
2650static const struct hda_codec_ops simple_hdmi_patch_ops = {
2651 .build_controls = simple_playback_build_controls,
2652 .build_pcms = simple_playback_build_pcms,
2653 .init = simple_playback_init,
2654 .free = simple_playback_free,
250e41ac 2655 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2656};
2657
2658static int patch_simple_hdmi(struct hda_codec *codec,
2659 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2660{
2661 struct hdmi_spec *spec;
bce0d2a8
TI		 2662 struct hdmi_spec_per_cvt *per_cvt;
2663 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2664
2665 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2666 if (!spec)
2667 return -ENOMEM;
2668
2669 codec->spec = spec;
bce0d2a8 2670 hdmi_array_init(spec, 1);
d0b1252d
TI		 2671
2672 spec->multiout.num_dacs = 0; /* no analog */
2673 spec->multiout.max_channels = 2;
2674 spec->multiout.dig_out_nid = cvt_nid;
2675 spec->num_cvts = 1;
2676 spec->num_pins = 1;
bce0d2a8
TI		 2677 per_pin = snd_array_new(&spec->pins);
2678 per_cvt = snd_array_new(&spec->cvts);
2679 if (!per_pin || !per_cvt) {
2680 simple_playback_free(codec);
2681 return -ENOMEM;
2682 }
2683 per_cvt->cvt_nid = cvt_nid;
2684 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2685 spec->pcm_playback = simple_pcm_playback;
2686
2687 codec->patch_ops = simple_hdmi_patch_ops;
2688
2689 return 0;
2690}
2691
1f348522
AP		 2692static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2693 int channels)
2694{
2695 unsigned int chanmask;
2696 int chan = channels ? (channels - 1) : 1;
2697
2698 switch (channels) {
2699 default:
2700 case 0:
2701 case 2:
2702 chanmask = 0x00;
2703 break;
2704 case 4:
2705 chanmask = 0x08;
2706 break;
2707 case 6:
2708 chanmask = 0x0b;
2709 break;
2710 case 8:
2711 chanmask = 0x13;
2712 break;
2713 }
2714
2715 /* Set the audio infoframe channel allocation and checksum fields. The
2716 * channel count is computed implicitly by the hardware. */
2717 snd_hda_codec_write(codec, 0x1, 0,
2718 Nv_VERB_SET_Channel_Allocation, chanmask);
2719
2720 snd_hda_codec_write(codec, 0x1, 0,
2721 Nv_VERB_SET_Info_Frame_Checksum,
2722 (0x71 - chan - chanmask));
2723}
2724
84eb01be
TI		 2725static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2726 struct hda_codec *codec,
2727 struct snd_pcm_substream *substream)
2728{
2729 struct hdmi_spec *spec = codec->spec;
2730 int i;
2731
2732 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2733 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2734 for (i = 0; i < 4; i++) {
2735 /* set the stream id */
2736 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2737 AC_VERB_SET_CHANNEL_STREAMID, 0);
2738 /* set the stream format */
2739 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2740 AC_VERB_SET_STREAM_FORMAT, 0);
2741 }
2742
1f348522
AP		 2743 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2744 * streams are disabled. */
2745 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2746
84eb01be
TI		 2747 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2748}
2749
2750static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2751 struct hda_codec *codec,
2752 unsigned int stream_tag,
2753 unsigned int format,
2754 struct snd_pcm_substream *substream)
2755{
2756 int chs;
112daa7a 2757 unsigned int dataDCC2, channel_id;
84eb01be 2758 int i;
7c935976 2759 struct hdmi_spec *spec = codec->spec;
e3245cdd 2760 struct hda_spdif_out *spdif;
bce0d2a8 2761 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2762
2763 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2764 per_cvt = get_cvt(spec, 0);
2765 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2766
2767 chs = substream->runtime->channels;
84eb01be 2768
84eb01be
TI		 2769 dataDCC2 = 0x2;
2770
84eb01be 2771 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2772 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2773 snd_hda_codec_write(codec,
2774 nvhdmi_master_con_nid_7x,
2775 0,
2776 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2777 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2778
2779 /* set the stream id */
2780 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2781 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2782
2783 /* set the stream format */
2784 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2785 AC_VERB_SET_STREAM_FORMAT, format);
2786
2787 /* turn on again (if needed) */
2788 /* enable and set the channel status audio/data flag */
7c935976 2789 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2790 snd_hda_codec_write(codec,
2791 nvhdmi_master_con_nid_7x,
2792 0,
2793 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2794 spdif->ctls & 0xff);
84eb01be
TI		 2795 snd_hda_codec_write(codec,
2796 nvhdmi_master_con_nid_7x,
2797 0,
2798 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2799 }
2800
2801 for (i = 0; i < 4; i++) {
2802 if (chs == 2)
2803 channel_id = 0;
2804 else
2805 channel_id = i * 2;
2806
2807 /* turn off SPDIF once;
2808 *otherwise the IEC958 bits won't be updated
2809 */
2810 if (codec->spdif_status_reset &&
7c935976 2811 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2812 snd_hda_codec_write(codec,
2813 nvhdmi_con_nids_7x[i],
2814 0,
2815 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2816 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2817 /* set the stream id */
2818 snd_hda_codec_write(codec,
2819 nvhdmi_con_nids_7x[i],
2820 0,
2821 AC_VERB_SET_CHANNEL_STREAMID,
2822 (stream_tag << 4) | channel_id);
2823 /* set the stream format */
2824 snd_hda_codec_write(codec,
2825 nvhdmi_con_nids_7x[i],
2826 0,
2827 AC_VERB_SET_STREAM_FORMAT,
2828 format);
2829 /* turn on again (if needed) */
2830 /* enable and set the channel status audio/data flag */
2831 if (codec->spdif_status_reset &&
7c935976 2832 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2833 snd_hda_codec_write(codec,
2834 nvhdmi_con_nids_7x[i],
2835 0,
2836 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2837 spdif->ctls & 0xff);
84eb01be
TI		 2838 snd_hda_codec_write(codec,
2839 nvhdmi_con_nids_7x[i],
2840 0,
2841 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2842 }
2843 }
2844
1f348522 2845 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2846
2847 mutex_unlock(&codec->spdif_mutex);
2848 return 0;
2849}
2850
fb79e1e0 2851static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2852 .substreams = 1,
2853 .channels_min = 2,
2854 .channels_max = 8,
2855 .nid = nvhdmi_master_con_nid_7x,
2856 .rates = SUPPORTED_RATES,
2857 .maxbps = SUPPORTED_MAXBPS,
2858 .formats = SUPPORTED_FORMATS,
2859 .ops = {
2860 .open = simple_playback_pcm_open,
2861 .close = nvhdmi_8ch_7x_pcm_close,
2862 .prepare = nvhdmi_8ch_7x_pcm_prepare
2863 },
2864};
2865
84eb01be
TI		 2866static int patch_nvhdmi_2ch(struct hda_codec *codec)
2867{
2868 struct hdmi_spec *spec;
d0b1252d
TI		 2869 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2870 nvhdmi_master_pin_nid_7x);
2871 if (err < 0)
2872 return err;
84eb01be 2873
ceaa86ba 2874 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2875 /* override the PCM rates, etc, as the codec doesn't give full list */
2876 spec = codec->spec;
2877 spec->pcm_playback.rates = SUPPORTED_RATES;
2878 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2879 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2880 return 0;
2881}
2882
53775b0d
TI		 2883static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2884{
2885 struct hdmi_spec *spec = codec->spec;
2886 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2887 if (!err) {
2888 struct hda_pcm *info = get_pcm_rec(spec, 0);
2889 info->own_chmap = true;
2890 }
53775b0d
TI		 2891 return err;
2892}
2893
2894static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2895{
2896 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2897 struct hda_pcm *info;
53775b0d
TI		 2898 struct snd_pcm_chmap *chmap;
2899 int err;
2900
2901 err = simple_playback_build_controls(codec);
2902 if (err < 0)
2903 return err;
2904
2905 /* add channel maps */
bce0d2a8
TI		 2906 info = get_pcm_rec(spec, 0);
2907 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2908 SNDRV_PCM_STREAM_PLAYBACK,
2909 snd_pcm_alt_chmaps, 8, 0, &chmap);
2910 if (err < 0)
2911 return err;
b9a94a9c 2912 switch (codec->preset->vendor_id) {
53775b0d
TI		 2913 case 0x10de0002:
2914 case 0x10de0003:
2915 case 0x10de0005:
2916 case 0x10de0006:
2917 chmap->channel_mask = (1U << 2) | (1U << 8);
2918 break;
2919 case 0x10de0007:
2920 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2921 }
2922 return 0;
2923}
2924
84eb01be
TI		 2925static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2926{
2927 struct hdmi_spec *spec;
2928 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2929 if (err < 0)
2930 return err;
2931 spec = codec->spec;
2932 spec->multiout.max_channels = 8;
d0b1252d 2933 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2934 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2935 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2936 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2937
2938 /* Initialize the audio infoframe channel mask and checksum to something
2939 * valid */
2940 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2941
84eb01be
TI		 2942 return 0;
2943}
2944
611885bc
AH		 2945/*
2946 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2947 * - 0x10de0015
2948 * - 0x10de0040
2949 */
2950static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2951 int channels)
2952{
2953 if (cap->ca_index == 0x00 && channels == 2)
2954 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2955
2956 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2957}
2958
2959static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2960{
2961 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2962 return -EINVAL;
2963
2964 return 0;
2965}
2966
2967static int patch_nvhdmi(struct hda_codec *codec)
2968{
2969 struct hdmi_spec *spec;
2970 int err;
2971
2972 err = patch_generic_hdmi(codec);
2973 if (err)
2974 return err;
2975
2976 spec = codec->spec;
75fae117 2977 spec->dyn_pin_out = true;
611885bc
AH		 2978
2979 spec->ops.chmap_cea_alloc_validate_get_type =
2980 nvhdmi_chmap_cea_alloc_validate_get_type;
2981 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2982
2983 return 0;
2984}
2985
26e9a960
TR		 2986/*
2987 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2988 * accessed using vendor-defined verbs. These registers can be used for
2989 * interoperability between the HDA and HDMI drivers.
2990 */
2991
2992/* Audio Function Group node */
2993#define NVIDIA_AFG_NID 0x01
2994
2995/*
2996 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2997 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2998 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2999 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3000 * additional bit (at position 30) to signal the validity of the format.
3001 *
3002 * | 31 | 30 | 29 16 | 15 0 |
3003 * +---------+-------+--------+--------+
3004 * | TRIGGER | VALID | UNUSED | FORMAT |
3005 * +-----------------------------------|
3006 *
3007 * Note that for the trigger bit to take effect it needs to change value
3008 * (i.e. it needs to be toggled).
3009 */
3010#define NVIDIA_GET_SCRATCH0 0xfa6
3011#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3012#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3013#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3014#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3015#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3016#define NVIDIA_SCRATCH_VALID (1 << 6)
3017
3018#define NVIDIA_GET_SCRATCH1 0xfab
3019#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3020#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3021#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3022#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3023
3024/*
3025 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3026 * the format is invalidated so that the HDMI codec can be disabled.
3027 */
3028static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3029{
3030 unsigned int value;
3031
3032 /* bits [31:30] contain the trigger and valid bits */
3033 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3034 NVIDIA_GET_SCRATCH0, 0);
3035 value = (value >> 24) & 0xff;
3036
3037 /* bits [15:0] are used to store the HDA format */
3038 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3039 NVIDIA_SET_SCRATCH0_BYTE0,
3040 (format >> 0) & 0xff);
3041 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3042 NVIDIA_SET_SCRATCH0_BYTE1,
3043 (format >> 8) & 0xff);
3044
3045 /* bits [16:24] are unused */
3046 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3047 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3048
3049 /*
3050 * Bit 30 signals that the data is valid and hence that HDMI audio can
3051 * be enabled.
3052 */
3053 if (format == 0)
3054 value &= ~NVIDIA_SCRATCH_VALID;
3055 else
3056 value |= NVIDIA_SCRATCH_VALID;
3057
3058 /*
3059 * Whenever the trigger bit is toggled, an interrupt is raised in the
3060 * HDMI codec. The HDMI driver will use that as trigger to update its
3061 * configuration.
3062 */
3063 value ^= NVIDIA_SCRATCH_TRIGGER;
3064
3065 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3066 NVIDIA_SET_SCRATCH0_BYTE3, value);
3067}
3068
3069static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3070 struct hda_codec *codec,
3071 unsigned int stream_tag,
3072 unsigned int format,
3073 struct snd_pcm_substream *substream)
3074{
3075 int err;
3076
3077 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3078 format, substream);
3079 if (err < 0)
3080 return err;
3081
3082 /* notify the HDMI codec of the format change */
3083 tegra_hdmi_set_format(codec, format);
3084
3085 return 0;
3086}
3087
3088static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3089 struct hda_codec *codec,
3090 struct snd_pcm_substream *substream)
3091{
3092 /* invalidate the format in the HDMI codec */
3093 tegra_hdmi_set_format(codec, 0);
3094
3095 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3096}
3097
3098static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3099{
3100 struct hdmi_spec *spec = codec->spec;
3101 unsigned int i;
3102
3103 for (i = 0; i < spec->num_pins; i++) {
3104 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3105
3106 if (pcm->pcm_type == type)
3107 return pcm;
3108 }
3109
3110 return NULL;
3111}
3112
3113static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3114{
3115 struct hda_pcm_stream *stream;
3116 struct hda_pcm *pcm;
3117 int err;
3118
3119 err = generic_hdmi_build_pcms(codec);
3120 if (err < 0)
3121 return err;
3122
3123 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3124 if (!pcm)
3125 return -ENODEV;
3126
3127 /*
3128 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3129 * codec about format changes.
3130 */
3131 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3132 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3133 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3134
3135 return 0;
3136}
3137
3138static int patch_tegra_hdmi(struct hda_codec *codec)
3139{
3140 int err;
3141
3142 err = patch_generic_hdmi(codec);
3143 if (err)
3144 return err;
3145
3146 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3147
3148 return 0;
3149}
3150
84eb01be 3151/*
5a613584 3152 * ATI/AMD-specific implementations
84eb01be
TI		 3153 */
3154
5a613584 3155#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3156 ((codec)->core.vendor_id == 0x1002aa01 && \
3157 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3158#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3159
3160/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3161#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3162#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3163#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3164#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3165#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3166#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3167#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3168#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3169#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3170#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3171#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3172#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3173#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3174#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3175#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3176#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3177#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3178#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3179#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3180#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3181#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3182#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3183#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3184#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3185
84d69e79
AH		 3186/* AMD specific HDA cvt verbs */
3187#define ATI_VERB_SET_RAMP_RATE 0x770
3188#define ATI_VERB_GET_RAMP_RATE 0xf70
3189
5a613584
AH		 3190#define ATI_OUT_ENABLE 0x1
3191
3192#define ATI_MULTICHANNEL_MODE_PAIRED 0
3193#define ATI_MULTICHANNEL_MODE_SINGLE 1
3194
461cf6b3
AH		 3195#define ATI_HBR_CAPABLE 0x01
3196#define ATI_HBR_ENABLE 0x10
3197
89250f84
AH		 3198static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3199 unsigned char *buf, int *eld_size)
3200{
3201 /* call hda_eld.c ATI/AMD-specific function */
3202 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3203 is_amdhdmi_rev3_or_later(codec));
3204}
3205
5a613584
AH		 3206static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3207 int active_channels, int conn_type)
3208{
3209 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3210}
3211
3212static int atihdmi_paired_swap_fc_lfe(int pos)
3213{
3214 /*
3215 * ATI/AMD have automatic FC/LFE swap built-in
3216 * when in pairwise mapping mode.
3217 */
3218
3219 switch (pos) {
3220 /* see channel_allocations[].speakers[] */
3221 case 2: return 3;
3222 case 3: return 2;
3223 default: break;
3224 }
3225
3226 return pos;
3227}
3228
3229static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3230{
3231 struct cea_channel_speaker_allocation *cap;
3232 int i, j;
3233
3234 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3235
3236 cap = &channel_allocations[get_channel_allocation_order(ca)];
3237 for (i = 0; i < chs; ++i) {
3238 int mask = to_spk_mask(map[i]);
3239 bool ok = false;
3240 bool companion_ok = false;
3241
3242 if (!mask)
3243 continue;
3244
3245 for (j = 0 + i % 2; j < 8; j += 2) {
3246 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3247 if (cap->speakers[chan_idx] == mask) {
3248 /* channel is in a supported position */
3249 ok = true;
3250
3251 if (i % 2 == 0 && i + 1 < chs) {
3252 /* even channel, check the odd companion */
3253 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3254 int comp_mask_req = to_spk_mask(map[i+1]);
3255 int comp_mask_act = cap->speakers[comp_chan_idx];
3256
3257 if (comp_mask_req == comp_mask_act)
3258 companion_ok = true;
3259 else
3260 return -EINVAL;
3261 }
3262 break;
3263 }
3264 }
3265
3266 if (!ok)
3267 return -EINVAL;
3268
3269 if (companion_ok)
3270 i++; /* companion channel already checked */
3271 }
3272
3273 return 0;
3274}
3275
3276static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3277 int hdmi_slot, int stream_channel)
3278{
3279 int verb;
3280 int ati_channel_setup = 0;
3281
3282 if (hdmi_slot > 7)
3283 return -EINVAL;
3284
3285 if (!has_amd_full_remap_support(codec)) {
3286 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3287
3288 /* In case this is an odd slot but without stream channel, do not
3289 * disable the slot since the corresponding even slot could have a
3290 * channel. In case neither have a channel, the slot pair will be
3291 * disabled when this function is called for the even slot. */
3292 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3293 return 0;
3294
3295 hdmi_slot -= hdmi_slot % 2;
3296
3297 if (stream_channel != 0xf)
3298 stream_channel -= stream_channel % 2;
3299 }
3300
3301 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3302
3303 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3304
3305 if (stream_channel != 0xf)
3306 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3307
3308 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3309}
3310
3311static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3312 int asp_slot)
3313{
3314 bool was_odd = false;
3315 int ati_asp_slot = asp_slot;
3316 int verb;
3317 int ati_channel_setup;
3318
3319 if (asp_slot > 7)
3320 return -EINVAL;
3321
3322 if (!has_amd_full_remap_support(codec)) {
3323 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3324 if (ati_asp_slot % 2 != 0) {
3325 ati_asp_slot -= 1;
3326 was_odd = true;
3327 }
3328 }
3329
3330 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3331
3332 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3333
3334 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3335 return 0xf;
3336
3337 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3338}
84eb01be 3339
5a613584
AH		 3340static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3341 int channels)
3342{
3343 int c;
3344
3345 /*
3346 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3347 * we need to take that into account (a single channel may take 2
3348 * channel slots if we need to carry a silent channel next to it).
3349 * On Rev3+ AMD codecs this function is not used.
3350 */
3351 int chanpairs = 0;
3352
3353 /* We only produce even-numbered channel count TLVs */
3354 if ((channels % 2) != 0)
3355 return -1;
3356
3357 for (c = 0; c < 7; c += 2) {
3358 if (cap->speakers[c] || cap->speakers[c+1])
3359 chanpairs++;
3360 }
3361
3362 if (chanpairs * 2 != channels)
3363 return -1;
3364
3365 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3366}
3367
3368static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3369 unsigned int *chmap, int channels)
3370{
3371 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3372 int count = 0;
3373 int c;
3374
3375 for (c = 7; c >= 0; c--) {
3376 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3377 int spk = cap->speakers[chan];
3378 if (!spk) {
3379 /* add N/A channel if the companion channel is occupied */
3380 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3381 chmap[count++] = SNDRV_CHMAP_NA;
3382
3383 continue;
3384 }
3385
3386 chmap[count++] = spk_to_chmap(spk);
3387 }
3388
3389 WARN_ON(count != channels);
3390}
3391
461cf6b3
AH		 3392static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3393 bool hbr)
3394{
3395 int hbr_ctl, hbr_ctl_new;
3396
3397 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3398 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3399 if (hbr)
3400 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3401 else
3402 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3403
4e76a883
TI		 3404 codec_dbg(codec,
3405 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3406 pin_nid,
3407 hbr_ctl == hbr_ctl_new ? "" : "new-",
3408 hbr_ctl_new);
3409
3410 if (hbr_ctl != hbr_ctl_new)
3411 snd_hda_codec_write(codec, pin_nid, 0,
3412 ATI_VERB_SET_HBR_CONTROL,
3413 hbr_ctl_new);
3414
3415 } else if (hbr)
3416 return -EINVAL;
3417
3418 return 0;
3419}
3420
84d69e79
AH		 3421static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3422 hda_nid_t pin_nid, u32 stream_tag, int format)
3423{
3424
3425 if (is_amdhdmi_rev3_or_later(codec)) {
3426 int ramp_rate = 180; /* default as per AMD spec */
3427 /* disable ramp-up/down for non-pcm as per AMD spec */
3428 if (format & AC_FMT_TYPE_NON_PCM)
3429 ramp_rate = 0;
3430
3431 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3432 }
3433
3434 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3435}
3436
3437
5a613584 3438static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3439{
3440 struct hdmi_spec *spec = codec->spec;
5a613584 3441 int pin_idx, err;
84eb01be 3442
5a613584
AH		 3443 err = generic_hdmi_init(codec);
3444
3445 if (err)
84eb01be 3446 return err;
5a613584
AH		 3447
3448 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3449 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3450
3451 /* make sure downmix information in infoframe is zero */
3452 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3453
3454 /* enable channel-wise remap mode if supported */
3455 if (has_amd_full_remap_support(codec))
3456 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3457 ATI_VERB_SET_MULTICHANNEL_MODE,
3458 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3459 }
5a613584 3460
84eb01be
TI		 3461 return 0;
3462}
3463
84eb01be
TI		 3464static int patch_atihdmi(struct hda_codec *codec)
3465{
3466 struct hdmi_spec *spec;
5a613584
AH		 3467 struct hdmi_spec_per_cvt *per_cvt;
3468 int err, cvt_idx;
3469
3470 err = patch_generic_hdmi(codec);
3471
3472 if (err)
d0b1252d 3473 return err;
5a613584
AH		 3474
3475 codec->patch_ops.init = atihdmi_init;
3476
d0b1252d 3477 spec = codec->spec;
5a613584 3478
89250f84 3479 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3480 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3481 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3482 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3483 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3484 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3485
3486 if (!has_amd_full_remap_support(codec)) {
3487 /* override to ATI/AMD-specific versions with pairwise mapping */
3488 spec->ops.chmap_cea_alloc_validate_get_type =
3489 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3490 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3491 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3492 }
3493
3494 /* ATI/AMD converters do not advertise all of their capabilities */
3495 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3496 per_cvt = get_cvt(spec, cvt_idx);
3497 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3498 per_cvt->rates |= SUPPORTED_RATES;
3499 per_cvt->formats |= SUPPORTED_FORMATS;
3500 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3501 }
3502
3503 spec->channels_max = max(spec->channels_max, 8u);
3504
84eb01be
TI		 3505 return 0;
3506}
3507
3de5ff88
AL		 3508/* VIA HDMI Implementation */
3509#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3510#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3511
3de5ff88
AL		 3512static int patch_via_hdmi(struct hda_codec *codec)
3513{
250e41ac 3514 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3515}
84eb01be
TI		 3516
3517/*
3518 * patch entries
3519 */
b9a94a9c
TI		 3520static const struct hda_device_id snd_hda_id_hdmi[] = {
3521HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3522HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3523HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3524HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3525HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3526HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3527HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3528HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3529HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3530HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3531HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3532HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3533HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3534HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3535HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3536HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3537HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3538HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3539HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3540HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3541HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3542HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3543HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 3544/* 17 is known to be absent */
b9a94a9c
TI		 3545HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3546HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3547HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3548HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3549HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3550HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3551HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3552HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3553HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3554HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3555HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3556HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3557HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3558HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3559HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3560HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3561HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3562HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3563HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3564HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3565HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3566HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3567HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3568HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3569HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3570HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3571HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3572HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3573HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3574HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3575HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3576HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3577HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3578HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3579HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3580HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3581HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
3582HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3583HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3584HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3585HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 3586/* special ID for generic HDMI */
b9a94a9c 3587HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 3588{} /* terminator */
3589};
b9a94a9c 3590MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 3591
3592MODULE_LICENSE("GPL");
3593MODULE_DESCRIPTION("HDMI HD-audio codec");
3594MODULE_ALIAS("snd-hda-codec-intelhdmi");
3595MODULE_ALIAS("snd-hda-codec-nvhdmi");
3596MODULE_ALIAS("snd-hda-codec-atihdmi");
3597
d8a766a1 3598static struct hda_codec_driver hdmi_driver = {
b9a94a9c 3599 .id = snd_hda_id_hdmi,
84eb01be
TI		 3600};
3601
d8a766a1 3602module_hda_codec_driver(hdmi_driver);
Michael's Linux tree.