core: add ofnode_get_by_phandle() api
[people/ms/u-boot.git] / README
CommitLineData
c609719b 1#
eca3aeb3 2# (C) Copyright 2000 - 2013
c609719b
WD
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
eca3aeb3 5# SPDX-License-Identifier: GPL-2.0+
c609719b
WD
6#
7
8Summary:
9========
10
24ee89b9 11This directory contains the source code for U-Boot, a boot loader for
e86e5a07
WD
12Embedded boards based on PowerPC, ARM, MIPS and several other
13processors, which can be installed in a boot ROM and used to
14initialize and test the hardware or to download and run application
15code.
c609719b
WD
16
17The development of U-Boot is closely related to Linux: some parts of
24ee89b9
WD
18the source code originate in the Linux source tree, we have some
19header files in common, and special provision has been made to
c609719b
WD
20support booting of Linux images.
21
22Some attention has been paid to make this software easily
23configurable and extendable. For instance, all monitor commands are
24implemented with the same call interface, so that it's very easy to
25add new commands. Also, instead of permanently adding rarely used
26code (for instance hardware test utilities) to the monitor, you can
27load and run it dynamically.
28
29
30Status:
31=======
32
33In general, all boards for which a configuration option exists in the
24ee89b9 34Makefile have been tested to some extent and can be considered
c609719b
WD
35"working". In fact, many of them are used in production systems.
36
7207b366
RD
37In case of problems see the CHANGELOG file to find out who contributed
38the specific port. In addition, there are various MAINTAINERS files
39scattered throughout the U-Boot source identifying the people or
40companies responsible for various boards and subsystems.
c609719b 41
7207b366
RD
42Note: As of August, 2010, there is no longer a CHANGELOG file in the
43actual U-Boot source tree; however, it can be created dynamically
44from the Git log using:
adb9d851
RD
45
46 make CHANGELOG
47
c609719b
WD
48
49Where to get help:
50==================
51
24ee89b9 52In case you have questions about, problems with or contributions for
7207b366 53U-Boot, you should send a message to the U-Boot mailing list at
0c32565f
PT
54<u-boot@lists.denx.de>. There is also an archive of previous traffic
55on the mailing list - please search the archive before asking FAQ's.
56Please see http://lists.denx.de/pipermail/u-boot and
57http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
c609719b
WD
58
59
218ca724
WD
60Where to get source code:
61=========================
62
7207b366 63The U-Boot source code is maintained in the Git repository at
218ca724
WD
64git://www.denx.de/git/u-boot.git ; you can browse it online at
65http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
66
67The "snapshot" links on this page allow you to download tarballs of
11ccc33f 68any version you might be interested in. Official releases are also
218ca724
WD
69available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
70directory.
71
d4ee711d 72Pre-built (and tested) images are available from
218ca724
WD
73ftp://ftp.denx.de/pub/u-boot/images/
74
75
c609719b
WD
76Where we come from:
77===================
78
79- start from 8xxrom sources
24ee89b9 80- create PPCBoot project (http://sourceforge.net/projects/ppcboot)
c609719b
WD
81- clean up code
82- make it easier to add custom boards
83- make it possible to add other [PowerPC] CPUs
84- extend functions, especially:
85 * Provide extended interface to Linux boot loader
86 * S-Record download
87 * network boot
11ccc33f 88 * PCMCIA / CompactFlash / ATA disk / SCSI ... boot
24ee89b9 89- create ARMBoot project (http://sourceforge.net/projects/armboot)
c609719b 90- add other CPU families (starting with ARM)
24ee89b9 91- create U-Boot project (http://sourceforge.net/projects/u-boot)
0d28f34b 92- current project page: see http://www.denx.de/wiki/U-Boot
24ee89b9
WD
93
94
95Names and Spelling:
96===================
97
98The "official" name of this project is "Das U-Boot". The spelling
99"U-Boot" shall be used in all written text (documentation, comments
100in source files etc.). Example:
101
102 This is the README file for the U-Boot project.
103
104File names etc. shall be based on the string "u-boot". Examples:
105
106 include/asm-ppc/u-boot.h
107
108 #include <asm/u-boot.h>
109
110Variable names, preprocessor constants etc. shall be either based on
111the string "u_boot" or on "U_BOOT". Example:
112
113 U_BOOT_VERSION u_boot_logo
114 IH_OS_U_BOOT u_boot_hush_start
c609719b
WD
115
116
93f19cc0
WD
117Versioning:
118===========
119
360d883a
TW
120Starting with the release in October 2008, the names of the releases
121were changed from numerical release numbers without deeper meaning
122into a time stamp based numbering. Regular releases are identified by
123names consisting of the calendar year and month of the release date.
124Additional fields (if present) indicate release candidates or bug fix
125releases in "stable" maintenance trees.
126
127Examples:
c0f40859 128 U-Boot v2009.11 - Release November 2009
360d883a 129 U-Boot v2009.11.1 - Release 1 in version November 2009 stable tree
0de21ecb 130 U-Boot v2010.09-rc1 - Release candidate 1 for September 2010 release
93f19cc0
WD
131
132
c609719b
WD
133Directory Hierarchy:
134====================
135
8d321b81 136/arch Architecture specific files
6eae68e4 137 /arc Files generic to ARC architecture
8d321b81 138 /arm Files generic to ARM architecture
8d321b81 139 /m68k Files generic to m68k architecture
8d321b81 140 /microblaze Files generic to microblaze architecture
8d321b81 141 /mips Files generic to MIPS architecture
afc1ce82 142 /nds32 Files generic to NDS32 architecture
8d321b81 143 /nios2 Files generic to Altera NIOS2 architecture
33c7731b 144 /openrisc Files generic to OpenRISC architecture
a47a12be 145 /powerpc Files generic to PowerPC architecture
3fafced7 146 /riscv Files generic to RISC-V architecture
7207b366 147 /sandbox Files generic to HW-independent "sandbox"
8d321b81 148 /sh Files generic to SH architecture
33c7731b 149 /x86 Files generic to x86 architecture
8d321b81
PT
150/api Machine/arch independent API for external apps
151/board Board dependent files
740f7e5c 152/cmd U-Boot commands functions
8d321b81 153/common Misc architecture independent functions
7207b366 154/configs Board default configuration files
8d321b81
PT
155/disk Code for disk drive partition handling
156/doc Documentation (don't expect too much)
157/drivers Commonly used device drivers
33c7731b 158/dts Contains Makefile for building internal U-Boot fdt.
8d321b81
PT
159/examples Example code for standalone applications, etc.
160/fs Filesystem code (cramfs, ext2, jffs2, etc.)
161/include Header Files
7207b366
RD
162/lib Library routines generic to all architectures
163/Licenses Various license files
8d321b81
PT
164/net Networking code
165/post Power On Self Test
7207b366
RD
166/scripts Various build scripts and Makefiles
167/test Various unit test files
8d321b81 168/tools Tools to build S-Record or U-Boot images, etc.
c609719b 169
c609719b
WD
170Software Configuration:
171=======================
172
173Configuration is usually done using C preprocessor defines; the
174rationale behind that is to avoid dead code whenever possible.
175
176There are two classes of configuration variables:
177
178* Configuration _OPTIONS_:
179 These are selectable by the user and have names beginning with
180 "CONFIG_".
181
182* Configuration _SETTINGS_:
183 These depend on the hardware etc. and should not be meddled with if
184 you don't know what you're doing; they have names beginning with
6d0f6bcf 185 "CONFIG_SYS_".
c609719b 186
7207b366
RD
187Previously, all configuration was done by hand, which involved creating
188symbolic links and editing configuration files manually. More recently,
189U-Boot has added the Kbuild infrastructure used by the Linux kernel,
190allowing you to use the "make menuconfig" command to configure your
191build.
c609719b
WD
192
193
194Selection of Processor Architecture and Board Type:
195---------------------------------------------------
196
197For all supported boards there are ready-to-use default
ab584d67 198configurations available; just type "make <board_name>_defconfig".
c609719b
WD
199
200Example: For a TQM823L module type:
201
202 cd u-boot
ab584d67 203 make TQM823L_defconfig
c609719b 204
7207b366
RD
205Note: If you're looking for the default configuration file for a board
206you're sure used to be there but is now missing, check the file
207doc/README.scrapyard for a list of no longer supported boards.
c609719b 208
75b3c3aa
SG
209Sandbox Environment:
210--------------------
211
212U-Boot can be built natively to run on a Linux host using the 'sandbox'
213board. This allows feature development which is not board- or architecture-
214specific to be undertaken on a native platform. The sandbox is also used to
215run some of U-Boot's tests.
216
6b1978f8 217See board/sandbox/README.sandbox for more details.
75b3c3aa
SG
218
219
db910353
SG
220Board Initialisation Flow:
221--------------------------
222
223This is the intended start-up flow for boards. This should apply for both
7207b366
RD
224SPL and U-Boot proper (i.e. they both follow the same rules).
225
226Note: "SPL" stands for "Secondary Program Loader," which is explained in
227more detail later in this file.
228
229At present, SPL mostly uses a separate code path, but the function names
230and roles of each function are the same. Some boards or architectures
231may not conform to this. At least most ARM boards which use
232CONFIG_SPL_FRAMEWORK conform to this.
233
234Execution typically starts with an architecture-specific (and possibly
235CPU-specific) start.S file, such as:
236
237 - arch/arm/cpu/armv7/start.S
238 - arch/powerpc/cpu/mpc83xx/start.S
239 - arch/mips/cpu/start.S
db910353 240
7207b366
RD
241and so on. From there, three functions are called; the purpose and
242limitations of each of these functions are described below.
db910353
SG
243
244lowlevel_init():
245 - purpose: essential init to permit execution to reach board_init_f()
246 - no global_data or BSS
247 - there is no stack (ARMv7 may have one but it will soon be removed)
248 - must not set up SDRAM or use console
249 - must only do the bare minimum to allow execution to continue to
250 board_init_f()
251 - this is almost never needed
252 - return normally from this function
253
254board_init_f():
255 - purpose: set up the machine ready for running board_init_r():
256 i.e. SDRAM and serial UART
257 - global_data is available
258 - stack is in SRAM
259 - BSS is not available, so you cannot use global/static variables,
260 only stack variables and global_data
261
262 Non-SPL-specific notes:
263 - dram_init() is called to set up DRAM. If already done in SPL this
264 can do nothing
265
266 SPL-specific notes:
267 - you can override the entire board_init_f() function with your own
268 version as needed.
269 - preloader_console_init() can be called here in extremis
270 - should set up SDRAM, and anything needed to make the UART work
271 - these is no need to clear BSS, it will be done by crt0.S
272 - must return normally from this function (don't call board_init_r()
273 directly)
274
275Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at
276this point the stack and global_data are relocated to below
277CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of
278memory.
279
280board_init_r():
281 - purpose: main execution, common code
282 - global_data is available
283 - SDRAM is available
284 - BSS is available, all static/global variables can be used
285 - execution eventually continues to main_loop()
286
287 Non-SPL-specific notes:
288 - U-Boot is relocated to the top of memory and is now running from
289 there.
290
291 SPL-specific notes:
292 - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
293 CONFIG_SPL_STACK_R_ADDR points into SDRAM
294 - preloader_console_init() can be called here - typically this is
0680f1b1 295 done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
db910353
SG
296 spl_board_init() function containing this call
297 - loads U-Boot or (in falcon mode) Linux
298
299
300
c609719b
WD
301Configuration Options:
302----------------------
303
304Configuration depends on the combination of board and CPU type; all
305such information is kept in a configuration file
306"include/configs/<board_name>.h".
307
308Example: For a TQM823L module, all configuration settings are in
309"include/configs/TQM823L.h".
310
311
7f6c2cbc
WD
312Many of the options are named exactly as the corresponding Linux
313kernel configuration options. The intention is to make it easier to
314build a config tool - later.
315
63b2316c
AK
316- ARM Platform Bus Type(CCI):
317 CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
318 provides full cache coherency between two clusters of multi-core
319 CPUs and I/O coherency for devices and I/O masters
320
321 CONFIG_SYS_FSL_HAS_CCI400
322
323 Defined For SoC that has cache coherent interconnect
324 CCN-400
7f6c2cbc 325
c055cee1
AK
326 CONFIG_SYS_FSL_HAS_CCN504
327
328 Defined for SoC that has cache coherent interconnect CCN-504
329
c609719b
WD
330The following options need to be configured:
331
2628114e
KP
332- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX.
333
334- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
6ccec449 335
cf946c6d
LW
336- Marvell Family Member
337 CONFIG_SYS_MVFS - define it if you want to enable
338 multiple fs option at one time
339 for marvell soc family
340
66412c63 341- 85xx CPU Options:
ffd06e02
YS
342 CONFIG_SYS_PPC64
343
344 Specifies that the core is a 64-bit PowerPC implementation (implements
345 the "64" category of the Power ISA). This is necessary for ePAPR
346 compliance, among other possible reasons.
347
66412c63
KG
348 CONFIG_SYS_FSL_TBCLK_DIV
349
350 Defines the core time base clock divider ratio compared to the
351 system clock. On most PQ3 devices this is 8, on newer QorIQ
352 devices it can be 16 or 32. The ratio varies from SoC to Soc.
353
8f29084a
KG
354 CONFIG_SYS_FSL_PCIE_COMPAT
355
356 Defines the string to utilize when trying to match PCIe device
357 tree nodes for the given platform.
358
33eee330
SW
359 CONFIG_SYS_FSL_ERRATUM_A004510
360
361 Enables a workaround for erratum A004510. If set,
362 then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
363 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
364
365 CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
366 CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
367
368 Defines one or two SoC revisions (low 8 bits of SVR)
369 for which the A004510 workaround should be applied.
370
371 The rest of SVR is either not relevant to the decision
372 of whether the erratum is present (e.g. p2040 versus
373 p2041) or is implied by the build target, which controls
374 whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
375
376 See Freescale App Note 4493 for more information about
377 this erratum.
378
74fa22ed
PK
379 CONFIG_A003399_NOR_WORKAROUND
380 Enables a workaround for IFC erratum A003399. It is only
b445bbb4 381 required during NOR boot.
74fa22ed 382
9f074e67
PK
383 CONFIG_A008044_WORKAROUND
384 Enables a workaround for T1040/T1042 erratum A008044. It is only
b445bbb4 385 required during NAND boot and valid for Rev 1.0 SoC revision
9f074e67 386
33eee330
SW
387 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
388
389 This is the value to write into CCSR offset 0x18600
390 according to the A004510 workaround.
391
64501c66
PJ
392 CONFIG_SYS_FSL_DSP_DDR_ADDR
393 This value denotes start offset of DDR memory which is
394 connected exclusively to the DSP cores.
395
765b0bdb
PJ
396 CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
397 This value denotes start offset of M2 memory
398 which is directly connected to the DSP core.
399
64501c66
PJ
400 CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
401 This value denotes start offset of M3 memory which is directly
402 connected to the DSP core.
403
765b0bdb
PJ
404 CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
405 This value denotes start offset of DSP CCSR space.
406
b135991a
PJ
407 CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
408 Single Source Clock is clocking mode present in some of FSL SoC's.
409 In this mode, a single differential clock is used to supply
410 clocks to the sysclock, ddrclock and usbclock.
411
fb4a2409
AB
412 CONFIG_SYS_CPC_REINIT_F
413 This CONFIG is defined when the CPC is configured as SRAM at the
a187559e 414 time of U-Boot entry and is required to be re-initialized.
fb4a2409 415
aade2004 416 CONFIG_DEEP_SLEEP
b445bbb4 417 Indicates this SoC supports deep sleep feature. If deep sleep is
aade2004
TY
418 supported, core will start to execute uboot when wakes up.
419
6cb461b4
DS
420- Generic CPU options:
421 CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
422
423 Defines the endianess of the CPU. Implementation of those
424 values is arch specific.
425
5614e71b
YS
426 CONFIG_SYS_FSL_DDR
427 Freescale DDR driver in use. This type of DDR controller is
428 found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
429 SoCs.
430
431 CONFIG_SYS_FSL_DDR_ADDR
432 Freescale DDR memory-mapped register base.
433
434 CONFIG_SYS_FSL_DDR_EMU
435 Specify emulator support for DDR. Some DDR features such as
436 deskew training are not available.
437
438 CONFIG_SYS_FSL_DDRC_GEN1
439 Freescale DDR1 controller.
440
441 CONFIG_SYS_FSL_DDRC_GEN2
442 Freescale DDR2 controller.
443
444 CONFIG_SYS_FSL_DDRC_GEN3
445 Freescale DDR3 controller.
446
34e026f9
YS
447 CONFIG_SYS_FSL_DDRC_GEN4
448 Freescale DDR4 controller.
449
9ac4ffbd
YS
450 CONFIG_SYS_FSL_DDRC_ARM_GEN3
451 Freescale DDR3 controller for ARM-based SoCs.
452
5614e71b
YS
453 CONFIG_SYS_FSL_DDR1
454 Board config to use DDR1. It can be enabled for SoCs with
455 Freescale DDR1 or DDR2 controllers, depending on the board
456 implemetation.
457
458 CONFIG_SYS_FSL_DDR2
62a3b7dd 459 Board config to use DDR2. It can be enabled for SoCs with
5614e71b
YS
460 Freescale DDR2 or DDR3 controllers, depending on the board
461 implementation.
462
463 CONFIG_SYS_FSL_DDR3
464 Board config to use DDR3. It can be enabled for SoCs with
34e026f9
YS
465 Freescale DDR3 or DDR3L controllers.
466
467 CONFIG_SYS_FSL_DDR3L
468 Board config to use DDR3L. It can be enabled for SoCs with
469 DDR3L controllers.
470
471 CONFIG_SYS_FSL_DDR4
472 Board config to use DDR4. It can be enabled for SoCs with
473 DDR4 controllers.
5614e71b 474
1b4175d6
PK
475 CONFIG_SYS_FSL_IFC_BE
476 Defines the IFC controller register space as Big Endian
477
478 CONFIG_SYS_FSL_IFC_LE
479 Defines the IFC controller register space as Little Endian
480
1c40707e
PK
481 CONFIG_SYS_FSL_IFC_CLK_DIV
482 Defines divider of platform clock(clock input to IFC controller).
483
add63f94
PK
484 CONFIG_SYS_FSL_LBC_CLK_DIV
485 Defines divider of platform clock(clock input to eLBC controller).
486
690e4258
PK
487 CONFIG_SYS_FSL_PBL_PBI
488 It enables addition of RCW (Power on reset configuration) in built image.
489 Please refer doc/README.pblimage for more details
490
491 CONFIG_SYS_FSL_PBL_RCW
492 It adds PBI(pre-boot instructions) commands in u-boot build image.
493 PBI commands can be used to configure SoC before it starts the execution.
494 Please refer doc/README.pblimage for more details
495
89ad7be8
PK
496 CONFIG_SPL_FSL_PBL
497 It adds a target to create boot binary having SPL binary in PBI format
498 concatenated with u-boot binary.
499
4e5b1bd0
YS
500 CONFIG_SYS_FSL_DDR_BE
501 Defines the DDR controller register space as Big Endian
502
503 CONFIG_SYS_FSL_DDR_LE
504 Defines the DDR controller register space as Little Endian
505
6b9e309a
YS
506 CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
507 Physical address from the view of DDR controllers. It is the
508 same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
509 it could be different for ARM SoCs.
510
6b1e1254
YS
511 CONFIG_SYS_FSL_DDR_INTLV_256B
512 DDR controller interleaving on 256-byte. This is a special
513 interleaving mode, handled by Dickens for Freescale layerscape
514 SoCs with ARM core.
515
1d71efbb
YS
516 CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
517 Number of controllers used as main memory.
518
519 CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
520 Number of controllers used for other than main memory.
521
44937214
PK
522 CONFIG_SYS_FSL_HAS_DP_DDR
523 Defines the SoC has DP-DDR used for DPAA.
524
028dbb8d
RG
525 CONFIG_SYS_FSL_SEC_BE
526 Defines the SEC controller register space as Big Endian
527
528 CONFIG_SYS_FSL_SEC_LE
529 Defines the SEC controller register space as Little Endian
530
92bbd64e
DS
531- MIPS CPU options:
532 CONFIG_SYS_INIT_SP_OFFSET
533
534 Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
535 pointer. This is needed for the temporary stack before
536 relocation.
537
538 CONFIG_SYS_MIPS_CACHE_MODE
539
540 Cache operation mode for the MIPS CPU.
541 See also arch/mips/include/asm/mipsregs.h.
542 Possible values are:
543 CONF_CM_CACHABLE_NO_WA
544 CONF_CM_CACHABLE_WA
545 CONF_CM_UNCACHED
546 CONF_CM_CACHABLE_NONCOHERENT
547 CONF_CM_CACHABLE_CE
548 CONF_CM_CACHABLE_COW
549 CONF_CM_CACHABLE_CUW
550 CONF_CM_CACHABLE_ACCELERATED
551
552 CONFIG_SYS_XWAY_EBU_BOOTCFG
553
554 Special option for Lantiq XWAY SoCs for booting from NOR flash.
555 See also arch/mips/cpu/mips32/start.S.
556
557 CONFIG_XWAY_SWAP_BYTES
558
559 Enable compilation of tools/xway-swap-bytes needed for Lantiq
560 XWAY SoCs for booting from NOR flash. The U-Boot image needs to
561 be swapped if a flash programmer is used.
562
b67d8816
CR
563- ARM options:
564 CONFIG_SYS_EXCEPTION_VECTORS_HIGH
565
566 Select high exception vectors of the ARM core, e.g., do not
567 clear the V bit of the c1 register of CP15.
568
207774b2
YS
569 COUNTER_FREQUENCY
570 Generic timer clock source frequency.
571
572 COUNTER_FREQUENCY_REAL
573 Generic timer clock source frequency if the real clock is
574 different from COUNTER_FREQUENCY, and can only be determined
575 at run time.
576
73c38934
SW
577- Tegra SoC options:
578 CONFIG_TEGRA_SUPPORT_NON_SECURE
579
580 Support executing U-Boot in non-secure (NS) mode. Certain
581 impossible actions will be skipped if the CPU is in NS mode,
582 such as ARM architectural timer initialization.
583
5da627a4 584- Linux Kernel Interface:
c609719b
WD
585 CONFIG_CLOCKS_IN_MHZ
586
587 U-Boot stores all clock information in Hz
588 internally. For binary compatibility with older Linux
589 kernels (which expect the clocks passed in the
590 bd_info data to be in MHz) the environment variable
591 "clocks_in_mhz" can be defined so that U-Boot
592 converts clock data to MHZ before passing it to the
593 Linux kernel.
c609719b 594 When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
218ca724 595 "clocks_in_mhz=1" is automatically included in the
c609719b
WD
596 default environment.
597
5da627a4
WD
598 CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
599
b445bbb4 600 When transferring memsize parameter to Linux, some versions
5da627a4
WD
601 expect it to be in bytes, others in MB.
602 Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
603
fec6d9ee 604 CONFIG_OF_LIBFDT
f57f70aa
WD
605
606 New kernel versions are expecting firmware settings to be
213bf8c8
GVB
607 passed using flattened device trees (based on open firmware
608 concepts).
609
610 CONFIG_OF_LIBFDT
611 * New libfdt-based support
612 * Adds the "fdt" command
3bb342fc 613 * The bootm command automatically updates the fdt
213bf8c8 614
f57f70aa 615 OF_TBCLK - The timebase frequency.
c2871f03 616 OF_STDOUT_PATH - The path to the console device
f57f70aa 617
11ccc33f
MZ
618 boards with QUICC Engines require OF_QE to set UCC MAC
619 addresses
3bb342fc 620
4e253137
KG
621 CONFIG_OF_BOARD_SETUP
622
623 Board code has addition modification that it wants to make
624 to the flat device tree before handing it off to the kernel
f57f70aa 625
c654b517
SG
626 CONFIG_OF_SYSTEM_SETUP
627
628 Other code has addition modification that it wants to make
629 to the flat device tree before handing it off to the kernel.
630 This causes ft_system_setup() to be called before booting
631 the kernel.
632
3887c3fb
HS
633 CONFIG_OF_IDE_FIXUP
634
635 U-Boot can detect if an IDE device is present or not.
636 If not, and this new config option is activated, U-Boot
637 removes the ATA node from the DTS before booting Linux,
638 so the Linux IDE driver does not probe the device and
639 crash. This is needed for buggy hardware (uc101) where
640 no pull down resistor is connected to the signal IDE5V_DD7.
641
7eb29398
IG
642 CONFIG_MACH_TYPE [relevant for ARM only][mandatory]
643
644 This setting is mandatory for all boards that have only one
645 machine type and must be used to specify the machine type
646 number as it appears in the ARM machine registry
647 (see http://www.arm.linux.org.uk/developer/machines/).
648 Only boards that have multiple machine types supported
649 in a single configuration file and the machine type is
650 runtime discoverable, do not have to use this setting.
651
0b2f4eca
NG
652- vxWorks boot parameters:
653
654 bootvx constructs a valid bootline using the following
9e98b7e3
BM
655 environments variables: bootdev, bootfile, ipaddr, netmask,
656 serverip, gatewayip, hostname, othbootargs.
0b2f4eca
NG
657 It loads the vxWorks image pointed bootfile.
658
0b2f4eca
NG
659 Note: If a "bootargs" environment is defined, it will overwride
660 the defaults discussed just above.
661
2c451f78
A
662- Cache Configuration:
663 CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
664 CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
665 CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
666
93bc2193
A
667- Cache Configuration for ARM:
668 CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
669 controller
670 CONFIG_SYS_PL310_BASE - Physical base address of PL310
671 controller register space
672
6705d81e 673- Serial Ports:
48d0192f 674 CONFIG_PL010_SERIAL
6705d81e
WD
675
676 Define this if you want support for Amba PrimeCell PL010 UARTs.
677
48d0192f 678 CONFIG_PL011_SERIAL
6705d81e
WD
679
680 Define this if you want support for Amba PrimeCell PL011 UARTs.
681
682 CONFIG_PL011_CLOCK
683
684 If you have Amba PrimeCell PL011 UARTs, set this variable to
685 the clock speed of the UARTs.
686
687 CONFIG_PL01x_PORTS
688
689 If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
690 define this to a list of base addresses for each (supported)
691 port. See e.g. include/configs/versatile.h
692
d57dee57
KM
693 CONFIG_SERIAL_HW_FLOW_CONTROL
694
695 Define this variable to enable hw flow control in serial driver.
696 Current user of this option is drivers/serial/nsl16550.c driver
6705d81e 697
c609719b
WD
698- Console Baudrate:
699 CONFIG_BAUDRATE - in bps
700 Select one of the baudrates listed in
6d0f6bcf 701 CONFIG_SYS_BAUDRATE_TABLE, see below.
c609719b 702
c609719b
WD
703- Autoboot Command:
704 CONFIG_BOOTCOMMAND
705 Only needed when CONFIG_BOOTDELAY is enabled;
706 define a command string that is automatically executed
707 when no character is read on the console interface
708 within "Boot Delay" after reset.
709
c609719b 710 CONFIG_RAMBOOT and CONFIG_NFSBOOT
43d9616c
WD
711 The value of these goes into the environment as
712 "ramboot" and "nfsboot" respectively, and can be used
713 as a convenience, when switching between booting from
11ccc33f 714 RAM and NFS.
c609719b 715
eda0ba38 716- Bootcount:
eda0ba38
HS
717 CONFIG_BOOTCOUNT_ENV
718 If no softreset save registers are found on the hardware
719 "bootcount" is stored in the environment. To prevent a
720 saveenv on all reboots, the environment variable
721 "upgrade_available" is used. If "upgrade_available" is
722 0, "bootcount" is always 0, if "upgrade_available" is
723 1 "bootcount" is incremented in the environment.
724 So the Userspace Applikation must set the "upgrade_available"
725 and "bootcount" variable to 0, if a boot was successfully.
726
c609719b
WD
727- Pre-Boot Commands:
728 CONFIG_PREBOOT
729
730 When this option is #defined, the existence of the
731 environment variable "preboot" will be checked
732 immediately before starting the CONFIG_BOOTDELAY
733 countdown and/or running the auto-boot command resp.
734 entering interactive mode.
735
736 This feature is especially useful when "preboot" is
737 automatically generated or modified. For an example
738 see the LWMON board specific code: here "preboot" is
739 modified when the user holds down a certain
740 combination of keys on the (special) keyboard when
741 booting the systems
742
743- Serial Download Echo Mode:
744 CONFIG_LOADS_ECHO
745 If defined to 1, all characters received during a
746 serial download (using the "loads" command) are
747 echoed back. This might be needed by some terminal
748 emulations (like "cu"), but may as well just take
749 time on others. This setting #define's the initial
750 value of the "loads_echo" environment variable.
751
602ad3b3 752- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
c609719b
WD
753 CONFIG_KGDB_BAUDRATE
754 Select one of the baudrates listed in
6d0f6bcf 755 CONFIG_SYS_BAUDRATE_TABLE, see below.
c609719b 756
302a6487
SG
757- Removal of commands
758 If no commands are needed to boot, you can disable
759 CONFIG_CMDLINE to remove them. In this case, the command line
760 will not be available, and when U-Boot wants to execute the
761 boot command (on start-up) it will call board_run_command()
762 instead. This can reduce image size significantly for very
763 simple boot procedures.
764
a5ecbe62
WD
765- Regular expression support:
766 CONFIG_REGEX
93e14596
WD
767 If this variable is defined, U-Boot is linked against
768 the SLRE (Super Light Regular Expression) library,
769 which adds regex support to some commands, as for
770 example "env grep" and "setexpr".
a5ecbe62 771
45ba8077
SG
772- Device tree:
773 CONFIG_OF_CONTROL
774 If this variable is defined, U-Boot will use a device tree
775 to configure its devices, instead of relying on statically
776 compiled #defines in the board file. This option is
777 experimental and only available on a few boards. The device
778 tree is available in the global data as gd->fdt_blob.
779
2c0f79e4 780 U-Boot needs to get its device tree from somewhere. This can
82f766d1 781 be done using one of the three options below:
bbb0b128
SG
782
783 CONFIG_OF_EMBED
784 If this variable is defined, U-Boot will embed a device tree
785 binary in its image. This device tree file should be in the
786 board directory and called <soc>-<board>.dts. The binary file
787 is then picked up in board_init_f() and made available through
eb3eb602 788 the global data structure as gd->fdt_blob.
45ba8077 789
2c0f79e4
SG
790 CONFIG_OF_SEPARATE
791 If this variable is defined, U-Boot will build a device tree
792 binary. It will be called u-boot.dtb. Architecture-specific
793 code will locate it at run-time. Generally this works by:
794
795 cat u-boot.bin u-boot.dtb >image.bin
796
797 and in fact, U-Boot does this for you, creating a file called
798 u-boot-dtb.bin which is useful in the common case. You can
799 still use the individual files if you need something more
800 exotic.
801
82f766d1
AD
802 CONFIG_OF_BOARD
803 If this variable is defined, U-Boot will use the device tree
804 provided by the board at runtime instead of embedding one with
805 the image. Only boards defining board_fdt_blob_setup() support
806 this option (see include/fdtdec.h file).
807
c609719b
WD
808- Watchdog:
809 CONFIG_WATCHDOG
810 If this variable is defined, it enables watchdog
6abe6fb6 811 support for the SoC. There must be support in the SoC
907208c4
CL
812 specific code for a watchdog. For the 8xx
813 CPUs, the SIU Watchdog feature is enabled in the SYPCR
814 register. When supported for a specific SoC is
815 available, then no further board specific code should
816 be needed to use it.
6abe6fb6
DZ
817
818 CONFIG_HW_WATCHDOG
819 When using a watchdog circuitry external to the used
820 SoC, then define this variable and provide board
821 specific code for the "hw_watchdog_reset" function.
c609719b 822
7bae0d6f
HS
823 CONFIG_AT91_HW_WDT_TIMEOUT
824 specify the timeout in seconds. default 2 seconds.
825
c1551ea8
SR
826- U-Boot Version:
827 CONFIG_VERSION_VARIABLE
828 If this variable is defined, an environment variable
829 named "ver" is created by U-Boot showing the U-Boot
830 version as printed by the "version" command.
a1ea8e51
BT
831 Any change to this variable will be reverted at the
832 next reset.
c1551ea8 833
c609719b
WD
834- Real-Time Clock:
835
602ad3b3 836 When CONFIG_CMD_DATE is selected, the type of the RTC
c609719b
WD
837 has to be selected, too. Define exactly one of the
838 following options:
839
c609719b 840 CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
4e8b7544 841 CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC
c609719b 842 CONFIG_RTC_MC146818 - use MC146818 RTC
1cb8e980 843 CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC
c609719b 844 CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC
7f70e853 845 CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC
412921d2 846 CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC
3bac3513 847 CONFIG_RTC_DS164x - use Dallas DS164x RTC
9536dfcc 848 CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
4c0d4c3b 849 CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
2bd3cab3 850 CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
71d19f30
HS
851 CONFIG_SYS_RV3029_TCR - enable trickle charger on
852 RV3029 RTC.
c609719b 853
b37c7e5e
WD
854 Note that if the RTC uses I2C, then the I2C interface
855 must also be configured. See I2C Support, below.
856
e92739d3
PT
857- GPIO Support:
858 CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
e92739d3 859
5dec49ca
CP
860 The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
861 chip-ngpio pairs that tell the PCA953X driver the number of
862 pins supported by a particular chip.
863
e92739d3
PT
864 Note that if the GPIO device uses I2C, then the I2C interface
865 must also be configured. See I2C Support, below.
866
aa53233a
SG
867- I/O tracing:
868 When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
869 accesses and can checksum them or write a list of them out
870 to memory. See the 'iotrace' command for details. This is
871 useful for testing device drivers since it can confirm that
872 the driver behaves the same way before and after a code
873 change. Currently this is supported on sandbox and arm. To
874 add support for your architecture, add '#include <iotrace.h>'
875 to the bottom of arch/<arch>/include/asm/io.h and test.
876
877 Example output from the 'iotrace stats' command is below.
878 Note that if the trace buffer is exhausted, the checksum will
879 still continue to operate.
880
881 iotrace is enabled
882 Start: 10000000 (buffer start address)
883 Size: 00010000 (buffer size)
884 Offset: 00000120 (current buffer offset)
885 Output: 10000120 (start + offset)
886 Count: 00000018 (number of trace records)
887 CRC32: 9526fb66 (CRC32 of all trace records)
888
c609719b
WD
889- Timestamp Support:
890
43d9616c
WD
891 When CONFIG_TIMESTAMP is selected, the timestamp
892 (date and time) of an image is printed by image
893 commands like bootm or iminfo. This option is
602ad3b3 894 automatically enabled when you select CONFIG_CMD_DATE .
c609719b 895
923c46f9
KP
896- Partition Labels (disklabels) Supported:
897 Zero or more of the following:
898 CONFIG_MAC_PARTITION Apple's MacOS partition table.
923c46f9
KP
899 CONFIG_ISO_PARTITION ISO partition table, used on CDROM etc.
900 CONFIG_EFI_PARTITION GPT partition table, common when EFI is the
901 bootloader. Note 2TB partition limit; see
902 disk/part_efi.c
903 CONFIG_MTD_PARTITIONS Memory Technology Device partition table.
c609719b 904
fc843a02 905 If IDE or SCSI support is enabled (CONFIG_IDE or
c649e3c9 906 CONFIG_SCSI) you must configure support for at
923c46f9 907 least one non-MTD partition type as well.
c609719b
WD
908
909- IDE Reset method:
4d13cbad
WD
910 CONFIG_IDE_RESET_ROUTINE - this is defined in several
911 board configurations files but used nowhere!
c609719b 912
4d13cbad
WD
913 CONFIG_IDE_RESET - is this is defined, IDE Reset will
914 be performed by calling the function
915 ide_set_reset(int reset)
916 which has to be defined in a board specific file
c609719b
WD
917
918- ATAPI Support:
919 CONFIG_ATAPI
920
921 Set this to enable ATAPI support.
922
c40b2956
WD
923- LBA48 Support
924 CONFIG_LBA48
925
926 Set this to enable support for disks larger than 137GB
4b142feb 927 Also look at CONFIG_SYS_64BIT_LBA.
c40b2956
WD
928 Whithout these , LBA48 support uses 32bit variables and will 'only'
929 support disks up to 2.1TB.
930
6d0f6bcf 931 CONFIG_SYS_64BIT_LBA:
c40b2956
WD
932 When enabled, makes the IDE subsystem use 64bit sector addresses.
933 Default is 32bit.
934
c609719b 935- SCSI Support:
6d0f6bcf
JCPV
936 CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
937 CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
938 CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
c609719b
WD
939 maximum numbers of LUNs, SCSI ID's and target
940 devices.
c609719b 941
93e14596
WD
942 The environment variable 'scsidevs' is set to the number of
943 SCSI devices found during the last scan.
447c031b 944
c609719b 945- NETWORK Support (PCI):
682011ff 946 CONFIG_E1000
ce5207e1
KM
947 Support for Intel 8254x/8257x gigabit chips.
948
949 CONFIG_E1000_SPI
950 Utility code for direct access to the SPI bus on Intel 8257x.
951 This does not do anything useful unless you set at least one
952 of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
953
954 CONFIG_E1000_SPI_GENERIC
955 Allow generic access to the SPI bus on the Intel 8257x, for
956 example with the "sspi" command.
957
c609719b
WD
958 CONFIG_EEPRO100
959 Support for Intel 82557/82559/82559ER chips.
11ccc33f 960 Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
c609719b
WD
961 write routine for first time initialisation.
962
963 CONFIG_TULIP
964 Support for Digital 2114x chips.
965 Optional CONFIG_TULIP_SELECT_MEDIA for board specific
966 modem chip initialisation (KS8761/QS6611).
967
968 CONFIG_NATSEMI
969 Support for National dp83815 chips.
970
971 CONFIG_NS8382X
972 Support for National dp8382[01] gigabit chips.
973
45219c46
WD
974- NETWORK Support (other):
975
c041e9d2
JS
976 CONFIG_DRIVER_AT91EMAC
977 Support for AT91RM9200 EMAC.
978
979 CONFIG_RMII
980 Define this to use reduced MII inteface
981
982 CONFIG_DRIVER_AT91EMAC_QUIET
983 If this defined, the driver is quiet.
984 The driver doen't show link status messages.
985
efdd7319
RH
986 CONFIG_CALXEDA_XGMAC
987 Support for the Calxeda XGMAC device
988
3bb46d23 989 CONFIG_LAN91C96
45219c46
WD
990 Support for SMSC's LAN91C96 chips.
991
45219c46
WD
992 CONFIG_LAN91C96_USE_32_BIT
993 Define this to enable 32 bit addressing
994
3bb46d23 995 CONFIG_SMC91111
f39748ae
WD
996 Support for SMSC's LAN91C111 chip
997
998 CONFIG_SMC91111_BASE
999 Define this to hold the physical address
1000 of the device (I/O space)
1001
1002 CONFIG_SMC_USE_32_BIT
1003 Define this if data bus is 32 bits
1004
1005 CONFIG_SMC_USE_IOFUNCS
1006 Define this to use i/o functions instead of macros
1007 (some hardware wont work with macros)
1008
dc02bada
HS
1009 CONFIG_DRIVER_TI_EMAC
1010 Support for davinci emac
1011
1012 CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
1013 Define this if you have more then 3 PHYs.
1014
b3dbf4a5
ML
1015 CONFIG_FTGMAC100
1016 Support for Faraday's FTGMAC100 Gigabit SoC Ethernet
1017
1018 CONFIG_FTGMAC100_EGIGA
1019 Define this to use GE link update with gigabit PHY.
1020 Define this if FTGMAC100 is connected to gigabit PHY.
1021 If your system has 10/100 PHY only, it might not occur
1022 wrong behavior. Because PHY usually return timeout or
1023 useless data when polling gigabit status and gigabit
1024 control registers. This behavior won't affect the
1025 correctnessof 10/100 link speed update.
1026
3d0075fa
YS
1027 CONFIG_SH_ETHER
1028 Support for Renesas on-chip Ethernet controller
1029
1030 CONFIG_SH_ETHER_USE_PORT
1031 Define the number of ports to be used
1032
1033 CONFIG_SH_ETHER_PHY_ADDR
1034 Define the ETH PHY's address
1035
68260aab
YS
1036 CONFIG_SH_ETHER_CACHE_WRITEBACK
1037 If this option is set, the driver enables cache flush.
1038
b2f97cf2
HS
1039- PWM Support:
1040 CONFIG_PWM_IMX
5052e819 1041 Support for PWM module on the imx6.
b2f97cf2 1042
5e124724 1043- TPM Support:
90899cc0
CC
1044 CONFIG_TPM
1045 Support TPM devices.
1046
0766ad2f
CR
1047 CONFIG_TPM_TIS_INFINEON
1048 Support for Infineon i2c bus TPM devices. Only one device
1b393db5
TWHT
1049 per system is supported at this time.
1050
1b393db5
TWHT
1051 CONFIG_TPM_TIS_I2C_BURST_LIMITATION
1052 Define the burst count bytes upper limit
1053
3aa74088
CR
1054 CONFIG_TPM_ST33ZP24
1055 Support for STMicroelectronics TPM devices. Requires DM_TPM support.
1056
1057 CONFIG_TPM_ST33ZP24_I2C
1058 Support for STMicroelectronics ST33ZP24 I2C devices.
1059 Requires TPM_ST33ZP24 and I2C.
1060
b75fdc11
CR
1061 CONFIG_TPM_ST33ZP24_SPI
1062 Support for STMicroelectronics ST33ZP24 SPI devices.
1063 Requires TPM_ST33ZP24 and SPI.
1064
c01939c7
DE
1065 CONFIG_TPM_ATMEL_TWI
1066 Support for Atmel TWI TPM device. Requires I2C support.
1067
90899cc0 1068 CONFIG_TPM_TIS_LPC
5e124724
VB
1069 Support for generic parallel port TPM devices. Only one device
1070 per system is supported at this time.
1071
1072 CONFIG_TPM_TIS_BASE_ADDRESS
1073 Base address where the generic TPM device is mapped
1074 to. Contemporary x86 systems usually map it at
1075 0xfed40000.
1076
be6c1529
RP
1077 CONFIG_TPM
1078 Define this to enable the TPM support library which provides
1079 functional interfaces to some TPM commands.
1080 Requires support for a TPM device.
1081
1082 CONFIG_TPM_AUTH_SESSIONS
1083 Define this to enable authorized functions in the TPM library.
1084 Requires CONFIG_TPM and CONFIG_SHA1.
1085
c609719b
WD
1086- USB Support:
1087 At the moment only the UHCI host controller is
064b55cf 1088 supported (PIP405, MIP405); define
c609719b
WD
1089 CONFIG_USB_UHCI to enable it.
1090 define CONFIG_USB_KEYBOARD to enable the USB Keyboard
30d56fae 1091 and define CONFIG_USB_STORAGE to enable the USB
c609719b
WD
1092 storage devices.
1093 Note:
1094 Supported are USB Keyboards and USB Floppy drives
1095 (TEAC FD-05PUB).
4d13cbad 1096
9ab4ce22
SG
1097 CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
1098 txfilltuning field in the EHCI controller on reset.
1099
6e9e0626
OT
1100 CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
1101 HW module registers.
1102
16c8d5e7
WD
1103- USB Device:
1104 Define the below if you wish to use the USB console.
1105 Once firmware is rebuilt from a serial console issue the
1106 command "setenv stdin usbtty; setenv stdout usbtty" and
11ccc33f 1107 attach your USB cable. The Unix command "dmesg" should print
16c8d5e7
WD
1108 it has found a new device. The environment variable usbtty
1109 can be set to gserial or cdc_acm to enable your device to
386eda02 1110 appear to a USB host as a Linux gserial device or a
16c8d5e7
WD
1111 Common Device Class Abstract Control Model serial device.
1112 If you select usbtty = gserial you should be able to enumerate
1113 a Linux host by
1114 # modprobe usbserial vendor=0xVendorID product=0xProductID
1115 else if using cdc_acm, simply setting the environment
1116 variable usbtty to be cdc_acm should suffice. The following
1117 might be defined in YourBoardName.h
386eda02 1118
16c8d5e7
WD
1119 CONFIG_USB_DEVICE
1120 Define this to build a UDC device
1121
1122 CONFIG_USB_TTY
1123 Define this to have a tty type of device available to
1124 talk to the UDC device
386eda02 1125
f9da0f89
VK
1126 CONFIG_USBD_HS
1127 Define this to enable the high speed support for usb
1128 device and usbtty. If this feature is enabled, a routine
1129 int is_usbd_high_speed(void)
1130 also needs to be defined by the driver to dynamically poll
1131 whether the enumeration has succeded at high speed or full
1132 speed.
1133
6d0f6bcf 1134 CONFIG_SYS_CONSOLE_IS_IN_ENV
16c8d5e7
WD
1135 Define this if you want stdin, stdout &/or stderr to
1136 be set to usbtty.
1137
386eda02 1138 If you have a USB-IF assigned VendorID then you may wish to
16c8d5e7 1139 define your own vendor specific values either in BoardName.h
386eda02 1140 or directly in usbd_vendor_info.h. If you don't define
16c8d5e7
WD
1141 CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME,
1142 CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot
1143 should pretend to be a Linux device to it's target host.
1144
1145 CONFIG_USBD_MANUFACTURER
1146 Define this string as the name of your company for
1147 - CONFIG_USBD_MANUFACTURER "my company"
386eda02 1148
16c8d5e7
WD
1149 CONFIG_USBD_PRODUCT_NAME
1150 Define this string as the name of your product
1151 - CONFIG_USBD_PRODUCT_NAME "acme usb device"
1152
1153 CONFIG_USBD_VENDORID
1154 Define this as your assigned Vendor ID from the USB
1155 Implementors Forum. This *must* be a genuine Vendor ID
1156 to avoid polluting the USB namespace.
1157 - CONFIG_USBD_VENDORID 0xFFFF
386eda02 1158
16c8d5e7
WD
1159 CONFIG_USBD_PRODUCTID
1160 Define this as the unique Product ID
1161 for your device
1162 - CONFIG_USBD_PRODUCTID 0xFFFF
4d13cbad 1163
d70a560f
IG
1164- ULPI Layer Support:
1165 The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
1166 the generic ULPI layer. The generic layer accesses the ULPI PHY
1167 via the platform viewport, so you need both the genric layer and
1168 the viewport enabled. Currently only Chipidea/ARC based
1169 viewport is supported.
1170 To enable the ULPI layer support, define CONFIG_USB_ULPI and
1171 CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
6d365ea0
LS
1172 If your ULPI phy needs a different reference clock than the
1173 standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
1174 the appropriate value in Hz.
c609719b 1175
71f95118 1176- MMC Support:
8bde7f77
WD
1177 The MMC controller on the Intel PXA is supported. To
1178 enable this define CONFIG_MMC. The MMC can be
1179 accessed from the boot prompt by mapping the device
71f95118 1180 to physical memory similar to flash. Command line is
602ad3b3
JL
1181 enabled with CONFIG_CMD_MMC. The MMC driver also works with
1182 the FAT fs. This is enabled with CONFIG_CMD_FAT.
71f95118 1183
afb35666
YS
1184 CONFIG_SH_MMCIF
1185 Support for Renesas on-chip MMCIF controller
1186
1187 CONFIG_SH_MMCIF_ADDR
1188 Define the base address of MMCIF registers
1189
1190 CONFIG_SH_MMCIF_CLK
1191 Define the clock frequency for MMCIF
1192
1fd93c6e
PA
1193 CONFIG_SUPPORT_EMMC_BOOT
1194 Enable some additional features of the eMMC boot partitions.
1195
1196 CONFIG_SUPPORT_EMMC_RPMB
1197 Enable the commands for reading, writing and programming the
1198 key for the Replay Protection Memory Block partition in eMMC.
1199
b3ba6e94 1200- USB Device Firmware Update (DFU) class support:
01acd6ab 1201 CONFIG_USB_FUNCTION_DFU
b3ba6e94
TR
1202 This enables the USB portion of the DFU USB class
1203
b3ba6e94
TR
1204 CONFIG_DFU_MMC
1205 This enables support for exposing (e)MMC devices via DFU.
1206
c6631764
PA
1207 CONFIG_DFU_NAND
1208 This enables support for exposing NAND devices via DFU.
1209
a9479f04
AM
1210 CONFIG_DFU_RAM
1211 This enables support for exposing RAM via DFU.
1212 Note: DFU spec refer to non-volatile memory usage, but
1213 allow usages beyond the scope of spec - here RAM usage,
1214 one that would help mostly the developer.
1215
e7e75c70
HS
1216 CONFIG_SYS_DFU_DATA_BUF_SIZE
1217 Dfu transfer uses a buffer before writing data to the
1218 raw storage device. Make the size (in bytes) of this buffer
1219 configurable. The size of this buffer is also configurable
1220 through the "dfu_bufsiz" environment variable.
1221
ea2453d5
PA
1222 CONFIG_SYS_DFU_MAX_FILE_SIZE
1223 When updating files rather than the raw storage device,
1224 we use a static buffer to copy the file into and then write
1225 the buffer once we've been given the whole file. Define
1226 this to the maximum filesize (in bytes) for the buffer.
1227 Default is 4 MiB if undefined.
1228
001a8319
HS
1229 DFU_DEFAULT_POLL_TIMEOUT
1230 Poll timeout [ms], is the timeout a device can send to the
1231 host. The host must wait for this timeout before sending
1232 a subsequent DFU_GET_STATUS request to the device.
1233
1234 DFU_MANIFEST_POLL_TIMEOUT
1235 Poll timeout [ms], which the device sends to the host when
1236 entering dfuMANIFEST state. Host waits this timeout, before
1237 sending again an USB request to the device.
1238
6705d81e 1239- Journaling Flash filesystem support:
b2482dff 1240 CONFIG_JFFS2_NAND
6705d81e
WD
1241 Define these for a default partition on a NAND device
1242
6d0f6bcf
JCPV
1243 CONFIG_SYS_JFFS2_FIRST_SECTOR,
1244 CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
6705d81e
WD
1245 Define these for a default partition on a NOR device
1246
c609719b 1247- Keyboard Support:
39f615ed
SG
1248 See Kconfig help for available keyboard drivers.
1249
1250 CONFIG_KEYBOARD
1251
1252 Define this to enable a custom keyboard support.
1253 This simply calls drv_keyboard_init() which must be
1254 defined in your board-specific files. This option is deprecated
1255 and is only used by novena. For new boards, use driver model
1256 instead.
c609719b
WD
1257
1258- Video support:
7d3053fb 1259 CONFIG_FSL_DIU_FB
04e5ae79 1260 Enable the Freescale DIU video driver. Reference boards for
7d3053fb
TT
1261 SOCs that have a DIU should define this macro to enable DIU
1262 support, and should also define these other macros:
1263
1264 CONFIG_SYS_DIU_ADDR
1265 CONFIG_VIDEO
7d3053fb
TT
1266 CONFIG_CFB_CONSOLE
1267 CONFIG_VIDEO_SW_CURSOR
1268 CONFIG_VGA_AS_SINGLE_DEVICE
1269 CONFIG_VIDEO_LOGO
1270 CONFIG_VIDEO_BMP_LOGO
1271
ba8e76bd
TT
1272 The DIU driver will look for the 'video-mode' environment
1273 variable, and if defined, enable the DIU as a console during
8eca9439 1274 boot. See the documentation file doc/README.video for a
ba8e76bd 1275 description of this variable.
7d3053fb 1276
c609719b
WD
1277- LCD Support: CONFIG_LCD
1278
1279 Define this to enable LCD support (for output to LCD
1280 display); also select one of the supported displays
1281 by defining one of these:
1282
39cf4804
SP
1283 CONFIG_ATMEL_LCD:
1284
1285 HITACHI TX09D70VM1CCA, 3.5", 240x320.
1286
fd3103bb 1287 CONFIG_NEC_NL6448AC33:
c609719b 1288
fd3103bb 1289 NEC NL6448AC33-18. Active, color, single scan.
c609719b 1290
fd3103bb 1291 CONFIG_NEC_NL6448BC20
c609719b 1292
fd3103bb
WD
1293 NEC NL6448BC20-08. 6.5", 640x480.
1294 Active, color, single scan.
1295
1296 CONFIG_NEC_NL6448BC33_54
1297
1298 NEC NL6448BC33-54. 10.4", 640x480.
c609719b
WD
1299 Active, color, single scan.
1300
1301 CONFIG_SHARP_16x9
1302
1303 Sharp 320x240. Active, color, single scan.
1304 It isn't 16x9, and I am not sure what it is.
1305
1306 CONFIG_SHARP_LQ64D341
1307
1308 Sharp LQ64D341 display, 640x480.
1309 Active, color, single scan.
1310
1311 CONFIG_HLD1045
1312
1313 HLD1045 display, 640x480.
1314 Active, color, single scan.
1315
1316 CONFIG_OPTREX_BW
1317
1318 Optrex CBL50840-2 NF-FW 99 22 M5
1319 or
1320 Hitachi LMG6912RPFC-00T
1321 or
1322 Hitachi SP14Q002
1323
1324 320x240. Black & white.
1325
676d319e
SG
1326 CONFIG_LCD_ALIGNMENT
1327
b445bbb4 1328 Normally the LCD is page-aligned (typically 4KB). If this is
676d319e
SG
1329 defined then the LCD will be aligned to this value instead.
1330 For ARM it is sometimes useful to use MMU_SECTION_SIZE
1331 here, since it is cheaper to change data cache settings on
1332 a per-section basis.
1333
1334
604c7d4a
HP
1335 CONFIG_LCD_ROTATION
1336
1337 Sometimes, for example if the display is mounted in portrait
1338 mode or even if it's mounted landscape but rotated by 180degree,
1339 we need to rotate our content of the display relative to the
1340 framebuffer, so that user can read the messages which are
1341 printed out.
1342 Once CONFIG_LCD_ROTATION is defined, the lcd_console will be
1343 initialized with a given rotation from "vl_rot" out of
1344 "vidinfo_t" which is provided by the board specific code.
1345 The value for vl_rot is coded as following (matching to
1346 fbcon=rotate:<n> linux-kernel commandline):
1347 0 = no rotation respectively 0 degree
1348 1 = 90 degree rotation
1349 2 = 180 degree rotation
1350 3 = 270 degree rotation
1351
1352 If CONFIG_LCD_ROTATION is not defined, the console will be
1353 initialized with 0degree rotation.
1354
45d7f525
TWHT
1355 CONFIG_LCD_BMP_RLE8
1356
1357 Support drawing of RLE8-compressed bitmaps on the LCD.
1358
735987c5
TWHT
1359 CONFIG_I2C_EDID
1360
1361 Enables an 'i2c edid' command which can read EDID
1362 information over I2C from an attached LCD display.
1363
7152b1d0 1364- Splash Screen Support: CONFIG_SPLASH_SCREEN
d791b1dc 1365
8bde7f77
WD
1366 If this option is set, the environment is checked for
1367 a variable "splashimage". If found, the usual display
1368 of logo, copyright and system information on the LCD
e94d2cd9 1369 is suppressed and the BMP image at the address
8bde7f77
WD
1370 specified in "splashimage" is loaded instead. The
1371 console is redirected to the "nulldev", too. This
1372 allows for a "silent" boot where a splash screen is
1373 loaded very quickly after power-on.
d791b1dc 1374
c0880485
NK
1375 CONFIG_SPLASHIMAGE_GUARD
1376
1377 If this option is set, then U-Boot will prevent the environment
1378 variable "splashimage" from being set to a problematic address
ab5645f1 1379 (see doc/README.displaying-bmps).
c0880485
NK
1380 This option is useful for targets where, due to alignment
1381 restrictions, an improperly aligned BMP image will cause a data
1382 abort. If you think you will not have problems with unaligned
1383 accesses (for example because your toolchain prevents them)
1384 there is no need to set this option.
1385
1ca298ce
MW
1386 CONFIG_SPLASH_SCREEN_ALIGN
1387
1388 If this option is set the splash image can be freely positioned
1389 on the screen. Environment variable "splashpos" specifies the
1390 position as "x,y". If a positive number is given it is used as
1391 number of pixel from left/top. If a negative number is given it
1392 is used as number of pixel from right/bottom. You can also
1393 specify 'm' for centering the image.
1394
1395 Example:
1396 setenv splashpos m,m
1397 => image at center of screen
1398
1399 setenv splashpos 30,20
1400 => image at x = 30 and y = 20
1401
1402 setenv splashpos -10,m
1403 => vertically centered image
1404 at x = dspWidth - bmpWidth - 9
1405
98f4a3df
SR
1406- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
1407
1408 If this option is set, additionally to standard BMP
1409 images, gzipped BMP images can be displayed via the
1410 splashscreen support or the bmp command.
1411
d5011762
AG
1412- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
1413
1414 If this option is set, 8-bit RLE compressed BMP images
1415 can be displayed via the splashscreen support or the
1416 bmp command.
1417
c29fdfc1 1418- Compression support:
8ef70478
KC
1419 CONFIG_GZIP
1420
1421 Enabled by default to support gzip compressed images.
1422
c29fdfc1
WD
1423 CONFIG_BZIP2
1424
1425 If this option is set, support for bzip2 compressed
1426 images is included. If not, only uncompressed and gzip
1427 compressed images are supported.
1428
42d1f039 1429 NOTE: the bzip2 algorithm requires a lot of RAM, so
6d0f6bcf 1430 the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
42d1f039 1431 be at least 4MB.
d791b1dc 1432
17ea1177
WD
1433- MII/PHY support:
1434 CONFIG_PHY_ADDR
1435
1436 The address of PHY on MII bus.
1437
1438 CONFIG_PHY_CLOCK_FREQ (ppc4xx)
1439
1440 The clock frequency of the MII bus
1441
17ea1177
WD
1442 CONFIG_PHY_RESET_DELAY
1443
1444 Some PHY like Intel LXT971A need extra delay after
1445 reset before any MII register access is possible.
1446 For such PHY, set this option to the usec delay
1447 required. (minimum 300usec for LXT971A)
1448
1449 CONFIG_PHY_CMD_DELAY (ppc4xx)
1450
1451 Some PHY like Intel LXT971A need extra delay after
1452 command issued before MII status register can be read
1453
c609719b
WD
1454- IP address:
1455 CONFIG_IPADDR
1456
1457 Define a default value for the IP address to use for
11ccc33f 1458 the default Ethernet interface, in case this is not
c609719b 1459 determined through e.g. bootp.
1ebcd654 1460 (Environment variable "ipaddr")
c609719b
WD
1461
1462- Server IP address:
1463 CONFIG_SERVERIP
1464
11ccc33f 1465 Defines a default value for the IP address of a TFTP
c609719b 1466 server to contact when using the "tftboot" command.
1ebcd654 1467 (Environment variable "serverip")
c609719b 1468
97cfe861
RG
1469 CONFIG_KEEP_SERVERADDR
1470
1471 Keeps the server's MAC address, in the env 'serveraddr'
1472 for passing to bootargs (like Linux's netconsole option)
1473
1ebcd654
WD
1474- Gateway IP address:
1475 CONFIG_GATEWAYIP
1476
1477 Defines a default value for the IP address of the
1478 default router where packets to other networks are
1479 sent to.
1480 (Environment variable "gatewayip")
1481
1482- Subnet mask:
1483 CONFIG_NETMASK
1484
1485 Defines a default value for the subnet mask (or
1486 routing prefix) which is used to determine if an IP
1487 address belongs to the local subnet or needs to be
1488 forwarded through a router.
1489 (Environment variable "netmask")
1490
53a5c424
DU
1491- Multicast TFTP Mode:
1492 CONFIG_MCAST_TFTP
1493
1494 Defines whether you want to support multicast TFTP as per
1495 rfc-2090; for example to work with atftp. Lets lots of targets
11ccc33f 1496 tftp down the same boot image concurrently. Note: the Ethernet
53a5c424
DU
1497 driver in use must provide a function: mcast() to join/leave a
1498 multicast group.
1499
c609719b
WD
1500- BOOTP Recovery Mode:
1501 CONFIG_BOOTP_RANDOM_DELAY
1502
1503 If you have many targets in a network that try to
1504 boot using BOOTP, you may want to avoid that all
1505 systems send out BOOTP requests at precisely the same
1506 moment (which would happen for instance at recovery
1507 from a power failure, when all systems will try to
1508 boot, thus flooding the BOOTP server. Defining
1509 CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
1510 inserted before sending out BOOTP requests. The
6c33c785 1511 following delays are inserted then:
c609719b
WD
1512
1513 1st BOOTP request: delay 0 ... 1 sec
1514 2nd BOOTP request: delay 0 ... 2 sec
1515 3rd BOOTP request: delay 0 ... 4 sec
1516 4th and following
1517 BOOTP requests: delay 0 ... 8 sec
1518
92ac8acc
TR
1519 CONFIG_BOOTP_ID_CACHE_SIZE
1520
1521 BOOTP packets are uniquely identified using a 32-bit ID. The
1522 server will copy the ID from client requests to responses and
1523 U-Boot will use this to determine if it is the destination of
1524 an incoming response. Some servers will check that addresses
1525 aren't in use before handing them out (usually using an ARP
1526 ping) and therefore take up to a few hundred milliseconds to
1527 respond. Network congestion may also influence the time it
1528 takes for a response to make it back to the client. If that
1529 time is too long, U-Boot will retransmit requests. In order
1530 to allow earlier responses to still be accepted after these
1531 retransmissions, U-Boot's BOOTP client keeps a small cache of
1532 IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
1533 cache. The default is to keep IDs for up to four outstanding
1534 requests. Increasing this will allow U-Boot to accept offers
1535 from a BOOTP client in networks with unusually high latency.
1536
fe389a82 1537- DHCP Advanced Options:
1fe80d79
JL
1538 You can fine tune the DHCP functionality by defining
1539 CONFIG_BOOTP_* symbols:
1540
1541 CONFIG_BOOTP_SUBNETMASK
1542 CONFIG_BOOTP_GATEWAY
1543 CONFIG_BOOTP_HOSTNAME
1544 CONFIG_BOOTP_NISDOMAIN
1545 CONFIG_BOOTP_BOOTPATH
1546 CONFIG_BOOTP_BOOTFILESIZE
1547 CONFIG_BOOTP_DNS
1548 CONFIG_BOOTP_DNS2
1549 CONFIG_BOOTP_SEND_HOSTNAME
1550 CONFIG_BOOTP_NTPSERVER
1551 CONFIG_BOOTP_TIMEOFFSET
1552 CONFIG_BOOTP_VENDOREX
2c00e099 1553 CONFIG_BOOTP_MAY_FAIL
fe389a82 1554
5d110f0a
WC
1555 CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
1556 environment variable, not the BOOTP server.
fe389a82 1557
2c00e099
JH
1558 CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
1559 after the configured retry count, the call will fail
1560 instead of starting over. This can be used to fail over
1561 to Link-local IP address configuration if the DHCP server
1562 is not available.
1563
fe389a82
SR
1564 CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
1565 serverip from a DHCP server, it is possible that more
1566 than one DNS serverip is offered to the client.
1567 If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
1568 serverip will be stored in the additional environment
1569 variable "dnsip2". The first DNS serverip is always
1570 stored in the variable "dnsip", when CONFIG_BOOTP_DNS
1fe80d79 1571 is defined.
fe389a82
SR
1572
1573 CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
1574 to do a dynamic update of a DNS server. To do this, they
1575 need the hostname of the DHCP requester.
5d110f0a 1576 If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
1fe80d79
JL
1577 of the "hostname" environment variable is passed as
1578 option 12 to the DHCP server.
fe389a82 1579
d9a2f416
AV
1580 CONFIG_BOOTP_DHCP_REQUEST_DELAY
1581
1582 A 32bit value in microseconds for a delay between
1583 receiving a "DHCP Offer" and sending the "DHCP Request".
1584 This fixes a problem with certain DHCP servers that don't
1585 respond 100% of the time to a "DHCP request". E.g. On an
1586 AT91RM9200 processor running at 180MHz, this delay needed
1587 to be *at least* 15,000 usec before a Windows Server 2003
1588 DHCP server would reply 100% of the time. I recommend at
1589 least 50,000 usec to be safe. The alternative is to hope
1590 that one of the retries will be successful but note that
1591 the DHCP timeout and retry process takes a longer than
1592 this delay.
1593
d22c338e
JH
1594 - Link-local IP address negotiation:
1595 Negotiate with other link-local clients on the local network
1596 for an address that doesn't require explicit configuration.
1597 This is especially useful if a DHCP server cannot be guaranteed
1598 to exist in all environments that the device must operate.
1599
1600 See doc/README.link-local for more information.
1601
24acb83d
PK
1602 - MAC address from environment variables
1603
1604 FDT_SEQ_MACADDR_FROM_ENV
1605
1606 Fix-up device tree with MAC addresses fetched sequentially from
1607 environment variables. This config work on assumption that
1608 non-usable ethernet node of device-tree are either not present
1609 or their status has been marked as "disabled".
1610
a3d991bd 1611 - CDP Options:
6e592385 1612 CONFIG_CDP_DEVICE_ID
a3d991bd
WD
1613
1614 The device id used in CDP trigger frames.
1615
1616 CONFIG_CDP_DEVICE_ID_PREFIX
1617
1618 A two character string which is prefixed to the MAC address
1619 of the device.
1620
1621 CONFIG_CDP_PORT_ID
1622
1623 A printf format string which contains the ascii name of
1624 the port. Normally is set to "eth%d" which sets
11ccc33f 1625 eth0 for the first Ethernet, eth1 for the second etc.
a3d991bd
WD
1626
1627 CONFIG_CDP_CAPABILITIES
1628
1629 A 32bit integer which indicates the device capabilities;
1630 0x00000010 for a normal host which does not forwards.
1631
1632 CONFIG_CDP_VERSION
1633
1634 An ascii string containing the version of the software.
1635
1636 CONFIG_CDP_PLATFORM
1637
1638 An ascii string containing the name of the platform.
1639
1640 CONFIG_CDP_TRIGGER
1641
1642 A 32bit integer sent on the trigger.
1643
1644 CONFIG_CDP_POWER_CONSUMPTION
1645
1646 A 16bit integer containing the power consumption of the
1647 device in .1 of milliwatts.
1648
1649 CONFIG_CDP_APPLIANCE_VLAN_TYPE
1650
1651 A byte containing the id of the VLAN.
1652
79267edd 1653- Status LED: CONFIG_LED_STATUS
c609719b
WD
1654
1655 Several configurations allow to display the current
1656 status using a LED. For instance, the LED will blink
1657 fast while running U-Boot code, stop blinking as
1658 soon as a reply to a BOOTP request was received, and
1659 start blinking slow once the Linux kernel is running
1660 (supported by a status LED driver in the Linux
79267edd 1661 kernel). Defining CONFIG_LED_STATUS enables this
c609719b
WD
1662 feature in U-Boot.
1663
1df7bbba
IG
1664 Additional options:
1665
79267edd 1666 CONFIG_LED_STATUS_GPIO
1df7bbba
IG
1667 The status LED can be connected to a GPIO pin.
1668 In such cases, the gpio_led driver can be used as a
79267edd 1669 status LED backend implementation. Define CONFIG_LED_STATUS_GPIO
1df7bbba
IG
1670 to include the gpio_led driver in the U-Boot binary.
1671
9dfdcdfe
IG
1672 CONFIG_GPIO_LED_INVERTED_TABLE
1673 Some GPIO connected LEDs may have inverted polarity in which
1674 case the GPIO high value corresponds to LED off state and
1675 GPIO low value corresponds to LED on state.
1676 In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
1677 with a list of GPIO LEDs that have inverted polarity.
1678
3f4978c7
HS
1679- I2C Support: CONFIG_SYS_I2C
1680
1681 This enable the NEW i2c subsystem, and will allow you to use
1682 i2c commands at the u-boot command line (as long as you set
1683 CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c
1684 based realtime clock chips or other i2c devices. See
1685 common/cmd_i2c.c for a description of the command line
1686 interface.
1687
1688 ported i2c driver to the new framework:
ea818dbb
HS
1689 - drivers/i2c/soft_i2c.c:
1690 - activate first bus with CONFIG_SYS_I2C_SOFT define
1691 CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
1692 for defining speed and slave address
1693 - activate second bus with I2C_SOFT_DECLARATIONS2 define
1694 CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
1695 for defining speed and slave address
1696 - activate third bus with I2C_SOFT_DECLARATIONS3 define
1697 CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
1698 for defining speed and slave address
1699 - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
1700 CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
1701 for defining speed and slave address
3f4978c7 1702
00f792e0
HS
1703 - drivers/i2c/fsl_i2c.c:
1704 - activate i2c driver with CONFIG_SYS_I2C_FSL
1705 define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
1706 offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
1707 CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
1708 bus.
93e14596 1709 - If your board supports a second fsl i2c bus, define
00f792e0
HS
1710 CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
1711 CONFIG_SYS_FSL_I2C2_SPEED for the speed and
1712 CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
1713 second bus.
1714
1f2ba722 1715 - drivers/i2c/tegra_i2c.c:
10cee516
NI
1716 - activate this driver with CONFIG_SYS_I2C_TEGRA
1717 - This driver adds 4 i2c buses with a fix speed from
1718 100000 and the slave addr 0!
1f2ba722 1719
880540de
DE
1720 - drivers/i2c/ppc4xx_i2c.c
1721 - activate this driver with CONFIG_SYS_I2C_PPC4XX
1722 - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
1723 - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
1724
fac96408 1725 - drivers/i2c/i2c_mxc.c
1726 - activate this driver with CONFIG_SYS_I2C_MXC
03544c66
AA
1727 - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
1728 - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
1729 - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
1730 - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
fac96408 1731 - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
1732 - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
1733 - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
1734 - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
1735 - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
1736 - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
03544c66
AA
1737 - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
1738 - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
b445bbb4 1739 If those defines are not set, default value is 100000
fac96408 1740 for speed, and 0 for slave.
1741
1086bfa9
NI
1742 - drivers/i2c/rcar_i2c.c:
1743 - activate this driver with CONFIG_SYS_I2C_RCAR
1744 - This driver adds 4 i2c buses
1745
1746 - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
1747 - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
1748 - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
1749 - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
1750 - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
1751 - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
1752 - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
1753 - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
1754 - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
1755
2035d77d
NI
1756 - drivers/i2c/sh_i2c.c:
1757 - activate this driver with CONFIG_SYS_I2C_SH
1758 - This driver adds from 2 to 5 i2c buses
1759
1760 - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
1761 - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
1762 - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
1763 - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
1764 - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
1765 - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
1766 - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
1767 - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
1768 - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
1769 - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
b445bbb4 1770 - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
2035d77d 1771
6789e84e
HS
1772 - drivers/i2c/omap24xx_i2c.c
1773 - activate this driver with CONFIG_SYS_I2C_OMAP24XX
1774 - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
1775 - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
1776 - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
1777 - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
1778 - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
1779 - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
1780 - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
1781 - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
1782 - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
1783 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
1784
0bdffe71
HS
1785 - drivers/i2c/zynq_i2c.c
1786 - activate this driver with CONFIG_SYS_I2C_ZYNQ
1787 - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
1788 - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
1789
e717fc6d
NKC
1790 - drivers/i2c/s3c24x0_i2c.c:
1791 - activate this driver with CONFIG_SYS_I2C_S3C24X0
1792 - This driver adds i2c buses (11 for Exynos5250, Exynos5420
1793 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
1794 with a fix speed from 100000 and the slave addr 0!
1795
b46226bd
DE
1796 - drivers/i2c/ihs_i2c.c
1797 - activate this driver with CONFIG_SYS_I2C_IHS
1798 - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
1799 - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
1800 - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
1801 - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
1802 - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
1803 - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
1804 - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
1805 - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
1806 - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
1807 - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
1808 - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
1809 - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
071be896
DE
1810 - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
1811 - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
1812 - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
1813 - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
1814 - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
1815 - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
1816 - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
1817 - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
1818 - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
b46226bd 1819
3f4978c7
HS
1820 additional defines:
1821
1822 CONFIG_SYS_NUM_I2C_BUSES
945a18e6 1823 Hold the number of i2c buses you want to use.
3f4978c7
HS
1824
1825 CONFIG_SYS_I2C_DIRECT_BUS
1826 define this, if you don't use i2c muxes on your hardware.
1827 if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
1828 omit this define.
1829
1830 CONFIG_SYS_I2C_MAX_HOPS
1831 define how many muxes are maximal consecutively connected
1832 on one i2c bus. If you not use i2c muxes, omit this
1833 define.
1834
1835 CONFIG_SYS_I2C_BUSES
b445bbb4 1836 hold a list of buses you want to use, only used if
3f4978c7
HS
1837 CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
1838 a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
1839 CONFIG_SYS_NUM_I2C_BUSES = 9:
1840
1841 CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
1842 {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
1843 {0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
1844 {0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
1845 {0, {{I2C_MUX_PCA9547, 0x70, 4}}}, \
1846 {0, {{I2C_MUX_PCA9547, 0x70, 5}}}, \
1847 {1, {I2C_NULL_HOP}}, \
1848 {1, {{I2C_MUX_PCA9544, 0x72, 1}}}, \
1849 {1, {{I2C_MUX_PCA9544, 0x72, 2}}}, \
1850 }
1851
1852 which defines
1853 bus 0 on adapter 0 without a mux
ea818dbb
HS
1854 bus 1 on adapter 0 with a PCA9547 on address 0x70 port 1
1855 bus 2 on adapter 0 with a PCA9547 on address 0x70 port 2
1856 bus 3 on adapter 0 with a PCA9547 on address 0x70 port 3
1857 bus 4 on adapter 0 with a PCA9547 on address 0x70 port 4
1858 bus 5 on adapter 0 with a PCA9547 on address 0x70 port 5
3f4978c7 1859 bus 6 on adapter 1 without a mux
ea818dbb
HS
1860 bus 7 on adapter 1 with a PCA9544 on address 0x72 port 1
1861 bus 8 on adapter 1 with a PCA9544 on address 0x72 port 2
3f4978c7
HS
1862
1863 If you do not have i2c muxes on your board, omit this define.
1864
ce3b5d69 1865- Legacy I2C Support:
ea818dbb 1866 If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
b37c7e5e
WD
1867 then the following macros need to be defined (examples are
1868 from include/configs/lwmon.h):
c609719b
WD
1869
1870 I2C_INIT
1871
b37c7e5e 1872 (Optional). Any commands necessary to enable the I2C
43d9616c 1873 controller or configure ports.
c609719b 1874
ba56f625 1875 eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
b37c7e5e 1876
c609719b
WD
1877 I2C_ACTIVE
1878
1879 The code necessary to make the I2C data line active
1880 (driven). If the data line is open collector, this
1881 define can be null.
1882
b37c7e5e
WD
1883 eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
1884
c609719b
WD
1885 I2C_TRISTATE
1886
1887 The code necessary to make the I2C data line tri-stated
1888 (inactive). If the data line is open collector, this
1889 define can be null.
1890
b37c7e5e
WD
1891 eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
1892
c609719b
WD
1893 I2C_READ
1894
472d5460
YS
1895 Code that returns true if the I2C data line is high,
1896 false if it is low.
c609719b 1897
b37c7e5e
WD
1898 eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
1899
c609719b
WD
1900 I2C_SDA(bit)
1901
472d5460
YS
1902 If <bit> is true, sets the I2C data line high. If it
1903 is false, it clears it (low).
c609719b 1904
b37c7e5e 1905 eg: #define I2C_SDA(bit) \
2535d602 1906 if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
ba56f625 1907 else immr->im_cpm.cp_pbdat &= ~PB_SDA
b37c7e5e 1908
c609719b
WD
1909 I2C_SCL(bit)
1910
472d5460
YS
1911 If <bit> is true, sets the I2C clock line high. If it
1912 is false, it clears it (low).
c609719b 1913
b37c7e5e 1914 eg: #define I2C_SCL(bit) \
2535d602 1915 if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
ba56f625 1916 else immr->im_cpm.cp_pbdat &= ~PB_SCL
b37c7e5e 1917
c609719b
WD
1918 I2C_DELAY
1919
1920 This delay is invoked four times per clock cycle so this
1921 controls the rate of data transfer. The data rate thus
b37c7e5e 1922 is 1 / (I2C_DELAY * 4). Often defined to be something
945af8d7
WD
1923 like:
1924
b37c7e5e 1925 #define I2C_DELAY udelay(2)
c609719b 1926
793b5726
MF
1927 CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
1928
1929 If your arch supports the generic GPIO framework (asm/gpio.h),
1930 then you may alternatively define the two GPIOs that are to be
1931 used as SCL / SDA. Any of the previous I2C_xxx macros will
1932 have GPIO-based defaults assigned to them as appropriate.
1933
1934 You should define these to the GPIO value as given directly to
1935 the generic GPIO functions.
1936
6d0f6bcf 1937 CONFIG_SYS_I2C_INIT_BOARD
47cd00fa 1938
8bde7f77
WD
1939 When a board is reset during an i2c bus transfer
1940 chips might think that the current transfer is still
1941 in progress. On some boards it is possible to access
1942 the i2c SCLK line directly, either by using the
1943 processor pin as a GPIO or by having a second pin
1944 connected to the bus. If this option is defined a
1945 custom i2c_init_board() routine in boards/xxx/board.c
1946 is run early in the boot sequence.
47cd00fa 1947
bb99ad6d
BW
1948 CONFIG_I2C_MULTI_BUS
1949
1950 This option allows the use of multiple I2C buses, each of which
c0f40859
WD
1951 must have a controller. At any point in time, only one bus is
1952 active. To switch to a different bus, use the 'i2c dev' command.
bb99ad6d
BW
1953 Note that bus numbering is zero-based.
1954
6d0f6bcf 1955 CONFIG_SYS_I2C_NOPROBES
bb99ad6d
BW
1956
1957 This option specifies a list of I2C devices that will be skipped
c0f40859 1958 when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
0f89c54b
PT
1959 is set, specify a list of bus-device pairs. Otherwise, specify
1960 a 1D array of device addresses
bb99ad6d
BW
1961
1962 e.g.
1963 #undef CONFIG_I2C_MULTI_BUS
c0f40859 1964 #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
bb99ad6d
BW
1965
1966 will skip addresses 0x50 and 0x68 on a board with one I2C bus
1967
c0f40859 1968 #define CONFIG_I2C_MULTI_BUS
945a18e6 1969 #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
bb99ad6d
BW
1970
1971 will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
1972
6d0f6bcf 1973 CONFIG_SYS_SPD_BUS_NUM
be5e6181
TT
1974
1975 If defined, then this indicates the I2C bus number for DDR SPD.
1976 If not defined, then U-Boot assumes that SPD is on I2C bus 0.
1977
6d0f6bcf 1978 CONFIG_SYS_RTC_BUS_NUM
0dc018ec
SR
1979
1980 If defined, then this indicates the I2C bus number for the RTC.
1981 If not defined, then U-Boot assumes that RTC is on I2C bus 0.
1982
2ac6985a
AD
1983 CONFIG_SOFT_I2C_READ_REPEATED_START
1984
1985 defining this will force the i2c_read() function in
1986 the soft_i2c driver to perform an I2C repeated start
1987 between writing the address pointer and reading the
1988 data. If this define is omitted the default behaviour
1989 of doing a stop-start sequence will be used. Most I2C
1990 devices can use either method, but some require one or
1991 the other.
be5e6181 1992
c609719b
WD
1993- SPI Support: CONFIG_SPI
1994
1995 Enables SPI driver (so far only tested with
1996 SPI EEPROM, also an instance works with Crystal A/D and
1997 D/As on the SACSng board)
1998
c609719b
WD
1999 CONFIG_SOFT_SPI
2000
43d9616c
WD
2001 Enables a software (bit-bang) SPI driver rather than
2002 using hardware support. This is a general purpose
2003 driver that only requires three general I/O port pins
2004 (two outputs, one input) to function. If this is
2005 defined, the board configuration must define several
2006 SPI configuration items (port pins to use, etc). For
2007 an example, see include/configs/sacsng.h.
c609719b 2008
04a9e118
BW
2009 CONFIG_HARD_SPI
2010
2011 Enables a hardware SPI driver for general-purpose reads
2012 and writes. As with CONFIG_SOFT_SPI, the board configuration
2013 must define a list of chip-select function pointers.
c0f40859 2014 Currently supported on some MPC8xxx processors. For an
04a9e118
BW
2015 example, see include/configs/mpc8349emds.h.
2016
f659b573
HS
2017 CONFIG_SYS_SPI_MXC_WAIT
2018 Timeout for waiting until spi transfer completed.
2019 default: (CONFIG_SYS_HZ/100) /* 10 ms */
2020
0133502e 2021- FPGA Support: CONFIG_FPGA
c609719b 2022
0133502e
MF
2023 Enables FPGA subsystem.
2024
2025 CONFIG_FPGA_<vendor>
2026
2027 Enables support for specific chip vendors.
2028 (ALTERA, XILINX)
c609719b 2029
0133502e 2030 CONFIG_FPGA_<family>
c609719b 2031
0133502e
MF
2032 Enables support for FPGA family.
2033 (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
2034
2035 CONFIG_FPGA_COUNT
2036
2037 Specify the number of FPGA devices to support.
c609719b 2038
6d0f6bcf 2039 CONFIG_SYS_FPGA_PROG_FEEDBACK
c609719b 2040
8bde7f77 2041 Enable printing of hash marks during FPGA configuration.
c609719b 2042
6d0f6bcf 2043 CONFIG_SYS_FPGA_CHECK_BUSY
c609719b 2044
43d9616c
WD
2045 Enable checks on FPGA configuration interface busy
2046 status by the configuration function. This option
2047 will require a board or device specific function to
2048 be written.
c609719b
WD
2049
2050 CONFIG_FPGA_DELAY
2051
2052 If defined, a function that provides delays in the FPGA
2053 configuration driver.
2054
6d0f6bcf 2055 CONFIG_SYS_FPGA_CHECK_CTRLC
c609719b
WD
2056 Allow Control-C to interrupt FPGA configuration
2057
6d0f6bcf 2058 CONFIG_SYS_FPGA_CHECK_ERROR
c609719b 2059
43d9616c
WD
2060 Check for configuration errors during FPGA bitfile
2061 loading. For example, abort during Virtex II
2062 configuration if the INIT_B line goes low (which
2063 indicated a CRC error).
c609719b 2064
6d0f6bcf 2065 CONFIG_SYS_FPGA_WAIT_INIT
c609719b 2066
b445bbb4
JM
2067 Maximum time to wait for the INIT_B line to de-assert
2068 after PROB_B has been de-asserted during a Virtex II
43d9616c 2069 FPGA configuration sequence. The default time is 500
11ccc33f 2070 ms.
c609719b 2071
6d0f6bcf 2072 CONFIG_SYS_FPGA_WAIT_BUSY
c609719b 2073
b445bbb4 2074 Maximum time to wait for BUSY to de-assert during
11ccc33f 2075 Virtex II FPGA configuration. The default is 5 ms.
c609719b 2076
6d0f6bcf 2077 CONFIG_SYS_FPGA_WAIT_CONFIG
c609719b 2078
43d9616c 2079 Time to wait after FPGA configuration. The default is
11ccc33f 2080 200 ms.
c609719b
WD
2081
2082- Configuration Management:
b2b8a696
SR
2083 CONFIG_BUILD_TARGET
2084
2085 Some SoCs need special image types (e.g. U-Boot binary
2086 with a special header) as build targets. By defining
2087 CONFIG_BUILD_TARGET in the SoC / board header, this
2088 special image will be automatically built upon calling
6de80f21 2089 make / buildman.
b2b8a696 2090
c609719b
WD
2091 CONFIG_IDENT_STRING
2092
43d9616c
WD
2093 If defined, this string will be added to the U-Boot
2094 version information (U_BOOT_VERSION)
c609719b
WD
2095
2096- Vendor Parameter Protection:
2097
43d9616c
WD
2098 U-Boot considers the values of the environment
2099 variables "serial#" (Board Serial Number) and
7152b1d0 2100 "ethaddr" (Ethernet Address) to be parameters that
43d9616c
WD
2101 are set once by the board vendor / manufacturer, and
2102 protects these variables from casual modification by
2103 the user. Once set, these variables are read-only,
2104 and write or delete attempts are rejected. You can
11ccc33f 2105 change this behaviour:
c609719b
WD
2106
2107 If CONFIG_ENV_OVERWRITE is #defined in your config
2108 file, the write protection for vendor parameters is
47cd00fa 2109 completely disabled. Anybody can change or delete
c609719b
WD
2110 these parameters.
2111
92ac5208
JH
2112 Alternatively, if you define _both_ an ethaddr in the
2113 default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
11ccc33f 2114 Ethernet address is installed in the environment,
c609719b
WD
2115 which can be changed exactly ONCE by the user. [The
2116 serial# is unaffected by this, i. e. it remains
2117 read-only.]
2118
2598090b
JH
2119 The same can be accomplished in a more flexible way
2120 for any variable by configuring the type of access
2121 to allow for those variables in the ".flags" variable
2122 or define CONFIG_ENV_FLAGS_LIST_STATIC.
2123
c609719b
WD
2124- Protected RAM:
2125 CONFIG_PRAM
2126
2127 Define this variable to enable the reservation of
2128 "protected RAM", i. e. RAM which is not overwritten
2129 by U-Boot. Define CONFIG_PRAM to hold the number of
2130 kB you want to reserve for pRAM. You can overwrite
2131 this default value by defining an environment
2132 variable "pram" to the number of kB you want to
2133 reserve. Note that the board info structure will
2134 still show the full amount of RAM. If pRAM is
2135 reserved, a new environment variable "mem" will
2136 automatically be defined to hold the amount of
2137 remaining RAM in a form that can be passed as boot
2138 argument to Linux, for instance like that:
2139
fe126d8b 2140 setenv bootargs ... mem=\${mem}
c609719b
WD
2141 saveenv
2142
2143 This way you can tell Linux not to use this memory,
2144 either, which results in a memory region that will
2145 not be affected by reboots.
2146
2147 *WARNING* If your board configuration uses automatic
2148 detection of the RAM size, you must make sure that
2149 this memory test is non-destructive. So far, the
2150 following board configurations are known to be
2151 "pRAM-clean":
2152
5b8e76c3 2153 IVMS8, IVML24, SPD8xx,
1b0757ec 2154 HERMES, IP860, RPXlite, LWMON,
2eb48ff7 2155 FLAGADM
c609719b 2156
40fef049
GB
2157- Access to physical memory region (> 4GB)
2158 Some basic support is provided for operations on memory not
2159 normally accessible to U-Boot - e.g. some architectures
2160 support access to more than 4GB of memory on 32-bit
2161 machines using physical address extension or similar.
2162 Define CONFIG_PHYSMEM to access this basic support, which
2163 currently only supports clearing the memory.
2164
c609719b 2165- Error Recovery:
c609719b
WD
2166 CONFIG_NET_RETRY_COUNT
2167
43d9616c
WD
2168 This variable defines the number of retries for
2169 network operations like ARP, RARP, TFTP, or BOOTP
2170 before giving up the operation. If not defined, a
2171 default value of 5 is used.
c609719b 2172
40cb90ee
GL
2173 CONFIG_ARP_TIMEOUT
2174
2175 Timeout waiting for an ARP reply in milliseconds.
2176
48a3e999
TK
2177 CONFIG_NFS_TIMEOUT
2178
2179 Timeout in milliseconds used in NFS protocol.
2180 If you encounter "ERROR: Cannot umount" in nfs command,
2181 try longer timeout such as
2182 #define CONFIG_NFS_TIMEOUT 10000UL
2183
c609719b 2184- Command Interpreter:
8078f1a5 2185 CONFIG_AUTO_COMPLETE
04a85b3b
WD
2186
2187 Enable auto completion of commands using TAB.
2188
6d0f6bcf 2189 CONFIG_SYS_PROMPT_HUSH_PS2
c609719b
WD
2190
2191 This defines the secondary prompt string, which is
2192 printed when the command interpreter needs more input
2193 to complete a command. Usually "> ".
2194
2195 Note:
2196
8bde7f77
WD
2197 In the current implementation, the local variables
2198 space and global environment variables space are
2199 separated. Local variables are those you define by
2200 simply typing `name=value'. To access a local
2201 variable later on, you have write `$name' or
2202 `${name}'; to execute the contents of a variable
2203 directly type `$name' at the command prompt.
c609719b 2204
43d9616c
WD
2205 Global environment variables are those you use
2206 setenv/printenv to work with. To run a command stored
2207 in such a variable, you need to use the run command,
2208 and you must not use the '$' sign to access them.
c609719b
WD
2209
2210 To store commands and special characters in a
2211 variable, please use double quotation marks
2212 surrounding the whole text of the variable, instead
2213 of the backslashes before semicolons and special
2214 symbols.
2215
b445bbb4 2216- Command Line Editing and History:
aa0c71ac
WD
2217 CONFIG_CMDLINE_EDITING
2218
11ccc33f 2219 Enable editing and History functions for interactive
b445bbb4 2220 command line input operations
aa0c71ac 2221
f3b267b3
MV
2222- Command Line PS1/PS2 support:
2223 CONFIG_CMDLINE_PS_SUPPORT
2224
2225 Enable support for changing the command prompt string
2226 at run-time. Only static string is supported so far.
2227 The string is obtained from environment variables PS1
2228 and PS2.
2229
a8c7c708 2230- Default Environment:
c609719b
WD
2231 CONFIG_EXTRA_ENV_SETTINGS
2232
43d9616c
WD
2233 Define this to contain any number of null terminated
2234 strings (variable = value pairs) that will be part of
7152b1d0 2235 the default environment compiled into the boot image.
2262cfee 2236
43d9616c
WD
2237 For example, place something like this in your
2238 board's config file:
c609719b
WD
2239
2240 #define CONFIG_EXTRA_ENV_SETTINGS \
2241 "myvar1=value1\0" \
2242 "myvar2=value2\0"
2243
43d9616c
WD
2244 Warning: This method is based on knowledge about the
2245 internal format how the environment is stored by the
2246 U-Boot code. This is NOT an official, exported
2247 interface! Although it is unlikely that this format
7152b1d0 2248 will change soon, there is no guarantee either.
c609719b
WD
2249 You better know what you are doing here.
2250
43d9616c
WD
2251 Note: overly (ab)use of the default environment is
2252 discouraged. Make sure to check other ways to preset
74de7aef 2253 the environment like the "source" command or the
43d9616c 2254 boot command first.
c609719b 2255
5e724ca2
SW
2256 CONFIG_ENV_VARS_UBOOT_CONFIG
2257
2258 Define this in order to add variables describing the
2259 U-Boot build configuration to the default environment.
2260 These will be named arch, cpu, board, vendor, and soc.
2261
2262 Enabling this option will cause the following to be defined:
2263
2264 - CONFIG_SYS_ARCH
2265 - CONFIG_SYS_CPU
2266 - CONFIG_SYS_BOARD
2267 - CONFIG_SYS_VENDOR
2268 - CONFIG_SYS_SOC
2269
7e27f89f
TR
2270 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
2271
2272 Define this in order to add variables describing certain
2273 run-time determined information about the hardware to the
2274 environment. These will be named board_name, board_rev.
2275
06fd8538
SG
2276 CONFIG_DELAY_ENVIRONMENT
2277
2278 Normally the environment is loaded when the board is
b445bbb4 2279 initialised so that it is available to U-Boot. This inhibits
06fd8538
SG
2280 that so that the environment is not available until
2281 explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
2282 this is instead controlled by the value of
2283 /config/load-environment.
2284
f61ec45e 2285- Serial Flash support
00fd59dd 2286 Usage requires an initial 'sf probe' to define the serial
f61ec45e
EN
2287 flash parameters, followed by read/write/erase/update
2288 commands.
2289
2290 The following defaults may be provided by the platform
2291 to handle the common case when only a single serial
2292 flash is present on the system.
2293
2294 CONFIG_SF_DEFAULT_BUS Bus identifier
2295 CONFIG_SF_DEFAULT_CS Chip-select
2296 CONFIG_SF_DEFAULT_MODE (see include/spi.h)
2297 CONFIG_SF_DEFAULT_SPEED in Hz
2298
3f85ce27 2299
ecb0ccd9
WD
2300- TFTP Fixed UDP Port:
2301 CONFIG_TFTP_PORT
2302
28cb9375 2303 If this is defined, the environment variable tftpsrcp
ecb0ccd9 2304 is used to supply the TFTP UDP source port value.
28cb9375 2305 If tftpsrcp isn't defined, the normal pseudo-random port
ecb0ccd9
WD
2306 number generator is used.
2307
28cb9375
WD
2308 Also, the environment variable tftpdstp is used to supply
2309 the TFTP UDP destination port value. If tftpdstp isn't
2310 defined, the normal port 69 is used.
2311
2312 The purpose for tftpsrcp is to allow a TFTP server to
ecb0ccd9
WD
2313 blindly start the TFTP transfer using the pre-configured
2314 target IP address and UDP port. This has the effect of
2315 "punching through" the (Windows XP) firewall, allowing
2316 the remainder of the TFTP transfer to proceed normally.
2317 A better solution is to properly configure the firewall,
2318 but sometimes that is not allowed.
2319
9e50c406 2320- bootcount support:
9e50c406
HS
2321 CONFIG_AT91SAM9XE
2322 enable special bootcounter support on at91sam9xe based boards.
9e50c406
HS
2323 CONFIG_SOC_DA8XX
2324 enable special bootcounter support on da850 based boards.
2325 CONFIG_BOOTCOUNT_RAM
2326 enable support for the bootcounter in RAM
2327 CONFIG_BOOTCOUNT_I2C
2328 enable support for the bootcounter on an i2c (like RTC) device.
2329 CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
2330 CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
2331 the bootcounter.
2332 CONFIG_BOOTCOUNT_ALEN = address len
f31dac4e
IR
2333 CONFIG_BOOTCOUNT_EXT
2334 enable support for the bootcounter in EXT filesystem
2335 CONFIG_SYS_BOOTCOUNT_ADDR = RAM address used for read
2336 and write.
2337 CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE = interface
2338 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART = device and part
2339 CONFIG_SYS_BOOTCOUNT_EXT_NAME = filename
19c402af 2340
a8c7c708 2341- Show boot progress:
c609719b
WD
2342 CONFIG_SHOW_BOOT_PROGRESS
2343
43d9616c
WD
2344 Defining this option allows to add some board-
2345 specific code (calling a user-provided function
2346 "show_boot_progress(int)") that enables you to show
2347 the system's boot progress on some display (for
2348 example, some LED's) on your board. At the moment,
2349 the following checkpoints are implemented:
c609719b 2350
94fd1316 2351
1372cce2
MB
2352Legacy uImage format:
2353
c609719b
WD
2354 Arg Where When
2355 1 common/cmd_bootm.c before attempting to boot an image
ba56f625 2356 -1 common/cmd_bootm.c Image header has bad magic number
c609719b 2357 2 common/cmd_bootm.c Image header has correct magic number
ba56f625 2358 -2 common/cmd_bootm.c Image header has bad checksum
c609719b 2359 3 common/cmd_bootm.c Image header has correct checksum
ba56f625 2360 -3 common/cmd_bootm.c Image data has bad checksum
c609719b
WD
2361 4 common/cmd_bootm.c Image data has correct checksum
2362 -4 common/cmd_bootm.c Image is for unsupported architecture
2363 5 common/cmd_bootm.c Architecture check OK
1372cce2 2364 -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi)
c609719b
WD
2365 6 common/cmd_bootm.c Image Type check OK
2366 -6 common/cmd_bootm.c gunzip uncompression error
2367 -7 common/cmd_bootm.c Unimplemented compression type
2368 7 common/cmd_bootm.c Uncompression OK
1372cce2 2369 8 common/cmd_bootm.c No uncompress/copy overwrite error
c609719b 2370 -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX)
1372cce2
MB
2371
2372 9 common/image.c Start initial ramdisk verification
2373 -10 common/image.c Ramdisk header has bad magic number
2374 -11 common/image.c Ramdisk header has bad checksum
2375 10 common/image.c Ramdisk header is OK
2376 -12 common/image.c Ramdisk data has bad checksum
2377 11 common/image.c Ramdisk data has correct checksum
2378 12 common/image.c Ramdisk verification complete, start loading
11ccc33f 2379 -13 common/image.c Wrong Image Type (not PPC Linux ramdisk)
1372cce2
MB
2380 13 common/image.c Start multifile image verification
2381 14 common/image.c No initial ramdisk, no multifile, continue.
2382
c0f40859 2383 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
c609719b 2384
a47a12be 2385 -30 arch/powerpc/lib/board.c Fatal error, hang the system
11dadd54
WD
2386 -31 post/post.c POST test failed, detected by post_output_backlog()
2387 -32 post/post.c POST test failed, detected by post_run_single()
63e73c9a 2388
566a494f
HS
2389 34 common/cmd_doc.c before loading a Image from a DOC device
2390 -35 common/cmd_doc.c Bad usage of "doc" command
2391 35 common/cmd_doc.c correct usage of "doc" command
2392 -36 common/cmd_doc.c No boot device
2393 36 common/cmd_doc.c correct boot device
2394 -37 common/cmd_doc.c Unknown Chip ID on boot device
2395 37 common/cmd_doc.c correct chip ID found, device available
2396 -38 common/cmd_doc.c Read Error on boot device
2397 38 common/cmd_doc.c reading Image header from DOC device OK
2398 -39 common/cmd_doc.c Image header has bad magic number
2399 39 common/cmd_doc.c Image header has correct magic number
2400 -40 common/cmd_doc.c Error reading Image from DOC device
2401 40 common/cmd_doc.c Image header has correct magic number
2402 41 common/cmd_ide.c before loading a Image from a IDE device
2403 -42 common/cmd_ide.c Bad usage of "ide" command
2404 42 common/cmd_ide.c correct usage of "ide" command
2405 -43 common/cmd_ide.c No boot device
2406 43 common/cmd_ide.c boot device found
2407 -44 common/cmd_ide.c Device not available
2408 44 common/cmd_ide.c Device available
2409 -45 common/cmd_ide.c wrong partition selected
2410 45 common/cmd_ide.c partition selected
2411 -46 common/cmd_ide.c Unknown partition table
2412 46 common/cmd_ide.c valid partition table found
2413 -47 common/cmd_ide.c Invalid partition type
2414 47 common/cmd_ide.c correct partition type
2415 -48 common/cmd_ide.c Error reading Image Header on boot device
2416 48 common/cmd_ide.c reading Image Header from IDE device OK
2417 -49 common/cmd_ide.c Image header has bad magic number
2418 49 common/cmd_ide.c Image header has correct magic number
2419 -50 common/cmd_ide.c Image header has bad checksum
2420 50 common/cmd_ide.c Image header has correct checksum
2421 -51 common/cmd_ide.c Error reading Image from IDE device
2422 51 common/cmd_ide.c reading Image from IDE device OK
2423 52 common/cmd_nand.c before loading a Image from a NAND device
2424 -53 common/cmd_nand.c Bad usage of "nand" command
2425 53 common/cmd_nand.c correct usage of "nand" command
2426 -54 common/cmd_nand.c No boot device
2427 54 common/cmd_nand.c boot device found
2428 -55 common/cmd_nand.c Unknown Chip ID on boot device
2429 55 common/cmd_nand.c correct chip ID found, device available
2430 -56 common/cmd_nand.c Error reading Image Header on boot device
2431 56 common/cmd_nand.c reading Image Header from NAND device OK
2432 -57 common/cmd_nand.c Image header has bad magic number
2433 57 common/cmd_nand.c Image header has correct magic number
2434 -58 common/cmd_nand.c Error reading Image from NAND device
2435 58 common/cmd_nand.c reading Image from NAND device OK
2436
2437 -60 common/env_common.c Environment has a bad CRC, using default
2438
11ccc33f 2439 64 net/eth.c starting with Ethernet configuration.
566a494f
HS
2440 -64 net/eth.c no Ethernet found.
2441 65 net/eth.c Ethernet found.
2442
2443 -80 common/cmd_net.c usage wrong
bc0571fc
JH
2444 80 common/cmd_net.c before calling net_loop()
2445 -81 common/cmd_net.c some error in net_loop() occurred
2446 81 common/cmd_net.c net_loop() back without error
566a494f
HS
2447 -82 common/cmd_net.c size == 0 (File with size 0 loaded)
2448 82 common/cmd_net.c trying automatic boot
74de7aef
WD
2449 83 common/cmd_net.c running "source" command
2450 -83 common/cmd_net.c some error in automatic boot or "source" command
566a494f 2451 84 common/cmd_net.c end without errors
c609719b 2452
1372cce2
MB
2453FIT uImage format:
2454
2455 Arg Where When
2456 100 common/cmd_bootm.c Kernel FIT Image has correct format
2457 -100 common/cmd_bootm.c Kernel FIT Image has incorrect format
2458 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration
2459 -101 common/cmd_bootm.c Can't get configuration for kernel subimage
2460 102 common/cmd_bootm.c Kernel unit name specified
2461 -103 common/cmd_bootm.c Can't get kernel subimage node offset
f773bea8 2462 103 common/cmd_bootm.c Found configuration node
1372cce2
MB
2463 104 common/cmd_bootm.c Got kernel subimage node offset
2464 -104 common/cmd_bootm.c Kernel subimage hash verification failed
2465 105 common/cmd_bootm.c Kernel subimage hash verification OK
2466 -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture
2467 106 common/cmd_bootm.c Architecture check OK
11ccc33f
MZ
2468 -106 common/cmd_bootm.c Kernel subimage has wrong type
2469 107 common/cmd_bootm.c Kernel subimage type OK
1372cce2
MB
2470 -107 common/cmd_bootm.c Can't get kernel subimage data/size
2471 108 common/cmd_bootm.c Got kernel subimage data/size
2472 -108 common/cmd_bootm.c Wrong image type (not legacy, FIT)
2473 -109 common/cmd_bootm.c Can't get kernel subimage type
2474 -110 common/cmd_bootm.c Can't get kernel subimage comp
2475 -111 common/cmd_bootm.c Can't get kernel subimage os
2476 -112 common/cmd_bootm.c Can't get kernel subimage load address
2477 -113 common/cmd_bootm.c Image uncompress/copy overwrite error
2478
2479 120 common/image.c Start initial ramdisk verification
2480 -120 common/image.c Ramdisk FIT image has incorrect format
2481 121 common/image.c Ramdisk FIT image has correct format
11ccc33f 2482 122 common/image.c No ramdisk subimage unit name, using configuration
1372cce2
MB
2483 -122 common/image.c Can't get configuration for ramdisk subimage
2484 123 common/image.c Ramdisk unit name specified
2485 -124 common/image.c Can't get ramdisk subimage node offset
2486 125 common/image.c Got ramdisk subimage node offset
2487 -125 common/image.c Ramdisk subimage hash verification failed
2488 126 common/image.c Ramdisk subimage hash verification OK
2489 -126 common/image.c Ramdisk subimage for unsupported architecture
2490 127 common/image.c Architecture check OK
2491 -127 common/image.c Can't get ramdisk subimage data/size
2492 128 common/image.c Got ramdisk subimage data/size
2493 129 common/image.c Can't get ramdisk load address
2494 -129 common/image.c Got ramdisk load address
2495
11ccc33f 2496 -130 common/cmd_doc.c Incorrect FIT image format
1372cce2
MB
2497 131 common/cmd_doc.c FIT image format OK
2498
11ccc33f 2499 -140 common/cmd_ide.c Incorrect FIT image format
1372cce2
MB
2500 141 common/cmd_ide.c FIT image format OK
2501
11ccc33f 2502 -150 common/cmd_nand.c Incorrect FIT image format
1372cce2
MB
2503 151 common/cmd_nand.c FIT image format OK
2504
21d29f7f
HS
2505- legacy image format:
2506 CONFIG_IMAGE_FORMAT_LEGACY
2507 enables the legacy image format support in U-Boot.
2508
2509 Default:
2510 enabled if CONFIG_FIT_SIGNATURE is not defined.
2511
2512 CONFIG_DISABLE_IMAGE_LEGACY
2513 disable the legacy image format
2514
2515 This define is introduced, as the legacy image format is
2516 enabled per default for backward compatibility.
2517
4cf2609b
WD
2518- Standalone program support:
2519 CONFIG_STANDALONE_LOAD_ADDR
2520
6feff899
WD
2521 This option defines a board specific value for the
2522 address where standalone program gets loaded, thus
2523 overwriting the architecture dependent default
4cf2609b
WD
2524 settings.
2525
2526- Frame Buffer Address:
2527 CONFIG_FB_ADDR
2528
2529 Define CONFIG_FB_ADDR if you want to use specific
44a53b57
WD
2530 address for frame buffer. This is typically the case
2531 when using a graphics controller has separate video
2532 memory. U-Boot will then place the frame buffer at
2533 the given address instead of dynamically reserving it
2534 in system RAM by calling lcd_setmem(), which grabs
2535 the memory for the frame buffer depending on the
2536 configured panel size.
4cf2609b
WD
2537
2538 Please see board_init_f function.
2539
cccfc2ab
DZ
2540- Automatic software updates via TFTP server
2541 CONFIG_UPDATE_TFTP
2542 CONFIG_UPDATE_TFTP_CNT_MAX
2543 CONFIG_UPDATE_TFTP_MSEC_MAX
2544
2545 These options enable and control the auto-update feature;
2546 for a more detailed description refer to doc/README.update.
2547
2548- MTD Support (mtdparts command, UBI support)
2549 CONFIG_MTD_DEVICE
2550
2551 Adds the MTD device infrastructure from the Linux kernel.
2552 Needed for mtdparts command support.
2553
2554 CONFIG_MTD_PARTITIONS
2555
2556 Adds the MTD partitioning infrastructure from the Linux
2557 kernel. Needed for UBI support.
2558
70c219cd 2559- UBI support
147162da
JH
2560 CONFIG_UBI_SILENCE_MSG
2561
2562 Make the verbose messages from UBI stop printing. This leaves
2563 warnings and errors enabled.
2564
ff94bc40
HS
2565
2566 CONFIG_MTD_UBI_WL_THRESHOLD
2567 This parameter defines the maximum difference between the highest
2568 erase counter value and the lowest erase counter value of eraseblocks
2569 of UBI devices. When this threshold is exceeded, UBI starts performing
2570 wear leveling by means of moving data from eraseblock with low erase
2571 counter to eraseblocks with high erase counter.
2572
2573 The default value should be OK for SLC NAND flashes, NOR flashes and
2574 other flashes which have eraseblock life-cycle 100000 or more.
2575 However, in case of MLC NAND flashes which typically have eraseblock
2576 life-cycle less than 10000, the threshold should be lessened (e.g.,
2577 to 128 or 256, although it does not have to be power of 2).
2578
2579 default: 4096
c654b517 2580
ff94bc40
HS
2581 CONFIG_MTD_UBI_BEB_LIMIT
2582 This option specifies the maximum bad physical eraseblocks UBI
2583 expects on the MTD device (per 1024 eraseblocks). If the
2584 underlying flash does not admit of bad eraseblocks (e.g. NOR
2585 flash), this value is ignored.
2586
2587 NAND datasheets often specify the minimum and maximum NVM
2588 (Number of Valid Blocks) for the flashes' endurance lifetime.
2589 The maximum expected bad eraseblocks per 1024 eraseblocks
2590 then can be calculated as "1024 * (1 - MinNVB / MaxNVB)",
2591 which gives 20 for most NANDs (MaxNVB is basically the total
2592 count of eraseblocks on the chip).
2593
2594 To put it differently, if this value is 20, UBI will try to
2595 reserve about 1.9% of physical eraseblocks for bad blocks
2596 handling. And that will be 1.9% of eraseblocks on the entire
2597 NAND chip, not just the MTD partition UBI attaches. This means
2598 that if you have, say, a NAND flash chip admits maximum 40 bad
2599 eraseblocks, and it is split on two MTD partitions of the same
2600 size, UBI will reserve 40 eraseblocks when attaching a
2601 partition.
2602
2603 default: 20
2604
2605 CONFIG_MTD_UBI_FASTMAP
2606 Fastmap is a mechanism which allows attaching an UBI device
2607 in nearly constant time. Instead of scanning the whole MTD device it
2608 only has to locate a checkpoint (called fastmap) on the device.
2609 The on-flash fastmap contains all information needed to attach
2610 the device. Using fastmap makes only sense on large devices where
2611 attaching by scanning takes long. UBI will not automatically install
2612 a fastmap on old images, but you can set the UBI parameter
2613 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT to 1 if you want so. Please note
2614 that fastmap-enabled images are still usable with UBI implementations
2615 without fastmap support. On typical flash devices the whole fastmap
2616 fits into one PEB. UBI will reserve PEBs to hold two fastmaps.
2617
2618 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT
2619 Set this parameter to enable fastmap automatically on images
2620 without a fastmap.
2621 default: 0
2622
0195a7bb
HS
2623 CONFIG_MTD_UBI_FM_DEBUG
2624 Enable UBI fastmap debug
2625 default: 0
2626
70c219cd 2627- UBIFS support
147162da
JH
2628 CONFIG_UBIFS_SILENCE_MSG
2629
2630 Make the verbose messages from UBIFS stop printing. This leaves
2631 warnings and errors enabled.
2632
6a11cf48 2633- SPL framework
04e5ae79
WD
2634 CONFIG_SPL
2635 Enable building of SPL globally.
6a11cf48 2636
95579793
TR
2637 CONFIG_SPL_LDSCRIPT
2638 LDSCRIPT for linking the SPL binary.
2639
6ebc3461
AA
2640 CONFIG_SPL_MAX_FOOTPRINT
2641 Maximum size in memory allocated to the SPL, BSS included.
2642 When defined, the linker checks that the actual memory
2643 used by SPL from _start to __bss_end does not exceed it.
8960af8b 2644 CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
6ebc3461
AA
2645 must not be both defined at the same time.
2646
95579793 2647 CONFIG_SPL_MAX_SIZE
6ebc3461
AA
2648 Maximum size of the SPL image (text, data, rodata, and
2649 linker lists sections), BSS excluded.
2650 When defined, the linker checks that the actual size does
2651 not exceed it.
95579793 2652
04e5ae79
WD
2653 CONFIG_SPL_TEXT_BASE
2654 TEXT_BASE for linking the SPL binary.
6a11cf48 2655
94a45bb1
SW
2656 CONFIG_SPL_RELOC_TEXT_BASE
2657 Address to relocate to. If unspecified, this is equal to
2658 CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
2659
95579793
TR
2660 CONFIG_SPL_BSS_START_ADDR
2661 Link address for the BSS within the SPL binary.
2662
2663 CONFIG_SPL_BSS_MAX_SIZE
6ebc3461
AA
2664 Maximum size in memory allocated to the SPL BSS.
2665 When defined, the linker checks that the actual memory used
2666 by SPL from __bss_start to __bss_end does not exceed it.
8960af8b 2667 CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
6ebc3461 2668 must not be both defined at the same time.
95579793
TR
2669
2670 CONFIG_SPL_STACK
2671 Adress of the start of the stack SPL will use
2672
8c80eb3b
AA
2673 CONFIG_SPL_PANIC_ON_RAW_IMAGE
2674 When defined, SPL will panic() if the image it has
2675 loaded does not have a signature.
2676 Defining this is useful when code which loads images
2677 in SPL cannot guarantee that absolutely all read errors
2678 will be caught.
2679 An example is the LPC32XX MLC NAND driver, which will
2680 consider that a completely unreadable NAND block is bad,
2681 and thus should be skipped silently.
2682
94a45bb1
SW
2683 CONFIG_SPL_RELOC_STACK
2684 Adress of the start of the stack SPL will use after
2685 relocation. If unspecified, this is equal to
2686 CONFIG_SPL_STACK.
2687
95579793
TR
2688 CONFIG_SYS_SPL_MALLOC_START
2689 Starting address of the malloc pool used in SPL.
9ac4fc82
FE
2690 When this option is set the full malloc is used in SPL and
2691 it is set up by spl_init() and before that, the simple malloc()
2692 can be used if CONFIG_SYS_MALLOC_F is defined.
95579793
TR
2693
2694 CONFIG_SYS_SPL_MALLOC_SIZE
2695 The size of the malloc pool used in SPL.
6a11cf48 2696
9607faf2
TR
2697 CONFIG_SPL_OS_BOOT
2698 Enable booting directly to an OS from SPL.
2699 See also: doc/README.falcon
2700
861a86f4
TR
2701 CONFIG_SPL_DISPLAY_PRINT
2702 For ARM, enable an optional function to print more information
2703 about the running system.
2704
4b919725
SW
2705 CONFIG_SPL_INIT_MINIMAL
2706 Arch init code should be built for a very small image
2707
b97300b6
PK
2708 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
2709 Partition on the MMC to load U-Boot from when the MMC is being
2710 used in raw mode
2711
2b75b0ad
PK
2712 CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
2713 Sector to load kernel uImage from when MMC is being
2714 used in raw mode (for Falcon mode)
2715
2716 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
2717 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
2718 Sector and number of sectors to load kernel argument
2719 parameters from when MMC is being used in raw mode
2720 (for falcon mode)
2721
e2ccdf89
PK
2722 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
2723 Partition on the MMC to load U-Boot from when the MMC is being
2724 used in fs mode
2725
fae81c72
GG
2726 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
2727 Filename to read to load U-Boot when reading from filesystem
2728
2729 CONFIG_SPL_FS_LOAD_KERNEL_NAME
7ad2cc79 2730 Filename to read to load kernel uImage when reading
fae81c72 2731 from filesystem (for Falcon mode)
7ad2cc79 2732
fae81c72 2733 CONFIG_SPL_FS_LOAD_ARGS_NAME
7ad2cc79 2734 Filename to read to load kernel argument parameters
fae81c72 2735 when reading from filesystem (for Falcon mode)
7ad2cc79 2736
06f60ae3
SW
2737 CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
2738 Set this for NAND SPL on PPC mpc83xx targets, so that
2739 start.S waits for the rest of the SPL to load before
2740 continuing (the hardware starts execution after just
2741 loading the first page rather than the full 4K).
2742
651fcf60
PK
2743 CONFIG_SPL_SKIP_RELOCATE
2744 Avoid SPL relocation
2745
6f2f01b9
SW
2746 CONFIG_SPL_NAND_BASE
2747 Include nand_base.c in the SPL. Requires
2748 CONFIG_SPL_NAND_DRIVERS.
2749
2750 CONFIG_SPL_NAND_DRIVERS
2751 SPL uses normal NAND drivers, not minimal drivers.
2752
2753 CONFIG_SPL_NAND_ECC
2754 Include standard software ECC in the SPL
2755
95579793 2756 CONFIG_SPL_NAND_SIMPLE
7d4b7955
SW
2757 Support for NAND boot using simple NAND drivers that
2758 expose the cmd_ctrl() interface.
95579793 2759
6f4e7d3c
TG
2760 CONFIG_SPL_UBI
2761 Support for a lightweight UBI (fastmap) scanner and
2762 loader
2763
0c3117b1
HS
2764 CONFIG_SPL_NAND_RAW_ONLY
2765 Support to boot only raw u-boot.bin images. Use this only
2766 if you need to save space.
2767
7c8eea59
YZ
2768 CONFIG_SPL_COMMON_INIT_DDR
2769 Set for common ddr init with serial presence detect in
2770 SPL binary.
2771
95579793
TR
2772 CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
2773 CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
2774 CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
2775 CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
2776 CONFIG_SYS_NAND_ECCBYTES
2777 Defines the size and behavior of the NAND that SPL uses
7d4b7955 2778 to read U-Boot
95579793 2779
fbe76ae4
PK
2780 CONFIG_SPL_NAND_BOOT
2781 Add support NAND boot
2782
95579793 2783 CONFIG_SYS_NAND_U_BOOT_OFFS
7d4b7955
SW
2784 Location in NAND to read U-Boot from
2785
2786 CONFIG_SYS_NAND_U_BOOT_DST
2787 Location in memory to load U-Boot to
2788
2789 CONFIG_SYS_NAND_U_BOOT_SIZE
2790 Size of image to load
95579793
TR
2791
2792 CONFIG_SYS_NAND_U_BOOT_START
7d4b7955 2793 Entry point in loaded image to jump to
95579793
TR
2794
2795 CONFIG_SYS_NAND_HW_ECC_OOBFIRST
2796 Define this if you need to first read the OOB and then the
b445bbb4 2797 data. This is used, for example, on davinci platforms.
95579793 2798
c57b953d
PM
2799 CONFIG_SPL_RAM_DEVICE
2800 Support for running image already present in ram, in SPL binary
6a11cf48 2801
74752baa 2802 CONFIG_SPL_PAD_TO
6113d3f2
BT
2803 Image offset to which the SPL should be padded before appending
2804 the SPL payload. By default, this is defined as
2805 CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
2806 CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
2807 payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
74752baa 2808
ca2fca22
SW
2809 CONFIG_SPL_TARGET
2810 Final target image containing SPL and payload. Some SPLs
2811 use an arch-specific makefile fragment instead, for
2812 example if more than one image needs to be produced.
2813
87ebee39
SG
2814 CONFIG_FIT_SPL_PRINT
2815 Printing information about a FIT image adds quite a bit of
2816 code to SPL. So this is normally disabled in SPL. Use this
2817 option to re-enable it. This will affect the output of the
2818 bootm command when booting a FIT image.
2819
3aa29de0
YZ
2820- TPL framework
2821 CONFIG_TPL
2822 Enable building of TPL globally.
2823
2824 CONFIG_TPL_PAD_TO
2825 Image offset to which the TPL should be padded before appending
2826 the TPL payload. By default, this is defined as
93e14596
WD
2827 CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
2828 CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
2829 payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
3aa29de0 2830
a8c7c708
WD
2831- Interrupt support (PPC):
2832
d4ca31c4
WD
2833 There are common interrupt_init() and timer_interrupt()
2834 for all PPC archs. interrupt_init() calls interrupt_init_cpu()
11ccc33f 2835 for CPU specific initialization. interrupt_init_cpu()
d4ca31c4 2836 should set decrementer_count to appropriate value. If
11ccc33f 2837 CPU resets decrementer automatically after interrupt
d4ca31c4 2838 (ppc4xx) it should set decrementer_count to zero.
11ccc33f 2839 timer_interrupt() calls timer_interrupt_cpu() for CPU
d4ca31c4
WD
2840 specific handling. If board has watchdog / status_led
2841 / other_activity_monitor it works automatically from
2842 general timer_interrupt().
a8c7c708 2843
c609719b 2844
9660e442
HR
2845Board initialization settings:
2846------------------------------
2847
2848During Initialization u-boot calls a number of board specific functions
2849to allow the preparation of board specific prerequisites, e.g. pin setup
2850before drivers are initialized. To enable these callbacks the
2851following configuration macros have to be defined. Currently this is
2852architecture specific, so please check arch/your_architecture/lib/board.c
2853typically in board_init_f() and board_init_r().
2854
2855- CONFIG_BOARD_EARLY_INIT_F: Call board_early_init_f()
2856- CONFIG_BOARD_EARLY_INIT_R: Call board_early_init_r()
2857- CONFIG_BOARD_LATE_INIT: Call board_late_init()
2858- CONFIG_BOARD_POSTCLK_INIT: Call board_postclk_init()
c609719b 2859
c609719b
WD
2860Configuration Settings:
2861-----------------------
2862
4d1fd7f1
YS
2863- CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit.
2864 Optionally it can be defined to support 64-bit memory commands.
2865
6d0f6bcf 2866- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
c609719b
WD
2867 undefine this when you're short of memory.
2868
2fb2604d
PT
2869- CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
2870 width of the commands listed in the 'help' command output.
2871
6d0f6bcf 2872- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
c609719b
WD
2873 prompt for user input.
2874
6d0f6bcf 2875- CONFIG_SYS_CBSIZE: Buffer size for input from the Console
c609719b 2876
6d0f6bcf 2877- CONFIG_SYS_PBSIZE: Buffer size for Console output
c609719b 2878
6d0f6bcf 2879- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands
c609719b 2880
6d0f6bcf 2881- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
c609719b
WD
2882 the application (usually a Linux kernel) when it is
2883 booted
2884
6d0f6bcf 2885- CONFIG_SYS_BAUDRATE_TABLE:
c609719b
WD
2886 List of legal baudrate settings for this board.
2887
6d0f6bcf 2888- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
c609719b
WD
2889 Begin and End addresses of the area used by the
2890 simple memory test.
2891
6d0f6bcf 2892- CONFIG_SYS_ALT_MEMTEST:
8bde7f77 2893 Enable an alternate, more extensive memory test.
c609719b 2894
6d0f6bcf 2895- CONFIG_SYS_MEMTEST_SCRATCH:
5f535fe1
WD
2896 Scratch address used by the alternate memory test
2897 You only need to set this if address zero isn't writeable
2898
e8149522 2899- CONFIG_SYS_MEM_RESERVE_SECURE
e61a7534 2900 Only implemented for ARMv8 for now.
e8149522
YS
2901 If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
2902 is substracted from total RAM and won't be reported to OS.
2903 This memory can be used as secure memory. A variable
e61a7534 2904 gd->arch.secure_ram is used to track the location. In systems
e8149522
YS
2905 the RAM base is not zero, or RAM is divided into banks,
2906 this variable needs to be recalcuated to get the address.
2907
aabd7ddb 2908- CONFIG_SYS_MEM_TOP_HIDE:
6d0f6bcf 2909 If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
14f73ca6 2910 this specified memory area will get subtracted from the top
11ccc33f 2911 (end) of RAM and won't get "touched" at all by U-Boot. By
14f73ca6
SR
2912 fixing up gd->ram_size the Linux kernel should gets passed
2913 the now "corrected" memory size and won't touch it either.
2914 This should work for arch/ppc and arch/powerpc. Only Linux
5e12e75d 2915 board ports in arch/powerpc with bootwrapper support that
14f73ca6 2916 recalculate the memory size from the SDRAM controller setup
5e12e75d 2917 will have to get fixed in Linux additionally.
14f73ca6
SR
2918
2919 This option can be used as a workaround for the 440EPx/GRx
2920 CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
2921 be touched.
2922
2923 WARNING: Please make sure that this value is a multiple of
2924 the Linux page size (normally 4k). If this is not the case,
2925 then the end address of the Linux memory will be located at a
2926 non page size aligned address and this could cause major
2927 problems.
2928
6d0f6bcf 2929- CONFIG_SYS_LOADS_BAUD_CHANGE:
c609719b
WD
2930 Enable temporary baudrate change while serial download
2931
6d0f6bcf 2932- CONFIG_SYS_SDRAM_BASE:
c609719b
WD
2933 Physical start address of SDRAM. _Must_ be 0 here.
2934
6d0f6bcf 2935- CONFIG_SYS_FLASH_BASE:
c609719b
WD
2936 Physical start address of Flash memory.
2937
6d0f6bcf 2938- CONFIG_SYS_MONITOR_BASE:
c609719b
WD
2939 Physical start address of boot monitor code (set by
2940 make config files to be same as the text base address
14d0a02a 2941 (CONFIG_SYS_TEXT_BASE) used when linking) - same as
6d0f6bcf 2942 CONFIG_SYS_FLASH_BASE when booting from flash.
c609719b 2943
6d0f6bcf 2944- CONFIG_SYS_MONITOR_LEN:
8bde7f77
WD
2945 Size of memory reserved for monitor code, used to
2946 determine _at_compile_time_ (!) if the environment is
2947 embedded within the U-Boot image, or in a separate
2948 flash sector.
c609719b 2949
6d0f6bcf 2950- CONFIG_SYS_MALLOC_LEN:
c609719b
WD
2951 Size of DRAM reserved for malloc() use.
2952
d59476b6
SG
2953- CONFIG_SYS_MALLOC_F_LEN
2954 Size of the malloc() pool for use before relocation. If
2955 this is defined, then a very simple malloc() implementation
2956 will become available before relocation. The address is just
2957 below the global data, and the stack is moved down to make
2958 space.
2959
2960 This feature allocates regions with increasing addresses
2961 within the region. calloc() is supported, but realloc()
2962 is not available. free() is supported but does nothing.
b445bbb4 2963 The memory will be freed (or in fact just forgotten) when
d59476b6
SG
2964 U-Boot relocates itself.
2965
38687ae6
SG
2966- CONFIG_SYS_MALLOC_SIMPLE
2967 Provides a simple and small malloc() and calloc() for those
2968 boards which do not use the full malloc in SPL (which is
2969 enabled with CONFIG_SYS_SPL_MALLOC_START).
2970
1dfdd9ba
TR
2971- CONFIG_SYS_NONCACHED_MEMORY:
2972 Size of non-cached memory area. This area of memory will be
2973 typically located right below the malloc() area and mapped
2974 uncached in the MMU. This is useful for drivers that would
2975 otherwise require a lot of explicit cache maintenance. For
2976 some drivers it's also impossible to properly maintain the
2977 cache. For example if the regions that need to be flushed
2978 are not a multiple of the cache-line size, *and* padding
2979 cannot be allocated between the regions to align them (i.e.
2980 if the HW requires a contiguous array of regions, and the
2981 size of each region is not cache-aligned), then a flush of
2982 one region may result in overwriting data that hardware has
2983 written to another region in the same cache-line. This can
2984 happen for example in network drivers where descriptors for
2985 buffers are typically smaller than the CPU cache-line (e.g.
2986 16 bytes vs. 32 or 64 bytes).
2987
2988 Non-cached memory is only supported on 32-bit ARM at present.
2989
6d0f6bcf 2990- CONFIG_SYS_BOOTM_LEN:
15940c9a
SR
2991 Normally compressed uImages are limited to an
2992 uncompressed size of 8 MBytes. If this is not enough,
6d0f6bcf 2993 you can define CONFIG_SYS_BOOTM_LEN in your board config file
15940c9a
SR
2994 to adjust this setting to your needs.
2995
6d0f6bcf 2996- CONFIG_SYS_BOOTMAPSZ:
c609719b
WD
2997 Maximum size of memory mapped by the startup code of
2998 the Linux kernel; all data that must be processed by
7d721e34
BS
2999 the Linux kernel (bd_info, boot arguments, FDT blob if
3000 used) must be put below this limit, unless "bootm_low"
1bce2aeb 3001 environment variable is defined and non-zero. In such case
7d721e34 3002 all data for the Linux kernel must be between "bootm_low"
c0f40859 3003 and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment
c3624e6e
GL
3004 variable "bootm_mapsize" will override the value of
3005 CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
3006 then the value in "bootm_size" will be used instead.
c609719b 3007
fca43cc8
JR
3008- CONFIG_SYS_BOOT_RAMDISK_HIGH:
3009 Enable initrd_high functionality. If defined then the
3010 initrd_high feature is enabled and the bootm ramdisk subcommand
3011 is enabled.
3012
3013- CONFIG_SYS_BOOT_GET_CMDLINE:
3014 Enables allocating and saving kernel cmdline in space between
3015 "bootm_low" and "bootm_low" + BOOTMAPSZ.
3016
3017- CONFIG_SYS_BOOT_GET_KBD:
3018 Enables allocating and saving a kernel copy of the bd_info in
3019 space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
3020
6d0f6bcf 3021- CONFIG_SYS_MAX_FLASH_BANKS:
c609719b
WD
3022 Max number of Flash memory banks
3023
6d0f6bcf 3024- CONFIG_SYS_MAX_FLASH_SECT:
c609719b
WD
3025 Max number of sectors on a Flash chip
3026
6d0f6bcf 3027- CONFIG_SYS_FLASH_ERASE_TOUT:
c609719b
WD
3028 Timeout for Flash erase operations (in ms)
3029
6d0f6bcf 3030- CONFIG_SYS_FLASH_WRITE_TOUT:
c609719b
WD
3031 Timeout for Flash write operations (in ms)
3032
6d0f6bcf 3033- CONFIG_SYS_FLASH_LOCK_TOUT
8564acf9
WD
3034 Timeout for Flash set sector lock bit operation (in ms)
3035
6d0f6bcf 3036- CONFIG_SYS_FLASH_UNLOCK_TOUT
8564acf9
WD
3037 Timeout for Flash clear lock bits operation (in ms)
3038
6d0f6bcf 3039- CONFIG_SYS_FLASH_PROTECTION
8564acf9
WD
3040 If defined, hardware flash sectors protection is used
3041 instead of U-Boot software protection.
3042
6d0f6bcf 3043- CONFIG_SYS_DIRECT_FLASH_TFTP:
c609719b
WD
3044
3045 Enable TFTP transfers directly to flash memory;
3046 without this option such a download has to be
3047 performed in two steps: (1) download to RAM, and (2)
3048 copy from RAM to flash.
3049
3050 The two-step approach is usually more reliable, since
3051 you can check if the download worked before you erase
11ccc33f
MZ
3052 the flash, but in some situations (when system RAM is
3053 too limited to allow for a temporary copy of the
c609719b
WD
3054 downloaded image) this option may be very useful.
3055
6d0f6bcf 3056- CONFIG_SYS_FLASH_CFI:
43d9616c 3057 Define if the flash driver uses extra elements in the
5653fc33
WD
3058 common flash structure for storing flash geometry.
3059
00b1883a 3060- CONFIG_FLASH_CFI_DRIVER
5653fc33
WD
3061 This option also enables the building of the cfi_flash driver
3062 in the drivers directory
c609719b 3063
91809ed5
PZ
3064- CONFIG_FLASH_CFI_MTD
3065 This option enables the building of the cfi_mtd driver
3066 in the drivers directory. The driver exports CFI flash
3067 to the MTD layer.
3068
6d0f6bcf 3069- CONFIG_SYS_FLASH_USE_BUFFER_WRITE
96ef831f
GL
3070 Use buffered writes to flash.
3071
3072- CONFIG_FLASH_SPANSION_S29WS_N
3073 s29ws-n MirrorBit flash has non-standard addresses for buffered
3074 write commands.
3075
6d0f6bcf 3076- CONFIG_SYS_FLASH_QUIET_TEST
5568e613
SR
3077 If this option is defined, the common CFI flash doesn't
3078 print it's warning upon not recognized FLASH banks. This
3079 is useful, if some of the configured banks are only
3080 optionally available.
3081
9a042e9c
JVB
3082- CONFIG_FLASH_SHOW_PROGRESS
3083 If defined (must be an integer), print out countdown
3084 digits and dots. Recommended value: 45 (9..1) for 80
3085 column displays, 15 (3..1) for 40 column displays.
3086
352ef3f1
SR
3087- CONFIG_FLASH_VERIFY
3088 If defined, the content of the flash (destination) is compared
3089 against the source after the write operation. An error message
3090 will be printed when the contents are not identical.
3091 Please note that this option is useless in nearly all cases,
3092 since such flash programming errors usually are detected earlier
3093 while unprotecting/erasing/programming. Please only enable
3094 this option if you really know what you are doing.
3095
6d0f6bcf 3096- CONFIG_SYS_RX_ETH_BUFFER:
11ccc33f
MZ
3097 Defines the number of Ethernet receive buffers. On some
3098 Ethernet controllers it is recommended to set this value
53cf9435
SR
3099 to 8 or even higher (EEPRO100 or 405 EMAC), since all
3100 buffers can be full shortly after enabling the interface
11ccc33f 3101 on high Ethernet traffic.
53cf9435
SR
3102 Defaults to 4 if not defined.
3103
ea882baf
WD
3104- CONFIG_ENV_MAX_ENTRIES
3105
071bc923
WD
3106 Maximum number of entries in the hash table that is used
3107 internally to store the environment settings. The default
3108 setting is supposed to be generous and should work in most
3109 cases. This setting can be used to tune behaviour; see
3110 lib/hashtable.c for details.
ea882baf 3111
2598090b
JH
3112- CONFIG_ENV_FLAGS_LIST_DEFAULT
3113- CONFIG_ENV_FLAGS_LIST_STATIC
1bce2aeb 3114 Enable validation of the values given to environment variables when
2598090b
JH
3115 calling env set. Variables can be restricted to only decimal,
3116 hexadecimal, or boolean. If CONFIG_CMD_NET is also defined,
3117 the variables can also be restricted to IP address or MAC address.
3118
3119 The format of the list is:
3120 type_attribute = [s|d|x|b|i|m]
b445bbb4
JM
3121 access_attribute = [a|r|o|c]
3122 attributes = type_attribute[access_attribute]
2598090b
JH
3123 entry = variable_name[:attributes]
3124 list = entry[,list]
3125
3126 The type attributes are:
3127 s - String (default)
3128 d - Decimal
3129 x - Hexadecimal
3130 b - Boolean ([1yYtT|0nNfF])
3131 i - IP address
3132 m - MAC address
3133
267541f7
JH
3134 The access attributes are:
3135 a - Any (default)
3136 r - Read-only
3137 o - Write-once
3138 c - Change-default
3139
2598090b
JH
3140 - CONFIG_ENV_FLAGS_LIST_DEFAULT
3141 Define this to a list (string) to define the ".flags"
b445bbb4 3142 environment variable in the default or embedded environment.
2598090b
JH
3143
3144 - CONFIG_ENV_FLAGS_LIST_STATIC
3145 Define this to a list (string) to define validation that
3146 should be done if an entry is not found in the ".flags"
3147 environment variable. To override a setting in the static
3148 list, simply add an entry for the same variable name to the
3149 ".flags" variable.
3150
bdf1fe4e
JH
3151 If CONFIG_REGEX is defined, the variable_name above is evaluated as a
3152 regular expression. This allows multiple variables to define the same
3153 flags without explicitly listing them for each variable.
3154
267541f7
JH
3155- CONFIG_ENV_ACCESS_IGNORE_FORCE
3156 If defined, don't allow the -f switch to env set override variable
3157 access flags.
3158
0d296cc2
GB
3159- CONFIG_USE_STDINT
3160 If stdint.h is available with your toolchain you can define this
3161 option to enable it. You can provide option 'USE_STDINT=1' when
3162 building U-Boot to enable this.
3163
c609719b
WD
3164The following definitions that deal with the placement and management
3165of environment data (variable area); in general, we support the
3166following configurations:
3167
c3eb3fe4
MF
3168- CONFIG_BUILD_ENVCRC:
3169
3170 Builds up envcrc with the target environment so that external utils
3171 may easily extract it and embed it in final U-Boot images.
3172
c609719b 3173BE CAREFUL! The first access to the environment happens quite early
b445bbb4 3174in U-Boot initialization (when we try to get the setting of for the
11ccc33f 3175console baudrate). You *MUST* have mapped your NVRAM area then, or
c609719b
WD
3176U-Boot will hang.
3177
3178Please note that even with NVRAM we still use a copy of the
3179environment in RAM: we could work on NVRAM directly, but we want to
3180keep settings there always unmodified except somebody uses "saveenv"
3181to save the current settings.
3182
0a85a9e7
LG
3183BE CAREFUL! For some special cases, the local device can not use
3184"saveenv" command. For example, the local device will get the
fc54c7fa
LG
3185environment stored in a remote NOR flash by SRIO or PCIE link,
3186but it can not erase, write this NOR flash by SRIO or PCIE interface.
0a85a9e7 3187
b74ab737
GL
3188- CONFIG_NAND_ENV_DST
3189
3190 Defines address in RAM to which the nand_spl code should copy the
3191 environment. If redundant environment is used, it will be copied to
3192 CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE.
3193
e881cb56 3194Please note that the environment is read-only until the monitor
c609719b 3195has been relocated to RAM and a RAM copy of the environment has been
00caae6d 3196created; also, when using EEPROM you will have to use env_get_f()
c609719b
WD
3197until then to read environment variables.
3198
85ec0bcc
WD
3199The environment is protected by a CRC32 checksum. Before the monitor
3200is relocated into RAM, as a result of a bad CRC you will be working
3201with the compiled-in default environment - *silently*!!! [This is
3202necessary, because the first environment variable we need is the
3203"baudrate" setting for the console - if we have a bad CRC, we don't
3204have any device yet where we could complain.]
c609719b
WD
3205
3206Note: once the monitor has been relocated, then it will complain if
3207the default environment is used; a new CRC is computed as soon as you
85ec0bcc 3208use the "saveenv" command to store a valid environment.
c609719b 3209
6d0f6bcf 3210- CONFIG_SYS_FAULT_ECHO_LINK_DOWN:
42d1f039 3211 Echo the inverted Ethernet link state to the fault LED.
fc3e2165 3212
6d0f6bcf 3213 Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR
fc3e2165
WD
3214 also needs to be defined.
3215
6d0f6bcf 3216- CONFIG_SYS_FAULT_MII_ADDR:
42d1f039 3217 MII address of the PHY to check for the Ethernet link state.
c609719b 3218
f5675aa5
RM
3219- CONFIG_NS16550_MIN_FUNCTIONS:
3220 Define this if you desire to only have use of the NS16550_init
3221 and NS16550_putc functions for the serial driver located at
3222 drivers/serial/ns16550.c. This option is useful for saving
3223 space for already greatly restricted images, including but not
3224 limited to NAND_SPL configurations.
3225
b2b92f53
SG
3226- CONFIG_DISPLAY_BOARDINFO
3227 Display information about the board that U-Boot is running on
3228 when U-Boot starts up. The board function checkboard() is called
3229 to do this.
3230
e2e3e2b1
SG
3231- CONFIG_DISPLAY_BOARDINFO_LATE
3232 Similar to the previous option, but display this information
3233 later, once stdio is running and output goes to the LCD, if
3234 present.
3235
feb85801
SS
3236- CONFIG_BOARD_SIZE_LIMIT:
3237 Maximum size of the U-Boot image. When defined, the
3238 build system checks that the actual size does not
3239 exceed it.
3240
c609719b 3241Low Level (hardware related) configuration options:
dc7c9a1a 3242---------------------------------------------------
c609719b 3243
6d0f6bcf 3244- CONFIG_SYS_CACHELINE_SIZE:
c609719b
WD
3245 Cache Line Size of the CPU.
3246
e46fedfe
TT
3247- CONFIG_SYS_CCSRBAR_DEFAULT:
3248 Default (power-on reset) physical address of CCSR on Freescale
3249 PowerPC SOCs.
3250
3251- CONFIG_SYS_CCSRBAR:
3252 Virtual address of CCSR. On a 32-bit build, this is typically
3253 the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
3254
e46fedfe
TT
3255- CONFIG_SYS_CCSRBAR_PHYS:
3256 Physical address of CCSR. CCSR can be relocated to a new
3257 physical address, if desired. In this case, this macro should
c0f40859 3258 be set to that address. Otherwise, it should be set to the
e46fedfe
TT
3259 same value as CONFIG_SYS_CCSRBAR_DEFAULT. For example, CCSR
3260 is typically relocated on 36-bit builds. It is recommended
3261 that this macro be defined via the _HIGH and _LOW macros:
3262
3263 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
3264 * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
3265
3266- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
4cf2609b
WD
3267 Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically
3268 either 0 (32-bit build) or 0xF (36-bit build). This macro is
e46fedfe
TT
3269 used in assembly code, so it must not contain typecasts or
3270 integer size suffixes (e.g. "ULL").
3271
3272- CONFIG_SYS_CCSRBAR_PHYS_LOW:
3273 Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is
3274 used in assembly code, so it must not contain typecasts or
3275 integer size suffixes (e.g. "ULL").
3276
3277- CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
3278 If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
3279 forced to a value that ensures that CCSR is not relocated.
3280
7f6c2cbc 3281- Floppy Disk Support:
6d0f6bcf 3282 CONFIG_SYS_FDC_DRIVE_NUMBER
7f6c2cbc
WD
3283
3284 the default drive number (default value 0)
3285
6d0f6bcf 3286 CONFIG_SYS_ISA_IO_STRIDE
7f6c2cbc 3287
11ccc33f 3288 defines the spacing between FDC chipset registers
7f6c2cbc
WD
3289 (default value 1)
3290
6d0f6bcf 3291 CONFIG_SYS_ISA_IO_OFFSET
7f6c2cbc 3292
43d9616c
WD
3293 defines the offset of register from address. It
3294 depends on which part of the data bus is connected to
11ccc33f 3295 the FDC chipset. (default value 0)
7f6c2cbc 3296
6d0f6bcf
JCPV
3297 If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
3298 CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
43d9616c 3299 default value.
7f6c2cbc 3300
6d0f6bcf 3301 if CONFIG_SYS_FDC_HW_INIT is defined, then the function
43d9616c
WD
3302 fdc_hw_init() is called at the beginning of the FDC
3303 setup. fdc_hw_init() must be provided by the board
b445bbb4 3304 source code. It is used to make hardware-dependent
43d9616c 3305 initializations.
7f6c2cbc 3306
0abddf82
ML
3307- CONFIG_IDE_AHB:
3308 Most IDE controllers were designed to be connected with PCI
3309 interface. Only few of them were designed for AHB interface.
3310 When software is doing ATA command and data transfer to
3311 IDE devices through IDE-AHB controller, some additional
3312 registers accessing to these kind of IDE-AHB controller
b445bbb4 3313 is required.
0abddf82 3314
6d0f6bcf 3315- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
efe2a4d5 3316 DO NOT CHANGE unless you know exactly what you're
907208c4 3317 doing! (11-4) [MPC8xx systems only]
c609719b 3318
6d0f6bcf 3319- CONFIG_SYS_INIT_RAM_ADDR:
c609719b 3320
7152b1d0 3321 Start address of memory area that can be used for
c609719b
WD
3322 initial data and stack; please note that this must be
3323 writable memory that is working WITHOUT special
3324 initialization, i. e. you CANNOT use normal RAM which
3325 will become available only after programming the
3326 memory controller and running certain initialization
3327 sequences.
3328
3329 U-Boot uses the following memory types:
907208c4 3330 - MPC8xx: IMMR (internal memory of the CPU)
c609719b 3331
6d0f6bcf 3332- CONFIG_SYS_GBL_DATA_OFFSET:
c609719b
WD
3333
3334 Offset of the initial data structure in the memory
6d0f6bcf
JCPV
3335 area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
3336 CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
c609719b 3337 data is located at the end of the available space
553f0982 3338 (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
acd51f9d 3339 GENERATED_GBL_DATA_SIZE), and the initial stack is just
6d0f6bcf
JCPV
3340 below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
3341 CONFIG_SYS_GBL_DATA_OFFSET) downward.
c609719b
WD
3342
3343 Note:
3344 On the MPC824X (or other systems that use the data
3345 cache for initial memory) the address chosen for
6d0f6bcf 3346 CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
c609719b
WD
3347 point to an otherwise UNUSED address space between
3348 the top of RAM and the start of the PCI space.
3349
6d0f6bcf 3350- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
c609719b 3351
6d0f6bcf 3352- CONFIG_SYS_OR_TIMING_SDRAM:
c609719b
WD
3353 SDRAM timing
3354
6d0f6bcf 3355- CONFIG_SYS_MAMR_PTA:
c609719b
WD
3356 periodic timer for refresh
3357
6d0f6bcf
JCPV
3358- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
3359 CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
3360 CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
3361 CONFIG_SYS_BR1_PRELIM:
c609719b
WD
3362 Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
3363
3364- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
6d0f6bcf
JCPV
3365 CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
3366 CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
c609719b
WD
3367 Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
3368
69fd2d3b 3369- CONFIG_PCI_ENUM_ONLY
b445bbb4 3370 Only scan through and get the devices on the buses.
69fd2d3b
AS
3371 Don't do any setup work, presumably because someone or
3372 something has already done it, and we don't need to do it
3373 a second time. Useful for platforms that are pre-booted
3374 by coreboot or similar.
3375
842033e6
GJ
3376- CONFIG_PCI_INDIRECT_BRIDGE:
3377 Enable support for indirect PCI bridges.
3378
a09b9b68
KG
3379- CONFIG_SYS_SRIO:
3380 Chip has SRIO or not
3381
3382- CONFIG_SRIO1:
3383 Board has SRIO 1 port available
3384
3385- CONFIG_SRIO2:
3386 Board has SRIO 2 port available
3387
c8b28152
LG
3388- CONFIG_SRIO_PCIE_BOOT_MASTER
3389 Board can support master function for Boot from SRIO and PCIE
3390
a09b9b68
KG
3391- CONFIG_SYS_SRIOn_MEM_VIRT:
3392 Virtual Address of SRIO port 'n' memory region
3393
3394- CONFIG_SYS_SRIOn_MEM_PHYS:
3395 Physical Address of SRIO port 'n' memory region
3396
3397- CONFIG_SYS_SRIOn_MEM_SIZE:
3398 Size of SRIO port 'n' memory region
3399
66bd1846
FE
3400- CONFIG_SYS_NAND_BUSWIDTH_16BIT
3401 Defined to tell the NAND controller that the NAND chip is using
3402 a 16 bit bus.
3403 Not all NAND drivers use this symbol.
a430e916 3404 Example of drivers that use it:
66bd1846 3405 - drivers/mtd/nand/ndfc.c
a430e916 3406 - drivers/mtd/nand/mxc_nand.c
eced4626
AW
3407
3408- CONFIG_SYS_NDFC_EBC0_CFG
3409 Sets the EBC0_CFG register for the NDFC. If not defined
3410 a default value will be used.
3411
bb99ad6d 3412- CONFIG_SPD_EEPROM
218ca724
WD
3413 Get DDR timing information from an I2C EEPROM. Common
3414 with pluggable memory modules such as SODIMMs
3415
bb99ad6d
BW
3416 SPD_EEPROM_ADDRESS
3417 I2C address of the SPD EEPROM
3418
6d0f6bcf 3419- CONFIG_SYS_SPD_BUS_NUM
218ca724
WD
3420 If SPD EEPROM is on an I2C bus other than the first
3421 one, specify here. Note that the value must resolve
3422 to something your driver can deal with.
bb99ad6d 3423
1b3e3c4f
YS
3424- CONFIG_SYS_DDR_RAW_TIMING
3425 Get DDR timing information from other than SPD. Common with
3426 soldered DDR chips onboard without SPD. DDR raw timing
3427 parameters are extracted from datasheet and hard-coded into
3428 header files or board specific files.
3429
6f5e1dc5
YS
3430- CONFIG_FSL_DDR_INTERACTIVE
3431 Enable interactive DDR debugging. See doc/README.fsl-ddr.
3432
e32d59a2
YS
3433- CONFIG_FSL_DDR_SYNC_REFRESH
3434 Enable sync of refresh for multiple controllers.
3435
4516ff81
YS
3436- CONFIG_FSL_DDR_BIST
3437 Enable built-in memory test for Freescale DDR controllers.
3438
6d0f6bcf 3439- CONFIG_SYS_83XX_DDR_USES_CS0
218ca724
WD
3440 Only for 83xx systems. If specified, then DDR should
3441 be configured using CS0 and CS1 instead of CS2 and CS3.
2ad6b513 3442
c26e454d
WD
3443- CONFIG_RMII
3444 Enable RMII mode for all FECs.
3445 Note that this is a global option, we can't
3446 have one FEC in standard MII mode and another in RMII mode.
3447
5cf91d6b
WD
3448- CONFIG_CRC32_VERIFY
3449 Add a verify option to the crc32 command.
3450 The syntax is:
3451
3452 => crc32 -v <address> <count> <crc32>
3453
3454 Where address/count indicate a memory area
3455 and crc32 is the correct crc32 which the
3456 area should have.
3457
56523f12
WD
3458- CONFIG_LOOPW
3459 Add the "loopw" memory command. This only takes effect if
493f420e 3460 the memory commands are activated globally (CONFIG_CMD_MEMORY).
56523f12 3461
7b466641
SR
3462- CONFIG_MX_CYCLIC
3463 Add the "mdc" and "mwc" memory commands. These are cyclic
3464 "md/mw" commands.
3465 Examples:
3466
efe2a4d5 3467 => mdc.b 10 4 500
7b466641
SR
3468 This command will print 4 bytes (10,11,12,13) each 500 ms.
3469
efe2a4d5 3470 => mwc.l 100 12345678 10
7b466641
SR
3471 This command will write 12345678 to address 100 all 10 ms.
3472
efe2a4d5 3473 This only takes effect if the memory commands are activated