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Commit | Line | Data |
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dd84058d MY |
1 | menu "ARC architecture" |
2 | depends on ARC | |
3 | ||
4 | config SYS_ARCH | |
dd84058d MY |
5 | default "arc" |
6 | ||
e20bcb04 | 7 | config SYS_CPU |
fdff2370 | 8 | default "arcv1" |
e20bcb04 | 9 | |
812980bd AB |
10 | choice |
11 | prompt "CPU selection" | |
12 | default CPU_ARC770D | |
13 | ||
14 | config CPU_ARC750D | |
15 | bool "ARC 750D" | |
16 | select ARC_MMU_V2 | |
17 | help | |
18 | Choose this option to build an U-Boot for ARC750D CPU. | |
19 | ||
20 | config CPU_ARC770D | |
21 | bool "ARC 770D" | |
22 | select ARC_MMU_V3 | |
23 | help | |
24 | Choose this option to build an U-Boot for ARC770D CPU. | |
25 | ||
26 | endchoice | |
27 | ||
28 | choice | |
29 | prompt "MMU Version" | |
30 | default ARC_MMU_V3 if CPU_ARC770D | |
31 | default ARC_MMU_V2 if CPU_ARC750D | |
32 | ||
33 | config ARC_MMU_V2 | |
34 | bool "MMU v2" | |
35 | depends on CPU_ARC750D | |
36 | help | |
37 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
38 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
39 | ||
40 | config ARC_MMU_V3 | |
41 | bool "MMU v3" | |
42 | depends on CPU_ARC770D | |
43 | help | |
44 | Introduced with ARC700 4.10: New Features | |
45 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
46 | Shared Address Spaces (SASID) | |
47 | ||
48 | endchoice | |
49 | ||
1f9ad445 AB |
50 | config CPU_BIG_ENDIAN |
51 | bool "Enable Big Endian Mode" | |
52 | default n | |
53 | help | |
54 | Build kernel for Big Endian Mode of ARC CPU | |
55 | ||
205e7a7b AB |
56 | config SYS_ICACHE_OFF |
57 | bool "Do not use Instruction Cache" | |
58 | default n | |
59 | ||
60 | config SYS_DCACHE_OFF | |
61 | bool "Do not use Data Cache" | |
62 | default n | |
63 | ||
64 | config ARC_CACHE_LINE_SHIFT | |
65 | int "Cache Line Length (as power of 2)" | |
66 | range 5 7 | |
67 | default "6" | |
68 | depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF | |
69 | help | |
70 | Starting with ARC700 4.9, Cache line length is configurable, | |
71 | This option specifies "N", with Line-len = 2 power N | |
72 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
73 | Linux only supports same line lengths for I and D caches. | |
74 | ||
dd84058d MY |
75 | choice |
76 | prompt "Target select" | |
77 | ||
78 | config TARGET_TB100 | |
79 | bool "Support tb100" | |
80 | ||
81 | config TARGET_ARCANGEL4 | |
82 | bool "Support arcangel4" | |
83 | ||
dd84058d MY |
84 | config TARGET_AXS101 |
85 | bool "Support axs101" | |
86 | ||
87 | endchoice | |
88 | ||
89 | source "board/abilis/tb100/Kconfig" | |
90 | source "board/synopsys/Kconfig" | |
91 | source "board/synopsys/axs101/Kconfig" | |
92 | ||
93 | endmenu |