]>
Commit | Line | Data |
---|---|---|
288aaacf AB |
1 | /* |
2 | * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __ASM_ARC_CACHE_H | |
8 | #define __ASM_ARC_CACHE_H | |
9 | ||
10 | #include <config.h> | |
11 | ||
12 | /* | |
13 | * The current upper bound for ARC L1 data cache line sizes is 128 bytes. | |
14 | * We use that value for aligning DMA buffers unless the board config has | |
15 | * specified an alternate cache line size. | |
16 | */ | |
17 | #ifdef CONFIG_SYS_CACHELINE_SIZE | |
18 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE | |
19 | #else | |
20 | #define ARCH_DMA_MINALIGN 128 | |
21 | #endif | |
22 | ||
23 | #endif /* __ASM_ARC_CACHE_H */ |