arc: cache: Add required NOPs after invalidation of instruction cache
[people/ms/u-boot.git] / arch / arc / lib / cache.c
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1/*
2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <config.h>
379b3280 8#include <common.h>
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9#include <linux/compiler.h>
10#include <linux/kernel.h>
97a63144 11#include <linux/log2.h>
2f16ac9d 12#include <asm/arcregs.h>
205e7a7b 13#include <asm/cache.h>
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14
15/* Bit values in IC_CTRL */
16#define IC_CTRL_CACHE_DISABLE (1 << 0)
17
18/* Bit values in DC_CTRL */
19#define DC_CTRL_CACHE_DISABLE (1 << 0)
20#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
21#define DC_CTRL_FLUSH_STATUS (1 << 8)
f8cf3d1e 22#define CACHE_VER_NUM_MASK 0xF
6eb15e50 23#define SLC_CTRL_SB (1 << 2)
2f16ac9d 24
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25#define OP_INV 0x1
26#define OP_FLUSH 0x2
27#define OP_INV_IC 0x3
28
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29/*
30 * By default that variable will fall into .bss section.
31 * But .bss section is not relocated and so it will be initilized before
32 * relocation but will be used after being zeroed.
33 */
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34int l1_line_sz __section(".data");
35int dcache_exists __section(".data");
36int icache_exists __section(".data");
37
38#define CACHE_LINE_MASK (~(l1_line_sz - 1))
39
40#ifdef CONFIG_ISA_ARCV2
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41int slc_line_sz __section(".data");
42int slc_exists __section(".data");
db6ce231 43int ioc_exists __section(".data");
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44
45static unsigned int __before_slc_op(const int op)
46{
47 unsigned int reg = reg;
48
49 if (op == OP_INV) {
50 /*
51 * IM is set by default and implies Flush-n-inv
52 * Clear it here for vanilla inv
53 */
54 reg = read_aux_reg(ARC_AUX_SLC_CTRL);
55 write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
56 }
57
58 return reg;
59}
60
61static void __after_slc_op(const int op, unsigned int reg)
62{
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63 if (op & OP_FLUSH) { /* flush / flush-n-inv both wait */
64 /*
65 * Make sure "busy" bit reports correct status,
66 * see STAR 9001165532
67 */
68 read_aux_reg(ARC_AUX_SLC_CTRL);
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69 while (read_aux_reg(ARC_AUX_SLC_CTRL) &
70 DC_CTRL_FLUSH_STATUS)
71 ;
40a808f1 72 }
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73
74 /* Switch back to default Invalidate mode */
75 if (op == OP_INV)
76 write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
77}
78
79static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
80 const int op)
81{
82 unsigned int aux_cmd;
83 int num_lines;
84
85#define SLC_LINE_MASK (~(slc_line_sz - 1))
86
87 aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
88
89 sz += paddr & ~SLC_LINE_MASK;
90 paddr &= SLC_LINE_MASK;
91
92 num_lines = DIV_ROUND_UP(sz, slc_line_sz);
93
94 while (num_lines-- > 0) {
95 write_aux_reg(aux_cmd, paddr);
96 paddr += slc_line_sz;
97 }
98}
99
100static inline void __slc_entire_op(const int cacheop)
101{
102 int aux;
103 unsigned int ctrl_reg = __before_slc_op(cacheop);
104
105 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
106 aux = ARC_AUX_SLC_INVALIDATE;
107 else
108 aux = ARC_AUX_SLC_FLUSH;
109
110 write_aux_reg(aux, 0x1);
111
112 __after_slc_op(cacheop, ctrl_reg);
113}
114
115static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
116 const int cacheop)
117{
118 unsigned int ctrl_reg = __before_slc_op(cacheop);
119 __slc_line_loop(paddr, sz, cacheop);
120 __after_slc_op(cacheop, ctrl_reg);
121}
122#else
123#define __slc_entire_op(cacheop)
124#define __slc_line_op(paddr, sz, cacheop)
125#endif
126
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127#ifdef CONFIG_ISA_ARCV2
128static void read_decode_cache_bcr_arcv2(void)
ef639e6f 129{
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130 union {
131 struct {
132#ifdef CONFIG_CPU_BIG_ENDIAN
133 unsigned int pad:24, way:2, lsz:2, sz:4;
134#else
135 unsigned int sz:4, lsz:2, way:2, pad:24;
136#endif
137 } fields;
138 unsigned int word;
139 } slc_cfg;
140
141 union {
142 struct {
143#ifdef CONFIG_CPU_BIG_ENDIAN
144 unsigned int pad:24, ver:8;
145#else
146 unsigned int ver:8, pad:24;
147#endif
148 } fields;
149 unsigned int word;
150 } sbcr;
151
152 sbcr.word = read_aux_reg(ARC_BCR_SLC);
153 if (sbcr.fields.ver) {
154 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
155 slc_exists = 1;
156 slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
157 }
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158
159 union {
160 struct bcr_clust_cfg {
161#ifdef CONFIG_CPU_BIG_ENDIAN
162 unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
163#else
164 unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
165#endif
166 } fields;
167 unsigned int word;
168 } cbcr;
169
170 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
171 if (cbcr.fields.c)
172 ioc_exists = 1;
ef639e6f 173}
379b3280 174#endif
ef639e6f 175
379b3280 176void read_decode_cache_bcr(void)
ef639e6f 177{
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178 int dc_line_sz = 0, ic_line_sz = 0;
179
180 union {
181 struct {
182#ifdef CONFIG_CPU_BIG_ENDIAN
183 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
184#else
185 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
186#endif
187 } fields;
188 unsigned int word;
189 } ibcr, dbcr;
190
191 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
192 if (ibcr.fields.ver) {
193 icache_exists = 1;
194 l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
195 if (!ic_line_sz)
196 panic("Instruction exists but line length is 0\n");
197 }
198
199 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
200 if (dbcr.fields.ver){
201 dcache_exists = 1;
202 l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
203 if (!dc_line_sz)
204 panic("Data cache exists but line length is 0\n");
205 }
206
207 if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
208 panic("Instruction and data cache line lengths differ\n");
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209}
210
211void cache_init(void)
212{
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213 read_decode_cache_bcr();
214
ef639e6f 215#ifdef CONFIG_ISA_ARCV2
379b3280 216 read_decode_cache_bcr_arcv2();
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217
218 if (ioc_exists) {
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219 /* IOC Aperture start is equal to DDR start */
220 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
221 /* IOC Aperture size is equal to DDR size */
222 long ap_size = CONFIG_SYS_SDRAM_SIZE;
223
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224 flush_dcache_all();
225 invalidate_dcache_all();
226
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227 if (!is_power_of_2(ap_size) || ap_size < 4096)
228 panic("IOC Aperture size must be power of 2 and bigger 4Kib");
229
230 /*
231 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
232 * so setting 0x11 implies 512M, 0x12 implies 1G...
233 */
234 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
235 order_base_2(ap_size/1024) - 2);
236
237
238 /* IOC Aperture start must be aligned to the size of the aperture */
239 if (ap_base % ap_size != 0)
240 panic("IOC Aperture start must be aligned to the size of the aperture");
241
242 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
db6ce231 243 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
db6ce231 244 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
97a63144 245
db6ce231 246 }
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247#endif
248}
249
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250int icache_status(void)
251{
379b3280 252 if (!icache_exists)
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253 return 0;
254
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255 if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
256 return 0;
257 else
258 return 1;
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259}
260
261void icache_enable(void)
262{
379b3280 263 if (icache_exists)
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264 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
265 ~IC_CTRL_CACHE_DISABLE);
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266}
267
268void icache_disable(void)
269{
379b3280 270 if (icache_exists)
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271 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
272 IC_CTRL_CACHE_DISABLE);
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273}
274
ef639e6f 275#ifndef CONFIG_SYS_DCACHE_OFF
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276void invalidate_icache_all(void)
277{
2f16ac9d 278 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
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279 if (icache_status()) {
280 write_aux_reg(ARC_AUX_IC_IVIC, 1);
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281 /*
282 * As per ARC HS databook (see chapter 5.3.3.2)
283 * it is required to add 3 NOPs after each write to IC_IVIC.
284 */
285 __builtin_arc_nop();
286 __builtin_arc_nop();
287 __builtin_arc_nop();
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288 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
289 }
2f16ac9d 290}
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291#else
292void invalidate_icache_all(void)
293{
294}
295#endif
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296
297int dcache_status(void)
298{
379b3280 299 if (!dcache_exists)
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300 return 0;
301
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302 if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
303 return 0;
304 else
305 return 1;
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306}
307
308void dcache_enable(void)
309{
379b3280 310 if (!dcache_exists)
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311 return;
312
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313 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
314 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
315}
316
317void dcache_disable(void)
318{
379b3280 319 if (!dcache_exists)
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320 return;
321
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322 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
323 DC_CTRL_CACHE_DISABLE);
324}
325
2f16ac9d 326#ifndef CONFIG_SYS_DCACHE_OFF
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327/*
328 * Common Helper for Line Operations on {I,D}-Cache
329 */
330static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
331 const int cacheop)
2f16ac9d 332{
ef639e6f 333 unsigned int aux_cmd;
5ff40f3d 334#if (CONFIG_ARC_MMU_VER == 3)
ef639e6f 335 unsigned int aux_tag;
2f16ac9d 336#endif
ef639e6f 337 int num_lines;
2f16ac9d 338
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339 if (cacheop == OP_INV_IC) {
340 aux_cmd = ARC_AUX_IC_IVIL;
5ff40f3d 341#if (CONFIG_ARC_MMU_VER == 3)
ef639e6f 342 aux_tag = ARC_AUX_IC_PTAG;
2f16ac9d 343#endif
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344 } else {
345 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
346 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
347#if (CONFIG_ARC_MMU_VER == 3)
348 aux_tag = ARC_AUX_DC_PTAG;
349#endif
350 }
2f16ac9d 351
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352 sz += paddr & ~CACHE_LINE_MASK;
353 paddr &= CACHE_LINE_MASK;
2f16ac9d 354
379b3280 355 num_lines = DIV_ROUND_UP(sz, l1_line_sz);
2f16ac9d 356
ef639e6f 357 while (num_lines-- > 0) {
5ff40f3d 358#if (CONFIG_ARC_MMU_VER == 3)
ef639e6f 359 write_aux_reg(aux_tag, paddr);
2f16ac9d 360#endif
ef639e6f 361 write_aux_reg(aux_cmd, paddr);
379b3280 362 paddr += l1_line_sz;
2f16ac9d 363 }
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364}
365
ef639e6f 366static unsigned int __before_dc_op(const int op)
2f16ac9d 367{
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368 unsigned int reg;
369
370 if (op == OP_INV) {
371 /*
372 * IM is set by default and implies Flush-n-inv
373 * Clear it here for vanilla inv
374 */
375 reg = read_aux_reg(ARC_AUX_DC_CTRL);
376 write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
377 }
ae4a351a 378
ef639e6f 379 return reg;
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380}
381
ef639e6f 382static void __after_dc_op(const int op, unsigned int reg)
2f16ac9d 383{
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384 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
385 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
386 ;
387
388 /* Switch back to default Invalidate mode */
389 if (op == OP_INV)
390 write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
2f16ac9d 391}
6eb15e50 392
ef639e6f 393static inline void __dc_entire_op(const int cacheop)
6eb15e50 394{
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395 int aux;
396 unsigned int ctrl_reg = __before_dc_op(cacheop);
6eb15e50 397
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398 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
399 aux = ARC_AUX_DC_IVDC;
400 else
401 aux = ARC_AUX_DC_FLSH;
6eb15e50 402
ef639e6f 403 write_aux_reg(aux, 0x1);
6eb15e50 404
ef639e6f 405 __after_dc_op(cacheop, ctrl_reg);
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406}
407
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408static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
409 const int cacheop)
6eb15e50 410{
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411 unsigned int ctrl_reg = __before_dc_op(cacheop);
412 __cache_line_loop(paddr, sz, cacheop);
413 __after_dc_op(cacheop, ctrl_reg);
414}
415#else
416#define __dc_entire_op(cacheop)
417#define __dc_line_op(paddr, sz, cacheop)
418#endif /* !CONFIG_SYS_DCACHE_OFF */
6eb15e50 419
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420void invalidate_dcache_range(unsigned long start, unsigned long end)
421{
ef639e6f 422#ifdef CONFIG_ISA_ARCV2
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423 if (!ioc_exists)
424#endif
425 __dc_line_op(start, end - start, OP_INV);
426
427#ifdef CONFIG_ISA_ARCV2
428 if (slc_exists && !ioc_exists)
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429 __slc_line_op(start, end - start, OP_INV);
430#endif
431}
6eb15e50 432
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433void flush_dcache_range(unsigned long start, unsigned long end)
434{
ef639e6f 435#ifdef CONFIG_ISA_ARCV2
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436 if (!ioc_exists)
437#endif
438 __dc_line_op(start, end - start, OP_FLUSH);
439
440#ifdef CONFIG_ISA_ARCV2
441 if (slc_exists && !ioc_exists)
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442 __slc_line_op(start, end - start, OP_FLUSH);
443#endif
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444}
445
ef639e6f 446void flush_cache(unsigned long start, unsigned long size)
6eb15e50 447{
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448 flush_dcache_range(start, start + size);
449}
6eb15e50 450
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451void invalidate_dcache_all(void)
452{
bd91508b 453 __dc_entire_op(OP_INV);
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454
455#ifdef CONFIG_ISA_ARCV2
bd91508b 456 if (slc_exists)
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457 __slc_entire_op(OP_INV);
458#endif
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459}
460
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461void flush_dcache_all(void)
462{
2a8382c6 463 __dc_entire_op(OP_FLUSH);
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464
465#ifdef CONFIG_ISA_ARCV2
2a8382c6 466 if (slc_exists)
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467 __slc_entire_op(OP_FLUSH);
468#endif
469}