projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 281dfb0c JCPV |
1 | /* |
| 2 | * (C) Copyright 2002 | |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
| 4 | * Marius Groeger <mgroeger@sysgo.de> | |
| 5 | * | |
| 6 | * (C) Copyright 2002 | |
| 7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
| 8 | * Alex Zuepke <azu@sysgo.de> | |
| 9 | * | |
| 10 | * See file CREDITS for list of people who contributed to this | |
| 11 | * project. | |
| 12 | * | |
| 13 | * This program is free software; you can redistribute it and/or | |
| 14 | * modify it under the terms of the GNU General Public License as | |
| 15 | * published by the Free Software Foundation; either version 2 of | |
| 16 | * the License, or (at your option) any later version. | |
| 17 | * | |
| 18 | * This program is distributed in the hope that it will be useful, | |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 21 | * GNU General Public License for more details. | |
| 22 | * | |
| 23 | * You should have received a copy of the GNU General Public License | |
| 24 | * along with this program; if not, write to the Free Software | |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 26 | * MA 02111-1307 USA | |
| 27 | */ | |
| 28 | ||
| 29 | #include <common.h> | |
| 30 | #include <asm/hardware.h> | |
| 31 | ||
| 32 | void icache_enable (void) | |
| 33 | { | |
| 34 | s32 i; | |
| 35 | ||
| 36 | /* disable all cache bits */ | |
| 37 | CLR_REG( REG_SYSCFG, 0x3F); | |
| 38 | ||
| 39 | /* 8KB cache, write enable */ | |
| 40 | SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); | |
| 41 | ||
| 42 | /* clear TAG RAM bits */ | |
| 43 | for ( i = 0; i < 256; i++) | |
| 44 | PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); | |
| 45 | ||
| 46 | /* clear SET0 RAM */ | |
| 47 | for(i=0; i < 1024; i++) | |
| 48 | PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); | |
| 49 | ||
| 50 | /* clear SET1 RAM */ | |
| 51 | for(i=0; i < 1024; i++) | |
| 52 | PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); | |
| 53 | ||
| 54 | /* enable cache */ | |
| 55 | SET_REG( REG_SYSCFG, CACHE_ENABLE); | |
| 56 | ||
| 57 | } | |
| 58 | ||
| 59 | void icache_disable (void) | |
| 60 | { | |
| 61 | /* disable all cache bits */ | |
| 62 | CLR_REG( REG_SYSCFG, 0x3F); | |
| 63 | } | |
| 64 | ||
| 65 | int icache_status (void) | |
| 66 | { | |
| 67 | return GET_REG( REG_SYSCFG) & CACHE_ENABLE; | |
| 68 | } | |
| 69 | ||
| 70 | void dcache_enable (void) | |
| 71 | { | |
| 72 | /* we don't have seperate instruction/data caches */ | |
| 73 | icache_enable(); | |
| 74 | } | |
| 75 | ||
| 76 | void dcache_disable (void) | |
| 77 | { | |
| 78 | /* we don't have seperate instruction/data caches */ | |
| 79 | icache_disable(); | |
| 80 | } | |
| 81 | ||
| 82 | int dcache_status (void) | |
| 83 | { | |
| 84 | /* we don't have seperate instruction/data caches */ | |
| 85 | return icache_status(); | |
| 86 | } |