[people/ms/u-boot.git] / arch / arm / cpu / arm720t / start.S

/*
 *  armboot - Startup Code for ARM720 CPU-core
 *
 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/hardware.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start: b	reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt:	.word _software_interrupt
_prefetch_abort:	.word _prefetch_abort
_data_abort:		.word _data_abort
_not_used:		.word _not_used
_irq:			.word _irq
_fiq:			.word _fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#else
_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#endif	/* CONFIG_SPL_BUILD */

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from RAM!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _image_copy_end_ofs
_image_copy_end_ofs:
	.word __image_copy_end - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code(addr_moni)
 *
 * This function relocates the monitor code.
 */
	.globl	relocate_code
relocate_code:
	mov	r6, r0	/* save addr of destination */

	adr	r0, _start
	subs	r9, r6, r0		/* r9 <- relocation offset */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _image_copy_end_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	mov	pc, lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */

cpu_init_crit:

#if !defined(CONFIG_TEGRA)
	mov	ip, lr
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependent, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	bl	lowlevel_init
	mov	lr, ip
#endif

	mov	pc, lr


#ifndef CONFIG_SPL_BUILD
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC

	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC
	stmdb	r8, {sp, lr}^			@ Calling SP, LR
	str	lr, [r8, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]			@ Save CPSR
	str	r0, [r8, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str	lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif
#endif /* CONFIG_SPL_BUILD */
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* armboot - Startup Code for ARM720 CPU-core
	3	*
fa82f871 AA	4	* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
fa82f871 AA	5	* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
fe8c2806 WD	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
cdc7fea1	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
fe8c2806 WD	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
25ddd1fb	26	#include <asm-offsets.h>
fe8c2806 WD	27	#include <config.h>
fe8c2806 WD	28	#include <version.h>
39539887	29	#include <asm/hardware.h>
fe8c2806 WD	30
	31	/*
	32	*************************************************************************
	33	*
	34	* Jump vector table as in table 3.1 in [1]
	35	*
	36	*************************************************************************
	37	*/
	38
	39
	40	.globl _start
cdc7fea1	41	_start: b reset
fe8c2806 WD	42	ldr pc, _undefined_instruction
	43	ldr pc, _software_interrupt
	44	ldr pc, _prefetch_abort
	45	ldr pc, _data_abort
	46	ldr pc, _not_used
	47	ldr pc, _irq
	48	ldr pc, _fiq
	49
c7da6c67 AM	50	#ifdef CONFIG_SPL_BUILD
	51	_undefined_instruction: .word _undefined_instruction
	52	_software_interrupt: .word _software_interrupt
	53	_prefetch_abort: .word _prefetch_abort
	54	_data_abort: .word _data_abort
	55	_not_used: .word _not_used
	56	_irq: .word _irq
	57	_fiq: .word _fiq
c037c93b	58	_pad: .word 0x12345678 /* now 164=64 /
c7da6c67	59	#else
cdc7fea1	60	_undefined_instruction: .word undefined_instruction
fe8c2806 WD	61	_software_interrupt: .word software_interrupt
	62	_prefetch_abort: .word prefetch_abort
	63	_data_abort: .word data_abort
	64	_not_used: .word not_used
	65	_irq: .word irq
	66	_fiq: .word fiq
c037c93b	67	_pad: .word 0x12345678 /* now 164=64 /
c7da6c67	68	#endif /* CONFIG_SPL_BUILD */
fe8c2806 WD	69
	70	.balignl 16,0xdeadbeef
	71
	72
	73	/*
	74	*************************************************************************
	75	*
	76	* Startup Code (reset vector)
	77	*
f6e20fc6	78	* do important init only if we don't start from RAM!
fe8c2806 WD	79	* relocate armboot to ram
	80	* setup stack
	81	* jump to second stage
	82	*
	83	*************************************************************************
	84	*/
	85
abef7b85	86	.globl _TEXT_BASE
fe8c2806	87	_TEXT_BASE:
508611bc	88	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
c037c93b AM	89	.word CONFIG_SPL_TEXT_BASE
c037c93b AM	90	#else
14d0a02a	91	.word CONFIG_SYS_TEXT_BASE
c037c93b	92	#endif
fe8c2806	93
fe8c2806	94	/*
f6e20fc6	95	* These are defined in the board-specific linker script.
3336ca60 AA	96	* Subtracting _start from them lets the linker put their
	97	* relative position in the executable instead of leaving
	98	* them null.
fe8c2806	99	*/
3336ca60 AA	100	.globl _bss_start_ofs
	101	_bss_start_ofs:
	102	.word __bss_start - _start
f6e20fc6	103
7086e91b BT	104	.globl _image_copy_end_ofs
	105	_image_copy_end_ofs:
	106	.word __image_copy_end - _start
	107
3336ca60 AA	108	.globl _bss_end_ofs
3336ca60 AA	109	_bss_end_ofs:
3929fb0a	110	.word __bss_end - _start
fe8c2806	111
f326cbba PYC	112	.globl _end_ofs
	113	_end_ofs:
	114	.word _end - _start
	115
fe8c2806 WD	116	#ifdef CONFIG_USE_IRQ
	117	/* IRQ stack memory (calculated at run-time) */
	118	.globl IRQ_STACK_START
	119	IRQ_STACK_START:
	120	.word 0x0badc0de
	121
	122	/* IRQ stack memory (calculated at run-time) */
	123	.globl FIQ_STACK_START
	124	FIQ_STACK_START:
	125	.word 0x0badc0de
	126	#endif
	127
abef7b85 HS	128	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	129	.globl IRQ_STACK_START_IN
	130	IRQ_STACK_START_IN:
	131	.word 0x0badc0de
	132
abef7b85 HS	133	/*
	134	* the actual reset code
	135	*/
	136
	137	reset:
	138	/*
	139	* set the cpu to SVC32 mode
	140	*/
	141	mrs r0,cpsr
	142	bic r0,r0,#0x1f
	143	orr r0,r0,#0xd3
	144	msr cpsr,r0
	145
	146	/*
	147	* we do sys-critical inits only at reboot,
	148	* not when booting from ram!
	149	*/
	150	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	151	bl cpu_init_crit
	152	#endif
	153
e05e5de7	154	bl _main
abef7b85 HS	155
	156	/------------------------------------------------------------------------------/
	157
	158	/*
5c6db120	159	* void relocate_code(addr_moni)
abef7b85	160	*
959eaa74	161	* This function relocates the monitor code.
abef7b85 HS	162	*/
	163	.globl relocate_code
	164	relocate_code:
5c6db120	165	mov r6, r0 /* save addr of destination */
abef7b85	166
abef7b85	167	adr r0, _start
4b3db1cd	168	subs r9, r6, r0 /* r9 <- relocation offset */
e05e5de7	169	beq relocate_done /* skip relocation */
a78fb68f	170	mov r1, r6 /* r1 <- scratch for copy_loop */
7086e91b	171	ldr r3, _image_copy_end_ofs
3336ca60	172	add r2, r0, r3 /* r2 <- source end address */
abef7b85	173
abef7b85	174	copy_loop:
4b3db1cd BT	175	ldmia r0!, {r10-r11} /* copy from source address [r0] */
4b3db1cd BT	176	stmia r1!, {r10-r11} /* copy to target address [r1] */
da90d4ce AA	177	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	178	blo copy_loop
abef7b85	179
401bb30b	180	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	181	/*
	182	* fix .rel.dyn relocations
	183	*/
	184	ldr r0, _TEXT_BASE /* r0 <- Text base */
3336ca60 AA	185	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	186	add r10, r10, r0 /* r10 <- sym table in FLASH */
	187	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	188	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	189	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	190	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
abef7b85	191	fixloop:
3336ca60 AA	192	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	193	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	194	ldr r1, [r2, #4]
1f52d89f AB	195	and r7, r1, #0xff
1f52d89f AB	196	cmp r7, #23 /* relative fixup? */
3336ca60	197	beq fixrel
1f52d89f	198	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	199	beq fixabs
	200	/* ignore unknown type of fixup */
	201	b fixnext
	202	fixabs:
	203	/* absolute fix: set location to (offset) symbol value */
	204	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	205	add r1, r10, r1 /* r1 <- address of symbol in table */
	206	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	207	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	208	b fixnext
	209	fixrel:
	210	/* relative fix: increase location by offset */
	211	ldr r1, [r0]
	212	add r1, r1, r9
	213	fixnext:
	214	str r1, [r0]
	215	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
abef7b85	216	cmp r2, r3
79e63139	217	blo fixloop
abef7b85	218	#endif
abef7b85	219
e05e5de7	220	relocate_done:
abef7b85	221
abef7b85 HS	222	mov pc, lr
abef7b85 HS	223
3336ca60 AA	224	_rel_dyn_start_ofs:
	225	.word __rel_dyn_start - _start
	226	_rel_dyn_end_ofs:
	227	.word __rel_dyn_end - _start
	228	_dynsym_start_ofs:
	229	.word __dynsym_start - _start
abef7b85	230
e05e5de7 AA	231	.globl c_runtime_cpu_setup
	232	c_runtime_cpu_setup:
	233
	234	mov pc, lr
	235
fe8c2806 WD	236	/*
	237	*************************************************************************
	238	*
	239	* CPU_init_critical registers
	240	*
	241	* setup important registers
	242	* setup memory timing
	243	*
	244	*************************************************************************
	245	*/
	246
fe8c2806	247	cpu_init_crit:
fe8c2806	248
6f62f420	249	#if !defined(CONFIG_TEGRA)
87cb6862	250	mov ip, lr
fe8c2806 WD	251	/*
fe8c2806 WD	252	* before relocating, we have to setup RAM timing
f6e20fc6	253	* because memory timing is board-dependent, you will
400558b5	254	* find a lowlevel_init.S in your board directory.
fe8c2806	255	*/
400558b5	256	bl lowlevel_init
fe8c2806	257	mov lr, ip
6bd2447e	258	#endif
fe8c2806 WD	259
	260	mov pc, lr
	261
	262
c7da6c67	263	#ifndef CONFIG_SPL_BUILD
fe8c2806 WD	264	/*
	265	*************************************************************************
	266	*
	267	* Interrupt handling
	268	*
	269	*************************************************************************
	270	*/
	271
	272	@
	273	@ IRQ stack frame.
	274	@
	275	#define S_FRAME_SIZE 72
	276
	277	#define S_OLD_R0 68
	278	#define S_PSR 64
	279	#define S_PC 60
	280	#define S_LR 56
	281	#define S_SP 52
	282
	283	#define S_IP 48
	284	#define S_FP 44
	285	#define S_R10 40
	286	#define S_R9 36
	287	#define S_R8 32
	288	#define S_R7 28
	289	#define S_R6 24
	290	#define S_R5 20
	291	#define S_R4 16
	292	#define S_R3 12
	293	#define S_R2 8
	294	#define S_R1 4
	295	#define S_R0 0
	296
	297	#define MODE_SVC 0x13
	298	#define I_BIT 0x80
	299
	300	/*
	301	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	302	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	303	*/
	304
	305	.macro bad_save_user_regs
	306	sub sp, sp, #S_FRAME_SIZE
	307	stmia sp, {r0 - r12} @ Calling r0-r12
cdc7fea1	308	add r8, sp, #S_PC
fe8c2806	309
abef7b85	310	ldr r2, IRQ_STACK_START_IN
cdc7fea1	311	ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
fe8c2806 WD	312	add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
	313
	314	add r5, sp, #S_SP
	315	mov r1, lr
cdc7fea1	316	stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
fe8c2806 WD	317	mov r0, sp
	318	.endm
	319
	320	.macro irq_save_user_regs
	321	sub sp, sp, #S_FRAME_SIZE
	322	stmia sp, {r0 - r12} @ Calling r0-r12
cdc7fea1 WD	323	add r8, sp, #S_PC
	324	stmdb r8, {sp, lr}^ @ Calling SP, LR
	325	str lr, [r8, #0] @ Save calling PC
	326	mrs r6, spsr
	327	str r6, [r8, #4] @ Save CPSR
	328	str r0, [r8, #8] @ Save OLD_R0
fe8c2806 WD	329	mov r0, sp
	330	.endm
	331
	332	.macro irq_restore_user_regs
	333	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	334	mov r0, r0
	335	ldr lr, [sp, #S_PC] @ Get PC
	336	add sp, sp, #S_FRAME_SIZE
	337	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	338	.endm
	339
	340	.macro get_bad_stack
abef7b85	341	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
fe8c2806 WD	342
	343	str lr, [r13] @ save caller lr / spsr
	344	mrs lr, spsr
cdc7fea1	345	str lr, [r13, #4]
fe8c2806 WD	346
	347	mov r13, #MODE_SVC @ prepare SVC-Mode
	348	msr spsr_c, r13
	349	mov lr, pc
	350	movs pc, lr
	351	.endm
	352
	353	.macro get_irq_stack @ setup IRQ stack
	354	ldr sp, IRQ_STACK_START
	355	.endm
	356
	357	.macro get_fiq_stack @ setup FIQ stack
	358	ldr sp, FIQ_STACK_START
	359	.endm
	360
	361	/*
	362	* exception handlers
	363	*/
cdc7fea1	364	.align 5
fe8c2806 WD	365	undefined_instruction:
	366	get_bad_stack
	367	bad_save_user_regs
cdc7fea1	368	bl do_undefined_instruction
fe8c2806 WD	369
	370	.align 5
	371	software_interrupt:
	372	get_bad_stack
	373	bad_save_user_regs
cdc7fea1	374	bl do_software_interrupt
fe8c2806 WD	375
	376	.align 5
	377	prefetch_abort:
	378	get_bad_stack
	379	bad_save_user_regs
cdc7fea1	380	bl do_prefetch_abort
fe8c2806 WD	381
	382	.align 5
	383	data_abort:
	384	get_bad_stack
	385	bad_save_user_regs
cdc7fea1	386	bl do_data_abort
fe8c2806 WD	387
	388	.align 5
	389	not_used:
	390	get_bad_stack
	391	bad_save_user_regs
cdc7fea1	392	bl do_not_used
fe8c2806 WD	393
	394	#ifdef CONFIG_USE_IRQ
	395
	396	.align 5
	397	irq:
	398	get_irq_stack
	399	irq_save_user_regs
cdc7fea1	400	bl do_irq
fe8c2806 WD	401	irq_restore_user_regs
	402
	403	.align 5
	404	fiq:
	405	get_fiq_stack
	406	/* someone ought to write a more effiction fiq_save_user_regs */
	407	irq_save_user_regs
cdc7fea1	408	bl do_fiq
fe8c2806 WD	409	irq_restore_user_regs
	410
	411	#else
	412
	413	.align 5
	414	irq:
	415	get_bad_stack
	416	bad_save_user_regs
cdc7fea1	417	bl do_irq
fe8c2806 WD	418
	419	.align 5
	420	fiq:
	421	get_bad_stack
	422	bad_save_user_regs
cdc7fea1	423	bl do_fiq
fe8c2806 WD	424
fe8c2806 WD	425	#endif
c7da6c67	426	#endif /* CONFIG_SPL_BUILD */