[people/ms/u-boot.git] / arch / arm / cpu / arm720t / start.S

/*
 *  armboot - Startup Code for ARM720 CPU-core
 *
 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/hardware.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start: b	reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt:	.word _software_interrupt
_prefetch_abort:	.word _prefetch_abort
_data_abort:		.word _data_abort
_not_used:		.word _not_used
_irq:			.word _irq
_fiq:			.word _fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#else
_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#endif	/* CONFIG_SPL_BUILD */

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from RAM!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:

	mov	ip, lr
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependent, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	bl	lowlevel_init
	mov	lr, ip

	mov	pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */


#ifndef CONFIG_SPL_BUILD
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC

	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC
	stmdb	r8, {sp, lr}^			@ Calling SP, LR
	str	lr, [r8, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]			@ Save CPSR
	str	r0, [r8, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str	lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif
#endif /* CONFIG_SPL_BUILD */
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* armboot - Startup Code for ARM720 CPU-core
	3	*
fa82f871 AA	4	* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
fa82f871 AA	5	* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
fe8c2806	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
fe8c2806 WD	8	*/
fe8c2806 WD	9
25ddd1fb	10	#include <asm-offsets.h>
fe8c2806 WD	11	#include <config.h>
fe8c2806 WD	12	#include <version.h>
39539887	13	#include <asm/hardware.h>
fe8c2806 WD	14
	15	/*
	16	*************************************************************************
	17	*
	18	* Jump vector table as in table 3.1 in [1]
	19	*
	20	*************************************************************************
	21	*/
	22
	23
	24	.globl _start
cdc7fea1	25	_start: b reset
fe8c2806 WD	26	ldr pc, _undefined_instruction
	27	ldr pc, _software_interrupt
	28	ldr pc, _prefetch_abort
	29	ldr pc, _data_abort
	30	ldr pc, _not_used
	31	ldr pc, _irq
	32	ldr pc, _fiq
	33
c7da6c67 AM	34	#ifdef CONFIG_SPL_BUILD
	35	_undefined_instruction: .word _undefined_instruction
	36	_software_interrupt: .word _software_interrupt
	37	_prefetch_abort: .word _prefetch_abort
	38	_data_abort: .word _data_abort
	39	_not_used: .word _not_used
	40	_irq: .word _irq
	41	_fiq: .word _fiq
c037c93b	42	_pad: .word 0x12345678 /* now 164=64 /
c7da6c67	43	#else
cdc7fea1	44	_undefined_instruction: .word undefined_instruction
fe8c2806 WD	45	_software_interrupt: .word software_interrupt
	46	_prefetch_abort: .word prefetch_abort
	47	_data_abort: .word data_abort
	48	_not_used: .word not_used
	49	_irq: .word irq
	50	_fiq: .word fiq
c037c93b	51	_pad: .word 0x12345678 /* now 164=64 /
c7da6c67	52	#endif /* CONFIG_SPL_BUILD */
fe8c2806 WD	53
	54	.balignl 16,0xdeadbeef
	55
	56
	57	/*
	58	*************************************************************************
	59	*
	60	* Startup Code (reset vector)
	61	*
f6e20fc6	62	* do important init only if we don't start from RAM!
fe8c2806 WD	63	* relocate armboot to ram
	64	* setup stack
	65	* jump to second stage
	66	*
	67	*************************************************************************
	68	*/
	69
fe8c2806 WD	70	#ifdef CONFIG_USE_IRQ
	71	/* IRQ stack memory (calculated at run-time) */
	72	.globl IRQ_STACK_START
	73	IRQ_STACK_START:
	74	.word 0x0badc0de
	75
	76	/* IRQ stack memory (calculated at run-time) */
	77	.globl FIQ_STACK_START
	78	FIQ_STACK_START:
	79	.word 0x0badc0de
	80	#endif
	81
abef7b85 HS	82	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	83	.globl IRQ_STACK_START_IN
	84	IRQ_STACK_START_IN:
	85	.word 0x0badc0de
	86
abef7b85 HS	87	/*
	88	* the actual reset code
	89	*/
	90
	91	reset:
	92	/*
	93	* set the cpu to SVC32 mode
	94	*/
	95	mrs r0,cpsr
	96	bic r0,r0,#0x1f
	97	orr r0,r0,#0xd3
	98	msr cpsr,r0
	99
	100	/*
	101	* we do sys-critical inits only at reboot,
	102	* not when booting from ram!
	103	*/
	104	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	105	bl cpu_init_crit
	106	#endif
	107
e05e5de7	108	bl _main
abef7b85 HS	109
	110	/------------------------------------------------------------------------------/
	111
e05e5de7 AA	112	.globl c_runtime_cpu_setup
	113	c_runtime_cpu_setup:
	114
	115	mov pc, lr
	116
fe8c2806 WD	117	/*
	118	*************************************************************************
	119	*
	120	* CPU_init_critical registers
	121	*
	122	* setup important registers
	123	* setup memory timing
	124	*
	125	*************************************************************************
	126	*/
	127
578e6378	128	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
fe8c2806	129	cpu_init_crit:
fe8c2806	130
87cb6862	131	mov ip, lr
fe8c2806 WD	132	/*
fe8c2806 WD	133	* before relocating, we have to setup RAM timing
f6e20fc6	134	* because memory timing is board-dependent, you will
400558b5	135	* find a lowlevel_init.S in your board directory.
fe8c2806	136	*/
400558b5	137	bl lowlevel_init
fe8c2806 WD	138	mov lr, ip
	139
	140	mov pc, lr
578e6378	141	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
fe8c2806 WD	142
fe8c2806 WD	143
c7da6c67	144	#ifndef CONFIG_SPL_BUILD
fe8c2806 WD	145	/*
	146	*************************************************************************
	147	*
	148	* Interrupt handling
	149	*
	150	*************************************************************************
	151	*/
	152
	153	@
	154	@ IRQ stack frame.
	155	@
	156	#define S_FRAME_SIZE 72
	157
	158	#define S_OLD_R0 68
	159	#define S_PSR 64
	160	#define S_PC 60
	161	#define S_LR 56
	162	#define S_SP 52
	163
	164	#define S_IP 48
	165	#define S_FP 44
	166	#define S_R10 40
	167	#define S_R9 36
	168	#define S_R8 32
	169	#define S_R7 28
	170	#define S_R6 24
	171	#define S_R5 20
	172	#define S_R4 16
	173	#define S_R3 12
	174	#define S_R2 8
	175	#define S_R1 4
	176	#define S_R0 0
	177
	178	#define MODE_SVC 0x13
	179	#define I_BIT 0x80
	180
	181	/*
	182	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	183	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	184	*/
	185
	186	.macro bad_save_user_regs
	187	sub sp, sp, #S_FRAME_SIZE
	188	stmia sp, {r0 - r12} @ Calling r0-r12
cdc7fea1	189	add r8, sp, #S_PC
fe8c2806	190
abef7b85	191	ldr r2, IRQ_STACK_START_IN
cdc7fea1	192	ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
fe8c2806 WD	193	add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
	194
	195	add r5, sp, #S_SP
	196	mov r1, lr
cdc7fea1	197	stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
fe8c2806 WD	198	mov r0, sp
	199	.endm
	200
	201	.macro irq_save_user_regs
	202	sub sp, sp, #S_FRAME_SIZE
	203	stmia sp, {r0 - r12} @ Calling r0-r12
cdc7fea1 WD	204	add r8, sp, #S_PC
	205	stmdb r8, {sp, lr}^ @ Calling SP, LR
	206	str lr, [r8, #0] @ Save calling PC
	207	mrs r6, spsr
	208	str r6, [r8, #4] @ Save CPSR
	209	str r0, [r8, #8] @ Save OLD_R0
fe8c2806 WD	210	mov r0, sp
	211	.endm
	212
	213	.macro irq_restore_user_regs
	214	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	215	mov r0, r0
	216	ldr lr, [sp, #S_PC] @ Get PC
	217	add sp, sp, #S_FRAME_SIZE
	218	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	219	.endm
	220
	221	.macro get_bad_stack
abef7b85	222	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
fe8c2806 WD	223
	224	str lr, [r13] @ save caller lr / spsr
	225	mrs lr, spsr
cdc7fea1	226	str lr, [r13, #4]
fe8c2806 WD	227
	228	mov r13, #MODE_SVC @ prepare SVC-Mode
	229	msr spsr_c, r13
	230	mov lr, pc
	231	movs pc, lr
	232	.endm
	233
	234	.macro get_irq_stack @ setup IRQ stack
	235	ldr sp, IRQ_STACK_START
	236	.endm
	237
	238	.macro get_fiq_stack @ setup FIQ stack
	239	ldr sp, FIQ_STACK_START
	240	.endm
	241
	242	/*
	243	* exception handlers
	244	*/
cdc7fea1	245	.align 5
fe8c2806 WD	246	undefined_instruction:
	247	get_bad_stack
	248	bad_save_user_regs
cdc7fea1	249	bl do_undefined_instruction
fe8c2806 WD	250
	251	.align 5
	252	software_interrupt:
	253	get_bad_stack
	254	bad_save_user_regs
cdc7fea1	255	bl do_software_interrupt
fe8c2806 WD	256
	257	.align 5
	258	prefetch_abort:
	259	get_bad_stack
	260	bad_save_user_regs
cdc7fea1	261	bl do_prefetch_abort
fe8c2806 WD	262
	263	.align 5
	264	data_abort:
	265	get_bad_stack
	266	bad_save_user_regs
cdc7fea1	267	bl do_data_abort
fe8c2806 WD	268
	269	.align 5
	270	not_used:
	271	get_bad_stack
	272	bad_save_user_regs
cdc7fea1	273	bl do_not_used
fe8c2806 WD	274
	275	#ifdef CONFIG_USE_IRQ
	276
	277	.align 5
	278	irq:
	279	get_irq_stack
	280	irq_save_user_regs
cdc7fea1	281	bl do_irq
fe8c2806 WD	282	irq_restore_user_regs
	283
	284	.align 5
	285	fiq:
	286	get_fiq_stack
	287	/* someone ought to write a more effiction fiq_save_user_regs */
	288	irq_save_user_regs
cdc7fea1	289	bl do_fiq
fe8c2806 WD	290	irq_restore_user_regs
	291
	292	#else
	293
	294	.align 5
	295	irq:
	296	get_bad_stack
	297	bad_save_user_regs
cdc7fea1	298	bl do_irq
fe8c2806 WD	299
	300	.align 5
	301	fiq:
	302	get_bad_stack
	303	bad_save_user_regs
cdc7fea1	304	bl do_fiq
fe8c2806 WD	305
fe8c2806 WD	306	#endif
c7da6c67	307	#endif /* CONFIG_SPL_BUILD */