[people/ms/u-boot.git] / arch / arm / cpu / arm720t / tegra-common / cpu.c

/*
 * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/scu.h>
#include "cpu.h"

int get_num_cpus(void)
{
	struct apb_misc_gp_ctlr *gp;
	uint rev;

	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;

	switch (rev) {
	case CHIPID_TEGRA20:
		return 2;
		break;
	case CHIPID_TEGRA30:
	case CHIPID_TEGRA114:
	default:
		return 4;
		break;
	}
}

/*
 * Timing tables for each SOC for all four oscillator options.
 */
struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
	/*
	 * T20: 1 GHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      22:20    3
	 * PLLX_BASE  n      17: 8   10
	 * PLLX_BASE  m       4: 0    5
	 * PLLX_MISC  cpcon  11: 8    4
	 */
	{
		{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
		{ .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
		{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
		{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
	},
	/*
	 * T25: 1.2 GHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      22:20    3
	 * PLLX_BASE  n      17: 8   10
	 * PLLX_BASE  m       4: 0    5
	 * PLLX_MISC  cpcon  11: 8    4
	 */
	{
		{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
		{ .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
		{ .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
		{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
	},
	/*
	 * T30: 600 MHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      22:20    3
	 * PLLX_BASE  n      17: 8   10
	 * PLLX_BASE  m       4: 0    5
	 * PLLX_MISC  cpcon  11: 8    4
	 */
	{
		{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
		{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
		{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
		{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
	},
	/*
	 * T114: 700 MHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      23:20    4
	 * PLLX_BASE  n      15: 8    8
	 * PLLX_BASE  m       7: 0    8
	 */
	{
		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
	},

	/*
	 * T124: 700 MHz
	 *
	 * Register   Field  Bits   Width
	 * ------------------------------
	 * PLLX_BASE  p      23:20    4
	 * PLLX_BASE  n      15: 8    8
	 * PLLX_BASE  m       7: 0    8
	 */
	{
		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
	},
};

static inline void pllx_set_iddq(void)
{
#if defined(CONFIG_TEGRA124)
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 reg;

	/* Disable IDDQ */
	reg = readl(&clkrst->crc_pllx_misc3);
	reg &= ~PLLX_IDDQ_MASK;
	writel(reg, &clkrst->crc_pllx_misc3);
	udelay(2);
	debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
	      readl(&clkrst->crc_pllx_misc3));
#endif
}

int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
		u32 divp, u32 cpcon)
{
	int chip = tegra_get_chip();
	u32 reg;

	/* If PLLX is already enabled, just return */
	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
		debug("pllx_set_rate: PLLX already enabled, returning\n");
		return 0;
	}

	debug(" pllx_set_rate entry\n");

	pllx_set_iddq();

	/* Set BYPASS, m, n and p to PLLX_BASE */
	reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
	reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
	writel(reg, &pll->pll_base);

	/* Set cpcon to PLLX_MISC */
	if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
		reg = (cpcon << PLL_CPCON_SHIFT);
	else
		reg = 0;

	/* Set dccon to PLLX_MISC if freq > 600MHz */
	if (divn > 600)
		reg |= (1 << PLL_DCCON_SHIFT);
	writel(reg, &pll->pll_misc);

	/* Disable BYPASS */
	reg = readl(&pll->pll_base);
	reg &= ~PLL_BYPASS_MASK;
	writel(reg, &pll->pll_base);
	debug("pllx_set_rate: base = 0x%08X\n", reg);

	/* Set lock_enable to PLLX_MISC */
	reg = readl(&pll->pll_misc);
	reg |= PLL_LOCK_ENABLE_MASK;
	writel(reg, &pll->pll_misc);
	debug("pllx_set_rate: misc = 0x%08X\n", reg);

	/* Enable PLLX last, once it's all configured */
	reg = readl(&pll->pll_base);
	reg |= PLL_ENABLE_MASK;
	writel(reg, &pll->pll_base);
	debug("pllx_set_rate: base final = 0x%08X\n", reg);

	return 0;
}

void init_pllx(void)
{
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
	int soc_type, sku_info, chip_sku;
	enum clock_osc_freq osc;
	struct clk_pll_table *sel;

	debug("init_pllx entry\n");

	/* get SOC (chip) type */
	soc_type = tegra_get_chip();
	debug(" init_pllx: SoC = 0x%02X\n", soc_type);

	/* get SKU info */
	sku_info = tegra_get_sku_info();
	debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);

	/* get chip SKU, combo of the above info */
	chip_sku = tegra_get_chip_sku();
	debug(" init_pllx: Chip SKU = %d\n", chip_sku);

	/* get osc freq */
	osc = clock_get_osc_freq();
	debug(" init_pllx: osc = %d\n", osc);

	/* set pllx */
	sel = &tegra_pll_x_table[chip_sku][osc];
	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
}

void enable_cpu_clock(int enable)
{
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 clk;

	/*
	 * NOTE:
	 * Regardless of whether the request is to enable or disable the CPU
	 * clock, every processor in the CPU complex except the master (CPU 0)
	 * will have it's clock stopped because the AVP only talks to the
	 * master.
	 */

	if (enable) {
		/* Initialize PLLX */
		init_pllx();

		/* Wait until all clocks are stable */
		udelay(PLL_STABILIZATION_DELAY);

		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
	}

	/*
	 * Read the register containing the individual CPU clock enables and
	 * always stop the clocks to CPUs > 0.
	 */
	clk = readl(&clkrst->crc_clk_cpu_cmplx);
	clk |= 1 << CPU1_CLK_STP_SHIFT;
	if (get_num_cpus() == 4)
		clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);

	/* Stop/Unstop the CPU clock */
	clk &= ~CPU0_CLK_STP_MASK;
	clk |= !enable << CPU0_CLK_STP_SHIFT;
	writel(clk, &clkrst->crc_clk_cpu_cmplx);

	clock_enable(PERIPH_ID_CPU);
}

static int is_cpu_powered(void)
{
	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;

	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
}

static void remove_cpu_io_clamps(void)
{
	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
	u32 reg;

	/* Remove the clamps on the CPU I/O signals */
	reg = readl(&pmc->pmc_remove_clamping);
	reg |= CPU_CLMP;
	writel(reg, &pmc->pmc_remove_clamping);

	/* Give I/O signals time to stabilize */
	udelay(IO_STABILIZATION_DELAY);
}

void powerup_cpu(void)
{
	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
	u32 reg;
	int timeout = IO_STABILIZATION_DELAY;

	if (!is_cpu_powered()) {
		/* Toggle the CPU power state (OFF -> ON) */
		reg = readl(&pmc->pmc_pwrgate_toggle);
		reg &= PARTID_CP;
		reg |= START_CP;
		writel(reg, &pmc->pmc_pwrgate_toggle);

		/* Wait for the power to come up */
		while (!is_cpu_powered()) {
			if (timeout-- == 0)
				printf("CPU failed to power up!\n");
			else
				udelay(10);
		}

		/*
		 * Remove the I/O clamps from CPU power partition.
		 * Recommended only on a Warm boot, if the CPU partition gets
		 * power gated. Shouldn't cause any harm when called after a
		 * cold boot according to HW, probably just redundant.
		 */
		remove_cpu_io_clamps();
	}
}

void reset_A9_cpu(int reset)
{
	/*
	* NOTE:  Regardless of whether the request is to hold the CPU in reset
	*        or take it out of reset, every processor in the CPU complex
	*        except the master (CPU 0) will be held in reset because the
	*        AVP only talks to the master. The AVP does not know that there
	*        are multiple processors in the CPU complex.
	*/
	int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
	int num_cpus = get_num_cpus();
	int cpu;

	debug("reset_a9_cpu entry\n");
	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
	for (cpu = 1; cpu < num_cpus; cpu++)
		reset_cmplx_set_enable(cpu, mask, 1);
	reset_cmplx_set_enable(0, mask, reset);

	/* Enable/Disable master CPU reset */
	reset_set_enable(PERIPH_ID_CPU, reset);
}

void clock_enable_coresight(int enable)
{
	u32 rst, src = 2;

	debug("clock_enable_coresight entry\n");
	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);

	if (enable) {
		/*
		 * Put CoreSight on PLLP_OUT0 and divide it down as per
		 * PLLP base frequency based on SoC type (T20/T30+).
		 * Clock divider request would setup CSITE clock as 144MHz
		 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
		 */
		src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);

		/* Unlock the CPU CoreSight interfaces */
		rst = CORESIGHT_UNLOCK;
		writel(rst, CSITE_CPU_DBG0_LAR);
		writel(rst, CSITE_CPU_DBG1_LAR);
		if (get_num_cpus() == 4) {
			writel(rst, CSITE_CPU_DBG2_LAR);
			writel(rst, CSITE_CPU_DBG3_LAR);
		}
	}
}

void halt_avp(void)
{
	for (;;) {
		writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
		       FLOW_CTLR_HALT_COP_EVENTS);
	}
}
Commit	Line	Data
1b245fee	1	/*
b9dd6215	2	* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
1b245fee TW	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <common.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/gp_padctrl.h>
	21	#include <asm/arch/pinmux.h>
	22	#include <asm/arch/tegra.h>
	23	#include <asm/arch-tegra/clk_rst.h>
	24	#include <asm/arch-tegra/pmc.h>
	25	#include <asm/arch-tegra/scu.h>
	26	#include "cpu.h"
	27
1b245fee TW	28	int get_num_cpus(void)
1b245fee TW	29	{
4040ec10 TW	30	struct apb_misc_gp_ctlr *gp;
	31	uint rev;
	32
	33	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
	34	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
	35
	36	switch (rev) {
	37	case CHIPID_TEGRA20:
	38	return 2;
	39	break;
	40	case CHIPID_TEGRA30:
	41	case CHIPID_TEGRA114:
	42	default:
	43	return 4;
	44	break;
	45	}
1b245fee TW	46	}
	47
	48	/*
	49	* Timing tables for each SOC for all four oscillator options.
	50	*/
	51	struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
44de8e22 JZ	52	/*
	53	* T20: 1 GHz
	54	*
	55	* Register Field Bits Width
	56	* ------------------------------
	57	* PLLX_BASE p 22:20 3
	58	* PLLX_BASE n 17: 8 10
	59	* PLLX_BASE m 4: 0 5
	60	* PLLX_MISC cpcon 11: 8 4
	61	*/
	62	{
	63	{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
	64	{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
	65	{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
	66	{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
1b245fee	67	},
44de8e22 JZ	68	/*
	69	* T25: 1.2 GHz
	70	*
	71	* Register Field Bits Width
	72	* ------------------------------
	73	* PLLX_BASE p 22:20 3
	74	* PLLX_BASE n 17: 8 10
	75	* PLLX_BASE m 4: 0 5
	76	* PLLX_MISC cpcon 11: 8 4
	77	*/
	78	{
	79	{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
	80	{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
	81	{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
	82	{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
1b245fee	83	},
44de8e22	84	/*
2364e151	85	* T30: 600 MHz
44de8e22 JZ	86	*
	87	* Register Field Bits Width
	88	* ------------------------------
	89	* PLLX_BASE p 22:20 3
	90	* PLLX_BASE n 17: 8 10
	91	* PLLX_BASE m 4: 0 5
	92	* PLLX_MISC cpcon 11: 8 4
	93	*/
	94	{
2364e151 SW	95	{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
	96	{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
	97	{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
	98	{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
1b245fee	99	},
44de8e22 JZ	100	/*
	101	* T114: 700 MHz
	102	*
	103	* Register Field Bits Width
	104	* ------------------------------
	105	* PLLX_BASE p 23:20 4
	106	* PLLX_BASE n 15: 8 8
	107	* PLLX_BASE m 7: 0 8
	108	*/
	109	{
	110	{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
	111	{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
	112	{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
	113	{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
4040ec10	114	},
32edd2ed TW	115
	116	/*
	117	* T124: 700 MHz
	118	*
	119	* Register Field Bits Width
	120	* ------------------------------
	121	* PLLX_BASE p 23:20 4
	122	* PLLX_BASE n 15: 8 8
	123	* PLLX_BASE m 7: 0 8
	124	*/
	125	{
	126	{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
	127	{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
	128	{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
	129	{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
	130	},
1b245fee TW	131	};
1b245fee TW	132
32edd2ed TW	133	static inline void pllx_set_iddq(void)
	134	{
	135	#if defined(CONFIG_TEGRA124)
	136	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
	137	u32 reg;
	138
	139	/* Disable IDDQ */
	140	reg = readl(&clkrst->crc_pllx_misc3);
	141	reg &= ~PLLX_IDDQ_MASK;
	142	writel(reg, &clkrst->crc_pllx_misc3);
	143	udelay(2);
	144	debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
	145	readl(&clkrst->crc_pllx_misc3));
	146	#endif
	147	}
	148
1b245fee TW	149	int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
	150	u32 divp, u32 cpcon)
	151	{
4475c775	152	int chip = tegra_get_chip();
1b245fee TW	153	u32 reg;
	154
	155	/* If PLLX is already enabled, just return */
	156	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
	157	debug("pllx_set_rate: PLLX already enabled, returning\n");
	158	return 0;
	159	}
	160
	161	debug(" pllx_set_rate entry\n");
	162
32edd2ed TW	163	pllx_set_iddq();
32edd2ed TW	164
1b245fee TW	165	/* Set BYPASS, m, n and p to PLLX_BASE */
	166	reg = PLL_BYPASS_MASK \| (divm << PLL_DIVM_SHIFT);
	167	reg \|= ((divn << PLL_DIVN_SHIFT) \| (divp << PLL_DIVP_SHIFT));
	168	writel(reg, &pll->pll_base);
	169
	170	/* Set cpcon to PLLX_MISC */
4475c775 TR	171	if (chip == CHIPID_TEGRA20 \|\| chip == CHIPID_TEGRA30)
	172	reg = (cpcon << PLL_CPCON_SHIFT);
	173	else
	174	reg = 0;
1b245fee TW	175
	176	/* Set dccon to PLLX_MISC if freq > 600MHz */
	177	if (divn > 600)
	178	reg \|= (1 << PLL_DCCON_SHIFT);
	179	writel(reg, &pll->pll_misc);
	180
1b245fee	181	/* Disable BYPASS */
41447fb2	182	reg = readl(&pll->pll_base);
1b245fee TW	183	reg &= ~PLL_BYPASS_MASK;
1b245fee TW	184	writel(reg, &pll->pll_base);
41447fb2	185	debug("pllx_set_rate: base = 0x%08X\n", reg);
1b245fee TW	186
	187	/* Set lock_enable to PLLX_MISC */
	188	reg = readl(&pll->pll_misc);
	189	reg \|= PLL_LOCK_ENABLE_MASK;
	190	writel(reg, &pll->pll_misc);
41447fb2 SW	191	debug("pllx_set_rate: misc = 0x%08X\n", reg);
	192
	193	/* Enable PLLX last, once it's all configured */
	194	reg = readl(&pll->pll_base);
	195	reg \|= PLL_ENABLE_MASK;
	196	writel(reg, &pll->pll_base);
	197	debug("pllx_set_rate: base final = 0x%08X\n", reg);
1b245fee TW	198
	199	return 0;
	200	}
	201
	202	void init_pllx(void)
	203	{
	204	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
	205	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
49493cb7	206	int soc_type, sku_info, chip_sku;
1b245fee TW	207	enum clock_osc_freq osc;
	208	struct clk_pll_table *sel;
	209
	210	debug("init_pllx entry\n");
	211
49493cb7 TW	212	/* get SOC (chip) type */
	213	soc_type = tegra_get_chip();
	214	debug(" init_pllx: SoC = 0x%02X\n", soc_type);
	215
	216	/* get SKU info */
	217	sku_info = tegra_get_sku_info();
	218	debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
	219
	220	/* get chip SKU, combo of the above info */
	221	chip_sku = tegra_get_chip_sku();
	222	debug(" init_pllx: Chip SKU = %d\n", chip_sku);
1b245fee TW	223
	224	/* get osc freq */
	225	osc = clock_get_osc_freq();
49493cb7	226	debug(" init_pllx: osc = %d\n", osc);
1b245fee TW	227
1b245fee TW	228	/* set pllx */
49493cb7	229	sel = &tegra_pll_x_table[chip_sku][osc];
1b245fee	230	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
1b245fee TW	231	}
	232
	233	void enable_cpu_clock(int enable)
	234	{
	235	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
	236	u32 clk;
	237
	238	/*
	239	* NOTE:
	240	* Regardless of whether the request is to enable or disable the CPU
	241	* clock, every processor in the CPU complex except the master (CPU 0)
	242	* will have it's clock stopped because the AVP only talks to the
	243	* master.
	244	*/
	245
	246	if (enable) {
	247	/* Initialize PLLX */
	248	init_pllx();
	249
	250	/* Wait until all clocks are stable */
	251	udelay(PLL_STABILIZATION_DELAY);
	252
	253	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
	254	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
	255	}
	256
	257	/*
	258	* Read the register containing the individual CPU clock enables and
	259	* always stop the clocks to CPUs > 0.
	260	*/
	261	clk = readl(&clkrst->crc_clk_cpu_cmplx);
	262	clk \|= 1 << CPU1_CLK_STP_SHIFT;
4040ec10 TW	263	if (get_num_cpus() == 4)
	264	clk \|= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
	265
1b245fee TW	266	/* Stop/Unstop the CPU clock */
	267	clk &= ~CPU0_CLK_STP_MASK;
	268	clk \|= !enable << CPU0_CLK_STP_SHIFT;
	269	writel(clk, &clkrst->crc_clk_cpu_cmplx);
	270
	271	clock_enable(PERIPH_ID_CPU);
	272	}
	273
	274	static int is_cpu_powered(void)
	275	{
	276	struct pmc_ctlr pmc = (struct pmc_ctlr )NV_PA_PMC_BASE;
	277
	278	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
	279	}
	280
	281	static void remove_cpu_io_clamps(void)
	282	{
	283	struct pmc_ctlr pmc = (struct pmc_ctlr )NV_PA_PMC_BASE;
	284	u32 reg;
	285
	286	/* Remove the clamps on the CPU I/O signals */
	287	reg = readl(&pmc->pmc_remove_clamping);
	288	reg \|= CPU_CLMP;
	289	writel(reg, &pmc->pmc_remove_clamping);
	290
	291	/* Give I/O signals time to stabilize */
	292	udelay(IO_STABILIZATION_DELAY);
	293	}
	294
	295	void powerup_cpu(void)
	296	{
	297	struct pmc_ctlr pmc = (struct pmc_ctlr )NV_PA_PMC_BASE;
	298	u32 reg;
	299	int timeout = IO_STABILIZATION_DELAY;
	300
	301	if (!is_cpu_powered()) {
	302	/* Toggle the CPU power state (OFF -> ON) */
	303	reg = readl(&pmc->pmc_pwrgate_toggle);
	304	reg &= PARTID_CP;
	305	reg \|= START_CP;
	306	writel(reg, &pmc->pmc_pwrgate_toggle);
	307
	308	/* Wait for the power to come up */
	309	while (!is_cpu_powered()) {
	310	if (timeout-- == 0)
	311	printf("CPU failed to power up!\n");
	312	else
	313	udelay(10);
	314	}
	315
	316	/*
	317	* Remove the I/O clamps from CPU power partition.
	318	* Recommended only on a Warm boot, if the CPU partition gets
	319	* power gated. Shouldn't cause any harm when called after a
	320	* cold boot according to HW, probably just redundant.
	321	*/
	322	remove_cpu_io_clamps();
	323	}
	324	}
	325
	326	void reset_A9_cpu(int reset)
	327	{
	328	/*
	329	* NOTE: Regardless of whether the request is to hold the CPU in reset
330	* or take it out of reset, every processor in the CPU complex
331	* except the master (CPU 0) will be held in reset because the
332	* AVP only talks to the master. The AVP does not know that there
333	* are multiple processors in the CPU complex.
334	*/
335	int mask = crc_rst_cpu \| crc_rst_de \| crc_rst_debug;
336	int num_cpus = get_num_cpus();
337	int cpu;
338
339	debug("reset_a9_cpu entry\n");
340	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
341	for (cpu = 1; cpu < num_cpus; cpu++)
342	reset_cmplx_set_enable(cpu, mask, 1);
343	reset_cmplx_set_enable(0, mask, reset);
344
345	/* Enable/Disable master CPU reset */
346	reset_set_enable(PERIPH_ID_CPU, reset);
347	}
348
349	void clock_enable_coresight(int enable)
350	{
4040ec10	351	u32 rst, src = 2;
1b245fee TW	352
	353	debug("clock_enable_coresight entry\n");
	354	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
	355	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
	356
	357	if (enable) {
	358	/*
49493cb7	359	* Put CoreSight on PLLP_OUT0 and divide it down as per
32edd2ed	360	* PLLP base frequency based on SoC type (T20/T30+).
49493cb7 TW	361	* Clock divider request would setup CSITE clock as 144MHz
49493cb7 TW	362	* for PLLP base 216MHz and 204MHz for PLLP base 408MHz
1b245fee	363	*/
a4bcd67c	364	src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
1b245fee TW	365	clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
	366
	367	/* Unlock the CPU CoreSight interfaces */
	368	rst = CORESIGHT_UNLOCK;
	369	writel(rst, CSITE_CPU_DBG0_LAR);
	370	writel(rst, CSITE_CPU_DBG1_LAR);
4040ec10 TW	371	if (get_num_cpus() == 4) {
	372	writel(rst, CSITE_CPU_DBG2_LAR);
	373	writel(rst, CSITE_CPU_DBG3_LAR);
	374	}
1b245fee TW	375	}
	376	}
	377
	378	void halt_avp(void)
	379	{
	380	for (;;) {
716ff5ce SW	381	writel(HALT_COP_EVENT_JTAG \| (FLOW_MODE_STOP << 29),
716ff5ce SW	382	FLOW_CTLR_HALT_COP_EVENTS);
1b245fee TW	383	}
1b245fee TW	384	}