[people/ms/u-boot.git] / arch / arm / cpu / arm920t / ks8695 / lowlevel_init.S

/*
 *  lowlevel_init.S - basic hardware initialization for the KS8695 CPU
 *
 *  Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <version.h>
#include <asm/arch/platform.h>

#ifndef CONFIG_SKIP_LOWLEVEL_INIT

/*
 *************************************************************************
 *
 * Handy dandy macros
 *
 *************************************************************************
 */

/* Delay a bit */
.macro DELAY_FOR cycles, reg0
	ldr     \reg0, =\cycles
	subs    \reg0, \reg0, #1
	subne   pc,  pc, #0xc
.endm

/*
 *************************************************************************
 *
 * Some local storage.
 *
 *************************************************************************
 */

/* Should we boot with an interactive console or not */
.globl serial_console

/*
 *************************************************************************
 *
 * Raw hardware initialization code. The important thing is to get
 * SDRAM setup and running. We do some other basic things here too,
 * like getting the PLL set for high speed, and init the LEDs.
 *
 *************************************************************************
 */

.globl lowlevel_init
lowlevel_init:

#if DEBUG
	/*
	 * enable UART for early debug trace
	 */
	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
	mov	r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
	str	r2, [r1]
	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
	mov	r2, #KS8695_UART_LINEC_WLEN8
	str	r2, [r1]		/* 8 data bits, no parity, 1 stop */
	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
	mov	r2, #0x41
	str	r2, [r1]		/* write 'A' */
#endif
#if DEBUG
	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
	mov	r2, #0x42
	str	r2, [r1]
#endif

	/*
	 * remap the memory and flash regions. we want to end up with
	 * ram from address 0, and flash at 32MB.
	 */
	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
	ldr	r2, =0xbfc00040
	str	r2, [r1]		/* large flash map */
	ldr	pc, =(highflash+0x02000000-0x00f00000)	/* jump to high flash address */
highflash:
	ldr	r2, =0x8fe00040
	str	r2, [r1]		/* remap flash range */

	/*
	 * remap the second select region to the 4MB immediately after
	 * the first region. This way if you have a larger flash (say 8Mb)
	 * then you can have it all mapped nicely. Has no effect if you
	 * only have a 4Mb or smaller flash.
	 */
	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
	ldr	r2, =0x9fe40040
	str	r2, [r1]		/* remap flash2 region, contiguous */
	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
	ldr	r2, =0x30000005
	str	r2, [r1]		/* enable both flash selects */

#ifdef CONFIG_CM41xx
	/*
	 * map the second flash chip, using the external IO lines.
	 */
	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
	ldr	r2, =0xafe80b6d
	str	r2, [r1]		/* remap io0 region, contiguous */
	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
	ldr	r2, =0xbfec0b6d
	str	r2, [r1]		/* remap io1 region, contiguous */
	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
	ldr	r2, =0x30050005
	str	r2, [r1]		/* enable second flash */
#endif

	/*
	 * before relocating, we have to setup RAM timing
	 */
	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
#if (PHYS_SDRAM_1_SIZE == 0x02000000)
	ldr	r2, =0x7fc0000e		/* 32MB */
#else
	ldr	r2, =0x3fc0000e		/* 16MB */
#endif
	str	r2, [r1]		/* configure sdram bank0 setup */
	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
	mov	r2, #0
	str	r2, [r1]		/* configure sdram bank1 setup */

	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
	ldr	r2, =0x0000000a
	str	r2, [r1]		/* set RAS/CAS timing */

	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
	ldr	r2, =0x00030000
	str	r2, [r1]		/* send NOP command */
	DELAY_FOR 0x100, r0
	ldr	r2, =0x00010000
	str	r2, [r1]		/* send PRECHARGE-ALL */
	DELAY_FOR 0x100, r0

	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
	ldr	r2, =0x00000020
	str	r2, [r1]		/* set for fast refresh */
	DELAY_FOR 0x100, r0
	ldr	r2, =0x00000190
	str	r2, [r1]		/* set normal refresh timing */

	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
	ldr	r2, =0x00020033
	str	r2, [r1]		/* send mode command */
	DELAY_FOR 0x100, r0
	ldr	r2, =0x01f00000
	str	r2, [r1]		/* enable sdram fifos */

	/*
	 * set pll to top speed
	 */
	ldr	r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
	mov	r2, #0
	str	r2, [r1]		/* set pll clock to 166MHz */

	ldr	r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
	ldr	r2, [r1]		/* Get switch ctrl0 register       */
	and	r2, r2, #0x0fc00000	/* Mask out LED control bits       */
	orr	r2, r2, #0x01800000	/* Set Link/activity/speed actions */
	str	r2, [r1]

#ifdef CONFIG_CM4008
	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
	ldr	r2, =0x0000fe30
	str	r2, [r1]		/* enable LED's as outputs	    */
	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
	ldr	r2, =0x0000fe20
	str	r2, [r1]		/* turn on power LED		    */
#endif
#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
	ldr	r2, [r1]		/* get current GPIO input data	    */
	tst	r2, #0x8		/* check if "erase" depressed	    */
	beq	nobutton
	mov	r2, #0			/* be quiet on boot, no console	    */
	ldr	r1, =serial_console
	str	r2, [r1]
nobutton:
#endif

	add	lr, lr, #0x02000000	/* flash is now mapped high */
	add	ip, ip, #0x02000000	/* this is a hack */
	mov	pc, lr			/* all done, return */

#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
Commit	Line	Data
3a574cbe WD	1	/*
	2	* lowlevel_init.S - basic hardware initialization for the KS8695 CPU
	3	*
	4	* Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
3a574cbe WD	7	*/
	8
	9	#include <config.h>
	10	#include <version.h>
	11	#include <asm/arch/platform.h>
	12
	13	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	14
	15	/*
	16	*************************************************************************
	17	*
	18	* Handy dandy macros
	19	*
	20	*************************************************************************
	21	*/
	22
	23	/* Delay a bit */
	24	.macro DELAY_FOR cycles, reg0
	25	ldr \reg0, =\cycles
	26	subs \reg0, \reg0, #1
	27	subne pc, pc, #0xc
	28	.endm
	29
	30	/*
	31	*************************************************************************
	32	*
	33	* Some local storage.
	34	*
	35	*************************************************************************
	36	*/
	37
	38	/* Should we boot with an interactive console or not */
	39	.globl serial_console
	40
	41	/*
	42	*************************************************************************
	43	*
	44	* Raw hardware initialization code. The important thing is to get
	45	* SDRAM setup and running. We do some other basic things here too,
	46	* like getting the PLL set for high speed, and init the LEDs.
	47	*
	48	*************************************************************************
	49	*/
	50
	51	.globl lowlevel_init
	52	lowlevel_init:
	53
	54	#if DEBUG
	55	/*
	56	* enable UART for early debug trace
	57	*/
	58	ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
bff679dd YV	59	mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
bff679dd YV	60	str r2, [r1]
3a574cbe	61	ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
bff679dd	62	mov r2, #KS8695_UART_LINEC_WLEN8
3a574cbe WD	63	str r2, [r1] /* 8 data bits, no parity, 1 stop */
	64	ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
	65	mov r2, #0x41
	66	str r2, [r1] /* write 'A' */
	67	#endif
	68	#if DEBUG
	69	ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
	70	mov r2, #0x42
	71	str r2, [r1]
	72	#endif
	73
	74	/*
	75	* remap the memory and flash regions. we want to end up with
	76	* ram from address 0, and flash at 32MB.
	77	*/
	78	ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
	79	ldr r2, =0xbfc00040
	80	str r2, [r1] /* large flash map */
	81	ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
	82	highflash:
	83	ldr r2, =0x8fe00040
	84	str r2, [r1] /* remap flash range */
	85
	86	/*
	87	* remap the second select region to the 4MB immediately after
	88	* the first region. This way if you have a larger flash (say 8Mb)
	89	* then you can have it all mapped nicely. Has no effect if you
	90	* only have a 4Mb or smaller flash.
	91	*/
	92	ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
	93	ldr r2, =0x9fe40040
	94	str r2, [r1] /* remap flash2 region, contiguous */
	95	ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
	96	ldr r2, =0x30000005
	97	str r2, [r1] /* enable both flash selects */
	98
	99	#ifdef CONFIG_CM41xx
	100	/*
	101	* map the second flash chip, using the external IO lines.
	102	*/
	103	ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
	104	ldr r2, =0xafe80b6d
	105	str r2, [r1] /* remap io0 region, contiguous */
	106	ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
	107	ldr r2, =0xbfec0b6d
	108	str r2, [r1] /* remap io1 region, contiguous */
	109	ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
	110	ldr r2, =0x30050005
	111	str r2, [r1] /* enable second flash */
	112	#endif
	113
	114	/*
	115	* before relocating, we have to setup RAM timing
	116	*/
	117	ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
	118	#if (PHYS_SDRAM_1_SIZE == 0x02000000)
	119	ldr r2, =0x7fc0000e /* 32MB */
	120	#else
	121	ldr r2, =0x3fc0000e /* 16MB */
	122	#endif
	123	str r2, [r1] /* configure sdram bank0 setup */
	124	ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
	125	mov r2, #0
	126	str r2, [r1] /* configure sdram bank1 setup */
127
128	ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
129	ldr r2, =0x0000000a
130	str r2, [r1] /* set RAS/CAS timing */
131
132	ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
133	ldr r2, =0x00030000
134	str r2, [r1] /* send NOP command */
135	DELAY_FOR 0x100, r0
136	ldr r2, =0x00010000
137	str r2, [r1] /* send PRECHARGE-ALL */
138	DELAY_FOR 0x100, r0
139
140	ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
141	ldr r2, =0x00000020
142	str r2, [r1] /* set for fast refresh */
143	DELAY_FOR 0x100, r0
144	ldr r2, =0x00000190
145	str r2, [r1] /* set normal refresh timing */
146
147	ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
148	ldr r2, =0x00020033
149	str r2, [r1] /* send mode command */
150	DELAY_FOR 0x100, r0
151	ldr r2, =0x01f00000
152	str r2, [r1] /* enable sdram fifos */
153
154	/*
155	* set pll to top speed
156	*/
157	ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
158	mov r2, #0
159	str r2, [r1] /* set pll clock to 166MHz */
160
161	ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
162	ldr r2, [r1] /* Get switch ctrl0 register */
163	and r2, r2, #0x0fc00000 /* Mask out LED control bits */
164	orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
165	str r2, [r1]
166
167	#ifdef CONFIG_CM4008
168	ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
169	ldr r2, =0x0000fe30
170	str r2, [r1] /* enable LED's as outputs */
171	ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
172	ldr r2, =0x0000fe20
173	str r2, [r1] /* turn on power LED */
174	#endif
175	#if defined(CONFIG_CM4008) \|\| defined(CONFIG_CM41xx)
176	ldr r2, [r1] /* get current GPIO input data */
177	tst r2, #0x8 /* check if "erase" depressed */
178	beq nobutton
179	mov r2, #0 /* be quiet on boot, no console */
180	ldr r1, =serial_console
181	str r2, [r1]
182	nobutton:
183	#endif
184
185	add lr, lr, #0x02000000 /* flash is now mapped high */
186	add ip, ip, #0x02000000 /* this is a hack */
187	mov pc, lr /* all done, return */
188
189	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */