[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / at91 / at91sam9260_devices.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>

/*
 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
 * peripheral pins. Good to have if hardware is soldered optionally
 * or in case of SPI no slave is selected. Avoid lines to float
 * needlessly. Use a short local PUP define.
 *
 * Due to errata "TXD floats when CTS is inactive" pullups are always
 * on for TXD pins.
 */
#ifdef CONFIG_AT91_GPIO_PULLUP
# define PUP CONFIG_AT91_GPIO_PULLUP
#else
# define PUP 0
#endif

void at91_serial0_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD0 */
	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP);		/* RXD0 */
	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}

void at91_serial1_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 6, 1);		/* TXD1 */
	at91_set_a_periph(AT91_PIO_PORTB, 7, PUP);		/* RXD1 */
	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}

void at91_serial2_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 8, 1);		/* TXD2 */
	at91_set_a_periph(AT91_PIO_PORTB, 9, PUP);		/* RXD2 */
	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}

void at91_seriald_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);		/* DRXD */
	at91_set_a_periph(AT91_PIO_PORTB, 15, 1);		/* DTXD */
	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}

#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */

	/* Enable clock */
	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
	}
}

void at91_spi1_hw_init(unsigned long cs_mask)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP);	/* SPI1_MISO */
	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP);	/* SPI1_MOSI */
	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP);	/* SPI1_SPCK */

	/* Enable clock */
	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
	}
}
#endif

#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
	/* Enable EMAC clock */
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);

	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* ETXCK_EREFCK */
	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ERXDV */
	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ERX0 */
	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERX1 */
	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* ERXER */
	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ETXEN */
	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ETX0 */
	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ETX1 */
	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* EMDIO */
	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* EMDC */

#ifndef CONFIG_RMII
	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ECRS */
	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECOL */
	at91_set_b_periph(AT91_PIO_PORTA, 25, 0);	/* ERX2 */
	at91_set_b_periph(AT91_PIO_PORTA, 26, 0);	/* ERX3 */
	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ERXCK */
#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
	/*
	 * use PA10, PA11 for ETX2, ETX3.
	 * PA23 and PA24 are for TWI EEPROM
	 */
	at91_set_b_periph(AT91_PIO_PORTA, 10, 0);	/* ETX2 */
	at91_set_b_periph(AT91_PIO_PORTA, 11, 0);	/* ETX3 */
#else
	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* ETX2 */
	at91_set_b_periph(AT91_PIO_PORTA, 24, 0);	/* ETX3 */
#if defined(CONFIG_AT91SAM9G20)
	/* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
#endif
#endif
	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* ETXER */
#endif
}
#endif

#if defined(CONFIG_GENERIC_ATMEL_MCI)
void at91_mci_hw_init(void)
{
	/* Enable mci clock */
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	writel(1 << ATMEL_ID_MCI, &pmc->pcer);

	at91_set_a_periph(AT91_PIO_PORTA, 8, 1);	/* MCCK */
#if defined(CONFIG_ATMEL_MCI_PORTB)
	at91_set_b_periph(AT91_PIO_PORTA, 1, 1);	/* MCCDB */
	at91_set_b_periph(AT91_PIO_PORTA, 0, 1);	/* MCDB0 */
	at91_set_b_periph(AT91_PIO_PORTA, 5, 1);	/* MCDB1 */
	at91_set_b_periph(AT91_PIO_PORTA, 4, 1);	/* MCDB2 */
	at91_set_b_periph(AT91_PIO_PORTA, 3, 1);	/* MCDB3 */
#else
	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);	/* MCCDA */
	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);	/* MCDA0 */
	at91_set_a_periph(AT91_PIO_PORTA, 9, 1);	/* MCDA1 */
	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);	/* MCDA2 */
	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);	/* MCDA3 */
#endif
}
#endif
Commit	Line	Data
7ebafb7e JCPV	1	/*
7ebafb7e JCPV	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
7ebafb7e JCPV	4	* Lead Tech Design <www.leadtechdesign.com>
7ebafb7e JCPV	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
7ebafb7e JCPV	7	*/
	8
	9	#include <common.h>
86592f60	10	#include <asm/io.h>
7ebafb7e JCPV	11	#include <asm/arch/at91_common.h>
	12	#include <asm/arch/at91_pmc.h>
	13	#include <asm/arch/gpio.h>
7ebafb7e	14
7588ad12 RM	15	/*
	16	* if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
	17	* peripheral pins. Good to have if hardware is soldered optionally
	18	* or in case of SPI no slave is selected. Avoid lines to float
	19	* needlessly. Use a short local PUP define.
	20	*
	21	* Due to errata "TXD floats when CTS is inactive" pullups are always
	22	* on for TXD pins.
	23	*/
	24	#ifdef CONFIG_AT91_GPIO_PULLUP
	25	# define PUP CONFIG_AT91_GPIO_PULLUP
	26	#else
	27	# define PUP 0
	28	#endif
	29
1699da62 JCPV	30	void at91_serial0_hw_init(void)
1699da62 JCPV	31	{
9f3fe90f	32	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	33
7f9e8633	34	at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
7588ad12	35	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
9f3fe90f	36	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
1699da62 JCPV	37	}
	38
	39	void at91_serial1_hw_init(void)
	40	{
9f3fe90f	41	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	42
7f9e8633	43	at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
7588ad12	44	at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
9f3fe90f	45	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
1699da62 JCPV	46	}
	47
	48	void at91_serial2_hw_init(void)
	49	{
9f3fe90f	50	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	51
7f9e8633	52	at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
7588ad12	53	at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
9f3fe90f	54	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
1699da62 JCPV	55	}
1699da62 JCPV	56
9f3fe90f	57	void at91_seriald_hw_init(void)
1699da62	58	{
9f3fe90f	59	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	60
7588ad12	61	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
7f9e8633	62	at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
9f3fe90f	63	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
1699da62 JCPV	64	}
1699da62 JCPV	65
9453967e	66	#if defined(CONFIG_HAS_DATAFLASH) \|\| defined(CONFIG_ATMEL_SPI)
7ebafb7e JCPV	67	void at91_spi0_hw_init(unsigned long cs_mask)
7ebafb7e JCPV	68	{
9f3fe90f	69	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	70
7588ad12 RM	71	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
	72	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
	73	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
7ebafb7e JCPV	74
7ebafb7e JCPV	75	/* Enable clock */
9f3fe90f	76	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
7ebafb7e JCPV	77
7ebafb7e JCPV	78	if (cs_mask & (1 << 0)) {
7f9e8633	79	at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
7ebafb7e JCPV	80	}
7ebafb7e JCPV	81	if (cs_mask & (1 << 1)) {
7f9e8633	82	at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
7ebafb7e JCPV	83	}
7ebafb7e JCPV	84	if (cs_mask & (1 << 2)) {
7f9e8633	85	at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
7ebafb7e JCPV	86	}
7ebafb7e JCPV	87	if (cs_mask & (1 << 3)) {
7f9e8633	88	at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
a47492ac JCPV	89	}
a47492ac JCPV	90	if (cs_mask & (1 << 4)) {
7f9e8633	91	at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
a47492ac JCPV	92	}
a47492ac JCPV	93	if (cs_mask & (1 << 5)) {
7f9e8633	94	at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
a47492ac JCPV	95	}
a47492ac JCPV	96	if (cs_mask & (1 << 6)) {
7f9e8633	97	at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
a47492ac JCPV	98	}
a47492ac JCPV	99	if (cs_mask & (1 << 7)) {
7f9e8633	100	at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
7ebafb7e JCPV	101	}
	102	}
	103
	104	void at91_spi1_hw_init(unsigned long cs_mask)
	105	{
9f3fe90f	106	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	107
7588ad12 RM	108	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
	109	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
	110	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
7ebafb7e JCPV	111
7ebafb7e JCPV	112	/* Enable clock */
9f3fe90f	113	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
7ebafb7e JCPV	114
7ebafb7e JCPV	115	if (cs_mask & (1 << 0)) {
7f9e8633	116	at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
7ebafb7e JCPV	117	}
7ebafb7e JCPV	118	if (cs_mask & (1 << 1)) {
7f9e8633	119	at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
7ebafb7e JCPV	120	}
7ebafb7e JCPV	121	if (cs_mask & (1 << 2)) {
7f9e8633	122	at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
7ebafb7e JCPV	123	}
7ebafb7e JCPV	124	if (cs_mask & (1 << 3)) {
b38d634b	125	at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
7ebafb7e	126	}
a47492ac	127	if (cs_mask & (1 << 4)) {
7f9e8633	128	at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
a47492ac JCPV	129	}
a47492ac JCPV	130	if (cs_mask & (1 << 5)) {
7f9e8633	131	at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
a47492ac JCPV	132	}
a47492ac JCPV	133	if (cs_mask & (1 << 6)) {
7f9e8633	134	at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
a47492ac JCPV	135	}
a47492ac JCPV	136	if (cs_mask & (1 << 7)) {
7f9e8633	137	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
a47492ac	138	}
7ebafb7e	139	}
1699da62 JCPV	140	#endif
	141
	142	#ifdef CONFIG_MACB
	143	void at91_macb_hw_init(void)
	144	{
a3dab5d1 MH	145	/* Enable EMAC clock */
	146	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	147	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
	148
7f9e8633 JS	149	at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
	150	at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
	151	at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
	152	at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */
	153	at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */
	154	at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */
	155	at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */
	156	at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */
	157	at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */
	158	at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */
1699da62 JCPV	159
1699da62 JCPV	160	#ifndef CONFIG_RMII
7f9e8633 JS	161	at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */
	162	at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */
	163	at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */
	164	at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */
	165	at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */
9475c63c	166	#if defined(CONFIG_AT91SAM9260EK) \|\| defined(CONFIG_AFEB9260)
1699da62 JCPV	167	/*
	168	* use PA10, PA11 for ETX2, ETX3.
	169	* PA23 and PA24 are for TWI EEPROM
	170	*/
7f9e8633 JS	171	at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */
7f9e8633 JS	172	at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */
1699da62	173	#else
7f9e8633 JS	174	at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
7f9e8633 JS	175	at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
accef431 RM	176	#if defined(CONFIG_AT91SAM9G20)
	177	/* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
	178	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
	179	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
	180	#endif
1699da62	181	#endif
7f9e8633	182	at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
1699da62 JCPV	183	#endif
	184	}
	185	#endif
1592ef85	186
c9abb426	187	#if defined(CONFIG_GENERIC_ATMEL_MCI)
1592ef85 RM	188	void at91_mci_hw_init(void)
1592ef85 RM	189	{
a73267a7 WJ	190	/* Enable mci clock */
	191	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	192	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
	193
1592ef85 RM	194	at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
	195	#if defined(CONFIG_ATMEL_MCI_PORTB)
	196	at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */
	197	at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */
	198	at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */
	199	at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */
	200	at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */
	201	#else
	202	at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */
	203	at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */
	204	at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */
	205	at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */
	206	at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */
	207	#endif
	208	}
	209	#endif