[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / at91 / at91sam9263_devices.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * (C) Copyright 2009-2011
 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 * esd electronic system design gmbh <www.esd.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>

/*
 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
 * peripheral pins. Good to have if hardware is soldered optionally
 * or in case of SPI no slave is selected. Avoid lines to float
 * needlessly. Use a short local PUP define.
 *
 * Due to errata "TXD floats when CTS is inactive" pullups are always
 * on for TXD pins.
 */
#ifdef CONFIG_AT91_GPIO_PULLUP
# define PUP CONFIG_AT91_GPIO_PULLUP
#else
# define PUP 0
#endif

void at91_serial0_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);		/* TXD0 */
	at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);		/* RXD0 */
	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}

void at91_serial1_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
	at91_set_a_periph(AT91_PIO_PORTD, 1, PUP);		/* RXD1 */
	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}

void at91_serial2_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
	at91_set_a_periph(AT91_PIO_PORTD, 3, PUP);		/* RXD2 */
	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}

void at91_seriald_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTC, 30, PUP);		/* DRXD */
	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}

#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_b_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
	at91_set_b_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
	at91_set_b_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */

	/* Enable clock */
	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);

	if (cs_mask & (1 << 0)) {
		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
	}
}

void at91_spi1_hw_init(unsigned long cs_mask)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 12, PUP);	/* SPI1_MISO */
	at91_set_a_periph(AT91_PIO_PORTB, 13, PUP);	/* SPI1_MOSI */
	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);	/* SPI1_SPCK */

	/* Enable clock */
	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
	}
}
#endif

#if defined(CONFIG_GENERIC_ATMEL_MCI)
void at91_mci_hw_init(void)
{
	/* Enable mci clock */
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	writel(1 << ATMEL_ID_MCI1, &pmc->pcer);

	at91_set_a_periph(AT91_PIO_PORTA, 6, PUP);	/* MCI1_CK */

#if defined(CONFIG_ATMEL_MCI_PORTB)
	at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);	/* MCI1_CDB */
	at91_set_a_periph(AT91_PIO_PORTA, 22, PUP);	/* MCI1_DB0 */
	at91_set_a_periph(AT91_PIO_PORTA, 23, PUP);	/* MCI1_DB1 */
	at91_set_a_periph(AT91_PIO_PORTA, 24, PUP);	/* MCI1_DB2 */
	at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);	/* MCI1_DB3 */
#else
	at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);	/* MCI1_CDA */
	at91_set_a_periph(AT91_PIO_PORTA, 8, PUP);	/* MCI1_DA0 */
	at91_set_a_periph(AT91_PIO_PORTA, 9, PUP);	/* MCI1_DA1 */
	at91_set_a_periph(AT91_PIO_PORTA, 10, PUP);	/* MCI1_DA2 */
	at91_set_a_periph(AT91_PIO_PORTA, 11, PUP);	/* MCI1_DA3 */
#endif
}
#endif

#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTE, 21, 0);	/* ETXCK_EREFCK */
	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ERXDV */
	at91_set_a_periph(AT91_PIO_PORTE, 25, 0);	/* ERX0 */
	at91_set_a_periph(AT91_PIO_PORTE, 26, 0);	/* ERX1 */
	at91_set_a_periph(AT91_PIO_PORTE, 27, 0);	/* ERXER */
	at91_set_a_periph(AT91_PIO_PORTE, 28, 0);	/* ETXEN */
	at91_set_a_periph(AT91_PIO_PORTE, 23, 0);	/* ETX0 */
	at91_set_a_periph(AT91_PIO_PORTE, 24, 0);	/* ETX1 */
	at91_set_a_periph(AT91_PIO_PORTE, 30, 0);	/* EMDIO */
	at91_set_a_periph(AT91_PIO_PORTE, 29, 0);	/* EMDC */

#ifndef CONFIG_RMII
	at91_set_a_periph(AT91_PIO_PORTE, 22, 0);	/* ECRS */
	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
#endif
}
#endif

#ifdef CONFIG_USB_OHCI_NEW
void at91_uhp_hw_init(void)
{
	/* Enable VBus on UHP ports */
	at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
	at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
}
#endif

#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CAN_TX */
	at91_set_a_periph(AT91_PIO_PORTA, 14, 1);	/* CAN_RX */

	/* Enable clock */
	writel(1 << ATMEL_ID_CAN, &pmc->pcer);
}
#endif
Commit	Line	Data
7ebafb7e JCPV	1	/*
7ebafb7e JCPV	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
7ebafb7e JCPV	4	* Lead Tech Design <www.leadtechdesign.com>
7ebafb7e JCPV	5	*
1069a5cf	6	* (C) Copyright 2009-2011
45627fce DG	7	* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
	8	* esd electronic system design gmbh <www.esd.eu>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
7ebafb7e JCPV	11	*/
	12
	13	#include <common.h>
1069a5cf	14	#include <asm/io.h>
7ebafb7e JCPV	15	#include <asm/arch/at91_common.h>
7ebafb7e JCPV	16	#include <asm/arch/at91_pmc.h>
ffa280fa XH	17	#include <asm/arch/gpio.h>
	18
	19	/*
	20	* if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
	21	* peripheral pins. Good to have if hardware is soldered optionally
	22	* or in case of SPI no slave is selected. Avoid lines to float
	23	* needlessly. Use a short local PUP define.
	24	*
	25	* Due to errata "TXD floats when CTS is inactive" pullups are always
	26	* on for TXD pins.
	27	*/
	28	#ifdef CONFIG_AT91_GPIO_PULLUP
	29	# define PUP CONFIG_AT91_GPIO_PULLUP
	30	#else
	31	# define PUP 0
	32	#endif
7ebafb7e	33
1699da62 JCPV	34	void at91_serial0_hw_init(void)
1699da62 JCPV	35	{
1069a5cf	36	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	37
7f9e8633	38	at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
ffa280fa	39	at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */
1069a5cf	40	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
1699da62 JCPV	41	}
	42
	43	void at91_serial1_hw_init(void)
	44	{
1069a5cf	45	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	46
7f9e8633	47	at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
ffa280fa	48	at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */
1069a5cf	49	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
1699da62 JCPV	50	}
	51
	52	void at91_serial2_hw_init(void)
	53	{
1069a5cf	54	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	55
7f9e8633	56	at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
ffa280fa	57	at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */
1069a5cf	58	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
1699da62 JCPV	59	}
1699da62 JCPV	60
1069a5cf	61	void at91_seriald_hw_init(void)
1699da62	62	{
1069a5cf	63	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	64
ffa280fa	65	at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */
7f9e8633	66	at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
1069a5cf	67	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
1699da62 JCPV	68	}
1699da62 JCPV	69
1069a5cf	70	#if defined(CONFIG_HAS_DATAFLASH) \|\| defined(CONFIG_ATMEL_SPI)
7ebafb7e JCPV	71	void at91_spi0_hw_init(unsigned long cs_mask)
7ebafb7e JCPV	72	{
1069a5cf	73	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	74
ffa280fa XH	75	at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
	76	at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
	77	at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
7ebafb7e JCPV	78
7ebafb7e JCPV	79	/* Enable clock */
1069a5cf	80	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
7ebafb7e JCPV	81
7ebafb7e JCPV	82	if (cs_mask & (1 << 0)) {
7f9e8633	83	at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
7ebafb7e JCPV	84	}
7ebafb7e JCPV	85	if (cs_mask & (1 << 1)) {
7f9e8633	86	at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
7ebafb7e JCPV	87	}
7ebafb7e JCPV	88	if (cs_mask & (1 << 2)) {
7f9e8633	89	at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
7ebafb7e JCPV	90	}
7ebafb7e JCPV	91	if (cs_mask & (1 << 3)) {
7f9e8633	92	at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
a47492ac JCPV	93	}
a47492ac JCPV	94	if (cs_mask & (1 << 4)) {
7f9e8633	95	at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
a47492ac JCPV	96	}
a47492ac JCPV	97	if (cs_mask & (1 << 5)) {
7f9e8633	98	at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
a47492ac JCPV	99	}
a47492ac JCPV	100	if (cs_mask & (1 << 6)) {
7f9e8633	101	at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
a47492ac JCPV	102	}
a47492ac JCPV	103	if (cs_mask & (1 << 7)) {
7f9e8633	104	at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
7ebafb7e JCPV	105	}
	106	}
	107
	108	void at91_spi1_hw_init(unsigned long cs_mask)
	109	{
1069a5cf	110	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	111
ffa280fa XH	112	at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */
	113	at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */
	114	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */
7ebafb7e JCPV	115
7ebafb7e JCPV	116	/* Enable clock */
1069a5cf	117	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
7ebafb7e JCPV	118
7ebafb7e JCPV	119	if (cs_mask & (1 << 0)) {
7f9e8633	120	at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
7ebafb7e JCPV	121	}
7ebafb7e JCPV	122	if (cs_mask & (1 << 1)) {
7f9e8633	123	at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
7ebafb7e JCPV	124	}
7ebafb7e JCPV	125	if (cs_mask & (1 << 2)) {
7f9e8633	126	at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
7ebafb7e JCPV	127	}
7ebafb7e JCPV	128	if (cs_mask & (1 << 3)) {
7f9e8633	129	at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
a47492ac JCPV	130	}
a47492ac JCPV	131	if (cs_mask & (1 << 4)) {
7f9e8633	132	at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
a47492ac JCPV	133	}
a47492ac JCPV	134	if (cs_mask & (1 << 5)) {
7f9e8633	135	at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
a47492ac JCPV	136	}
a47492ac JCPV	137	if (cs_mask & (1 << 6)) {
7f9e8633	138	at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
a47492ac JCPV	139	}
a47492ac JCPV	140	if (cs_mask & (1 << 7)) {
7f9e8633	141	at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
7ebafb7e JCPV	142	}
7ebafb7e JCPV	143	}
1699da62 JCPV	144	#endif
1699da62 JCPV	145
81724e09 AH	146	#if defined(CONFIG_GENERIC_ATMEL_MCI)
	147	void at91_mci_hw_init(void)
	148	{
	149	/* Enable mci clock */
	150	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	151	writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
	152
	153	at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
	154
	155	#if defined(CONFIG_ATMEL_MCI_PORTB)
	156	at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
	157	at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
	158	at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
	159	at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
	160	at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
	161	#else
	162	at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
	163	at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
	164	at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
	165	at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
	166	at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
	167	#endif
	168	}
	169	#endif
	170
1699da62 JCPV	171	#ifdef CONFIG_MACB
	172	void at91_macb_hw_init(void)
	173	{
7f9e8633 JS	174	at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */
	175	at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */
	176	at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */
	177	at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */
	178	at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */
	179	at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */
	180	at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */
	181	at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */
	182	at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */
	183	at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */
1699da62 JCPV	184
1699da62 JCPV	185	#ifndef CONFIG_RMII
7f9e8633 JS	186	at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */
	187	at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
	188	at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
	189	at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
	190	at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
	191	at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
	192	at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
	193	at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
1699da62 JCPV	194	#endif
	195	}
	196	#endif
	197
	198	#ifdef CONFIG_USB_OHCI_NEW
	199	void at91_uhp_hw_init(void)
	200	{
	201	/* Enable VBus on UHP ports */
7f9e8633 JS	202	at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
7f9e8633 JS	203	at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
1699da62 JCPV	204	}
1699da62 JCPV	205	#endif
45627fce DG	206
	207	#ifdef CONFIG_AT91_CAN
	208	void at91_can_hw_init(void)
	209	{
1069a5cf	210	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	211
7f9e8633 JS	212	at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
7f9e8633 JS	213	at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
45627fce DG	214
45627fce DG	215	/* Enable clock */
1069a5cf	216	writel(1 << ATMEL_ID_CAN, &pmc->pcer);
45627fce DG	217	}
45627fce DG	218	#endif