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dc39ae95 JCPV |
1 | /* |
2 | * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] | |
3 | * | |
4 | * Copyright (C) 2005 David Brownell | |
5 | * Copyright (C) 2005 Ivan Kokshaysky | |
6 | * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
5dca710a | 14 | #include <common.h> |
86592f60 | 15 | #include <asm/io.h> |
dc39ae95 JCPV |
16 | #include <asm/arch/hardware.h> |
17 | #include <asm/arch/at91_pmc.h> | |
18 | #include <asm/arch/clk.h> | |
dc39ae95 | 19 | |
5dca710a RM |
20 | #if !defined(CONFIG_AT91FAMILY) |
21 | # error You need to define CONFIG_AT91FAMILY in your board config! | |
22 | #endif | |
23 | ||
24 | DECLARE_GLOBAL_DATA_PTR; | |
dc39ae95 | 25 | |
dc39ae95 JCPV |
26 | static unsigned long at91_css_to_rate(unsigned long css) |
27 | { | |
28 | switch (css) { | |
0cf0b931 | 29 | case AT91_PMC_MCKR_CSS_SLOW: |
9f3fe90f | 30 | return CONFIG_SYS_AT91_SLOW_CLOCK; |
0cf0b931 | 31 | case AT91_PMC_MCKR_CSS_MAIN: |
5dca710a | 32 | return gd->main_clk_rate_hz; |
0cf0b931 | 33 | case AT91_PMC_MCKR_CSS_PLLA: |
5dca710a | 34 | return gd->plla_rate_hz; |
0cf0b931 | 35 | case AT91_PMC_MCKR_CSS_PLLB: |
5dca710a | 36 | return gd->pllb_rate_hz; |
dc39ae95 JCPV |
37 | } |
38 | ||
39 | return 0; | |
40 | } | |
41 | ||
42 | #ifdef CONFIG_USB_ATMEL | |
43 | static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) | |
44 | { | |
45 | unsigned i, div = 0, mul = 0, diff = 1 << 30; | |
46 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; | |
47 | ||
48 | /* PLL output max 240 MHz (or 180 MHz per errata) */ | |
49 | if (out_freq > 240000000) | |
50 | goto fail; | |
51 | ||
52 | for (i = 1; i < 256; i++) { | |
53 | int diff1; | |
54 | unsigned input, mul1; | |
55 | ||
56 | /* | |
57 | * PLL input between 1MHz and 32MHz per spec, but lower | |
58 | * frequences seem necessary in some cases so allow 100K. | |
59 | * Warning: some newer products need 2MHz min. | |
60 | */ | |
61 | input = main_freq / i; | |
62 | #if defined(CONFIG_AT91SAM9G20) | |
63 | if (input < 2000000) | |
64 | continue; | |
65 | #endif | |
66 | if (input < 100000) | |
67 | continue; | |
68 | if (input > 32000000) | |
69 | continue; | |
70 | ||
71 | mul1 = out_freq / input; | |
72 | #if defined(CONFIG_AT91SAM9G20) | |
73 | if (mul > 63) | |
74 | continue; | |
75 | #endif | |
76 | if (mul1 > 2048) | |
77 | continue; | |
78 | if (mul1 < 2) | |
79 | goto fail; | |
80 | ||
81 | diff1 = out_freq - input * mul1; | |
82 | if (diff1 < 0) | |
83 | diff1 = -diff1; | |
84 | if (diff > diff1) { | |
85 | diff = diff1; | |
86 | div = i; | |
87 | mul = mul1; | |
88 | if (diff == 0) | |
89 | break; | |
90 | } | |
91 | } | |
92 | if (i == 256 && diff > (out_freq >> 5)) | |
93 | goto fail; | |
94 | return ret | ((mul - 1) << 16) | div; | |
95 | fail: | |
96 | return 0; | |
97 | } | |
a1e5f931 | 98 | #endif |
dc39ae95 JCPV |
99 | |
100 | static u32 at91_pll_rate(u32 freq, u32 reg) | |
101 | { | |
102 | unsigned mul, div; | |
103 | ||
104 | div = reg & 0xff; | |
105 | mul = (reg >> 16) & 0x7ff; | |
106 | if (div && mul) { | |
107 | freq /= div; | |
108 | freq *= mul + 1; | |
109 | } else | |
110 | freq = 0; | |
111 | ||
112 | return freq; | |
113 | } | |
dc39ae95 JCPV |
114 | |
115 | int at91_clock_init(unsigned long main_clock) | |
116 | { | |
117 | unsigned freq, mckr; | |
9f3fe90f | 118 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
7c966a8b | 119 | #ifndef CONFIG_SYS_AT91_MAIN_CLOCK |
dc39ae95 JCPV |
120 | unsigned tmp; |
121 | /* | |
122 | * When the bootloader initialized the main oscillator correctly, | |
123 | * there's no problem using the cycle counter. But if it didn't, | |
124 | * or when using oscillator bypass mode, we must be told the speed | |
125 | * of the main clock. | |
126 | */ | |
127 | if (!main_clock) { | |
128 | do { | |
7cedb298 JS |
129 | tmp = readl(&pmc->mcfr); |
130 | } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); | |
131 | tmp &= AT91_PMC_MCFR_MAINF_MASK; | |
9f3fe90f | 132 | main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); |
dc39ae95 JCPV |
133 | } |
134 | #endif | |
5dca710a | 135 | gd->main_clk_rate_hz = main_clock; |
dc39ae95 JCPV |
136 | |
137 | /* report if PLLA is more than mildly overclocked */ | |
5dca710a | 138 | gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); |
dc39ae95 JCPV |
139 | |
140 | #ifdef CONFIG_USB_ATMEL | |
141 | /* | |
142 | * USB clock init: choose 48 MHz PLLB value, | |
143 | * disable 48MHz clock during usb peripheral suspend. | |
144 | * | |
145 | * REVISIT: assumes MCK doesn't derive from PLLB! | |
146 | */ | |
5dca710a | 147 | gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | |
0cf0b931 | 148 | AT91_PMC_PLLBR_USBDIV_2; |
5dca710a | 149 | gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init); |
dc39ae95 JCPV |
150 | #endif |
151 | ||
152 | /* | |
153 | * MCK and CPU derive from one of those primary clocks. | |
154 | * For now, assume this parentage won't change. | |
155 | */ | |
0cf0b931 | 156 | mckr = readl(&pmc->mckr); |
22ee6473 SG |
157 | #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) |
158 | /* plla divisor by 2 */ | |
5dca710a | 159 | gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); |
22ee6473 | 160 | #endif |
5dca710a RM |
161 | gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); |
162 | freq = gd->mck_rate_hz; | |
22ee6473 | 163 | |
0cf0b931 | 164 | freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ |
c3a383f5 | 165 | #if defined(CONFIG_AT91SAM9G20) |
0cf0b931 | 166 | /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ |
5dca710a | 167 | gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? |
0cf0b931 JS |
168 | freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; |
169 | if (mckr & AT91_PMC_MCKR_MDIV_MASK) | |
170 | freq /= 2; /* processor clock division */ | |
22ee6473 | 171 | #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) |
5dca710a | 172 | gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == |
e99056e3 | 173 | (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) |
0cf0b931 JS |
174 | ? freq / 3 |
175 | : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); | |
dc39ae95 | 176 | #else |
5dca710a | 177 | gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); |
dc39ae95 | 178 | #endif |
5dca710a | 179 | gd->cpu_clk_rate_hz = freq; |
dc39ae95 | 180 | |
0cf0b931 | 181 | return 0; |
dc39ae95 | 182 | } |