[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / mxs / mxs.c

/*
 * Freescale i.MX23/i.MX28 common code
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * Based on code from LTIB:
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
void lowlevel_init(void) {}

void reset_cpu(ulong ignored) __attribute__((noreturn));

void reset_cpu(ulong ignored)
{
	struct mxs_rtc_regs *rtc_regs =
		(struct mxs_rtc_regs *)MXS_RTC_BASE;
	struct mxs_lcdif_regs *lcdif_regs =
		(struct mxs_lcdif_regs *)MXS_LCDIF_BASE;

	/*
	 * Shut down the LCD controller as it interferes with BootROM boot mode
	 * pads sampling.
	 */
	writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);

	/* Wait 1 uS before doing the actual watchdog reset */
	writel(1, &rtc_regs->hw_rtc_watchdog);
	writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);

	/* Endless loop, reset will exit from here */
	for (;;)
		;
}

void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
	icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
	dcache_enable();
#endif
}

/*
 * This function will craft a jumptable at 0x0 which will redirect interrupt
 * vectoring to proper location of U-Boot in RAM.
 *
 * The structure of the jumptable will be as follows:
 *  ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
 *  <destination address> ... for each previous ldr, thus also repeated 8 times
 *
 * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
 * offset 0x18 from current value of PC register. Note that PC is already
 * incremented by 4 when computing the offset, so the effective offset is
 * actually 0x20, this the associated <destination address>. Loading the PC
 * register with an address performs a jump to that address.
 */
void mx28_fixup_vt(uint32_t start_addr)
{
	/* ldr pc, [pc, #0x18] */
	const uint32_t ldr_pc = 0xe59ff018;
	/* Jumptable location is 0x0 */
	uint32_t *vt = (uint32_t *)0x0;
	int i;

	for (i = 0; i < 8; i++) {
		/* cppcheck-suppress nullPointer */
		vt[i] = ldr_pc;
		/* cppcheck-suppress nullPointer */
		vt[i + 8] = start_addr + (4 * i);
	}
}

#ifdef	CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
	mx28_fixup_vt(gd->relocaddr);
	return 0;
}
#endif

int arch_cpu_init(void)
{
	struct mxs_clkctrl_regs *clkctrl_regs =
		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
	extern uint32_t _start;

	mx28_fixup_vt((uint32_t)&_start);

	/*
	 * Enable NAND clock
	 */
	/* Clear bypass bit */
	writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
		&clkctrl_regs->hw_clkctrl_clkseq_set);

	/* Set GPMI clock to ref_gpmi / 12 */
	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
		CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);

	udelay(1000);

	/*
	 * Configure GPIO unit
	 */
	mxs_gpio_init();

#ifdef	CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

	return 0;
}

u32 get_cpu_rev(void)
{
	struct mxs_digctl_regs *digctl_regs =
		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;

	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
	case HW_DIGCTL_CHIPID_MX23:
		switch (rev) {
		case 0x0:
		case 0x1:
		case 0x2:
		case 0x3:
		case 0x4:
			return (MXC_CPU_MX23 << 12) | (rev + 0x10);
		default:
			return 0;
		}
	case HW_DIGCTL_CHIPID_MX28:
		switch (rev) {
		case 0x1:
			return (MXC_CPU_MX28 << 12) | 0x12;
		default:
			return 0;
		}
	default:
		return 0;
	}
}

#if defined(CONFIG_DISPLAY_CPUINFO)
const char *get_imx_type(u32 imxtype)
{
	switch (imxtype) {
	case MXC_CPU_MX23:
		return "23";
	case MXC_CPU_MX28:
		return "28";
	default:
		return "??";
	}
}

int print_cpuinfo(void)
{
	u32 cpurev;
	struct mxs_spl_data *data = (struct mxs_spl_data *)
		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);

	cpurev = get_cpu_rev();
	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
		get_imx_type((cpurev & 0xFF000) >> 12),
		(cpurev & 0x000F0) >> 4,
		(cpurev & 0x0000F) >> 0,
		mxc_get_clock(MXC_ARM_CLK) / 1000000);
	printf("BOOT:  %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
	return 0;
}
#endif

int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
	printf("CPU:   %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	printf("BUS:   %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
	printf("EMI:   %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
	printf("GPMI:  %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
	return 0;
}

/*
 * Initializes on-chip ethernet controllers.
 */
#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
int cpu_eth_init(bd_t *bis)
{
	struct mxs_clkctrl_regs *clkctrl_regs =
		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

	/* Turn on ENET clocks */
	clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
		CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);

	/* Set up ENET PLL for 50 MHz */
	/* Power on ENET PLL */
	writel(CLKCTRL_PLL2CTRL0_POWER,
		&clkctrl_regs->hw_clkctrl_pll2ctrl0_set);

	udelay(10);

	/* Gate on ENET PLL */
	writel(CLKCTRL_PLL2CTRL0_CLKGATE,
		&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);

	/* Enable pad output */
	setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);

	return 0;
}
#endif

__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
{
	mac[0] = 0x00;
	mac[1] = 0x04; /* Use FSL vendor MAC address by default */

	if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
		mac[5] += 1;
}

#ifdef	CONFIG_MX28_FEC_MAC_IN_OCOTP

#define	MXS_OCOTP_MAX_TIMEOUT	1000000
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct mxs_ocotp_regs *ocotp_regs =
		(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
	uint32_t data;

	memset(mac, 0, 6);

	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);

	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
				MXS_OCOTP_MAX_TIMEOUT)) {
		printf("MXS FEC: Can't get MAC from OCOTP\n");
		return;
	}

	data = readl(&ocotp_regs->hw_ocotp_cust0);

	mac[2] = (data >> 24) & 0xff;
	mac[3] = (data >> 16) & 0xff;
	mac[4] = (data >> 8) & 0xff;
	mac[5] = data & 0xff;
	mx28_adjust_mac(dev_id, mac);
}
#else
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	memset(mac, 0, 6);
}
#endif

int mxs_dram_init(void)
{
	struct mxs_spl_data *data = (struct mxs_spl_data *)
		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);

	if (data->mem_dram_size == 0) {
		printf("MXS:\n"
			"Error, the RAM size passed up from SPL is 0!\n");
		hang();
	}

	gd->ram_size = data->mem_dram_size;
	return 0;
}

U_BOOT_CMD(
	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
	"display clocks",
	""
);
Commit	Line	Data
6e9a0a39	1	/*
f69077e4	2	* Freescale i.MX23/i.MX28 common code
6e9a0a39 MV	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
	7	* Based on code from LTIB:
	8	* Copyright (C) 2010 Freescale Semiconductor, Inc.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
6e9a0a39 MV	11	*/
	12
	13	#include <common.h>
1221ce45	14	#include <linux/errno.h>
6e9a0a39 MV	15	#include <asm/io.h>
6e9a0a39 MV	16	#include <asm/arch/clock.h>
552a848e	17	#include <asm/mach-imx/dma.h>
6e9a0a39	18	#include <asm/arch/gpio.h>
6b6440de	19	#include <asm/arch/iomux.h>
6e9a0a39 MV	20	#include <asm/arch/imx-regs.h>
6e9a0a39 MV	21	#include <asm/arch/sys_proto.h>
f0930882	22	#include <linux/compiler.h>
6e9a0a39	23
22fe68fb MV	24	DECLARE_GLOBAL_DATA_PTR;
22fe68fb MV	25
6e9a0a39	26	/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
e86c9530	27	void lowlevel_init(void) {}
6e9a0a39 MV	28
	29	void reset_cpu(ulong ignored) __attribute__((noreturn));
	30
	31	void reset_cpu(ulong ignored)
	32	{
9c471142 OS	33	struct mxs_rtc_regs *rtc_regs =
	34	(struct mxs_rtc_regs *)MXS_RTC_BASE;
	35	struct mxs_lcdif_regs *lcdif_regs =
	36	(struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
8d4c759f MV	37
	38	/*
	39	* Shut down the LCD controller as it interferes with BootROM boot mode
	40	* pads sampling.
	41	*/
	42	writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
6e9a0a39 MV	43
	44	/* Wait 1 uS before doing the actual watchdog reset */
	45	writel(1, &rtc_regs->hw_rtc_watchdog);
	46	writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
	47
	48	/* Endless loop, reset will exit from here */
	49	for (;;)
	50	;
	51	}
	52
345cd358 MV	53	void enable_caches(void)
	54	{
	55	#ifndef CONFIG_SYS_ICACHE_OFF
	56	icache_enable();
	57	#endif
	58	#ifndef CONFIG_SYS_DCACHE_OFF
	59	dcache_enable();
	60	#endif
	61	}
	62
86fb7b3d MV	63	/*
	64	* This function will craft a jumptable at 0x0 which will redirect interrupt
	65	* vectoring to proper location of U-Boot in RAM.
	66	*
	67	* The structure of the jumptable will be as follows:
	68	* ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
	69	* <destination address> ... for each previous ldr, thus also repeated 8 times
	70	*
	71	* The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
	72	* offset 0x18 from current value of PC register. Note that PC is already
	73	* incremented by 4 when computing the offset, so the effective offset is
	74	* actually 0x20, this the associated <destination address>. Loading the PC
	75	* register with an address performs a jump to that address.
	76	*/
22fe68fb MV	77	void mx28_fixup_vt(uint32_t start_addr)
22fe68fb MV	78	{
86fb7b3d MV	79	/* ldr pc, [pc, #0x18] */
	80	const uint32_t ldr_pc = 0xe59ff018;
	81	/* Jumptable location is 0x0 */
	82	uint32_t vt = (uint32_t )0x0;
22fe68fb MV	83	int i;
22fe68fb MV	84
86fb7b3d	85	for (i = 0; i < 8; i++) {
0060517a	86	/* cppcheck-suppress nullPointer */
86fb7b3d	87	vt[i] = ldr_pc;
0060517a	88	/* cppcheck-suppress nullPointer */
86fb7b3d MV	89	vt[i + 8] = start_addr + (4 * i);
86fb7b3d MV	90	}
22fe68fb MV	91	}
	92
	93	#ifdef CONFIG_ARCH_MISC_INIT
	94	int arch_misc_init(void)
	95	{
	96	mx28_fixup_vt(gd->relocaddr);
	97	return 0;
	98	}
	99	#endif
	100
6e9a0a39 MV	101	int arch_cpu_init(void)
6e9a0a39 MV	102	{
9c471142 OS	103	struct mxs_clkctrl_regs *clkctrl_regs =
9c471142 OS	104	(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
22fe68fb MV	105	extern uint32_t _start;
	106
	107	mx28_fixup_vt((uint32_t)&_start);
6e9a0a39 MV	108
	109	/*
	110	* Enable NAND clock
	111	*/
	112	/* Clear bypass bit */
	113	writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
	114	&clkctrl_regs->hw_clkctrl_clkseq_set);
	115
	116	/* Set GPMI clock to ref_gpmi / 12 */
	117	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
	118	CLKCTRL_GPMI_CLKGATE \| CLKCTRL_GPMI_DIV_MASK, 1);
	119
	120	udelay(1000);
	121
6b6440de MV	122	/*
	123	* Configure GPIO unit
	124	*/
	125	mxs_gpio_init();
	126
96666a39 MV	127	#ifdef CONFIG_APBH_DMA
	128	/* Start APBH DMA */
	129	mxs_dma_init();
	130	#endif
	131
6e9a0a39 MV	132	return 0;
6e9a0a39 MV	133	}
6e9a0a39	134
bf3b9cb6	135	u32 get_cpu_rev(void)
b0261b12	136	{
9c471142 OS	137	struct mxs_digctl_regs *digctl_regs =
9c471142 OS	138	(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
b0261b12 OS	139	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
	140
	141	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
f69077e4 OS	142	case HW_DIGCTL_CHIPID_MX23:
	143	switch (rev) {
	144	case 0x0:
f69077e4	145	case 0x1:
f69077e4	146	case 0x2:
f69077e4	147	case 0x3:
f69077e4	148	case 0x4:
bf3b9cb6	149	return (MXC_CPU_MX23 << 12) \| (rev + 0x10);
f69077e4	150	default:
bf3b9cb6	151	return 0;
f69077e4	152	}
b0261b12 OS	153	case HW_DIGCTL_CHIPID_MX28:
	154	switch (rev) {
	155	case 0x1:
bf3b9cb6	156	return (MXC_CPU_MX28 << 12) \| 0x12;
b0261b12	157	default:
bf3b9cb6	158	return 0;
b0261b12	159	}
bf3b9cb6 PF	160	default:
	161	return 0;
	162	}
	163	}
	164
	165	#if defined(CONFIG_DISPLAY_CPUINFO)
	166	const char *get_imx_type(u32 imxtype)
	167	{
	168	switch (imxtype) {
	169	case MXC_CPU_MX23:
d2ba7a6a	170	return "23";
bf3b9cb6	171	case MXC_CPU_MX28:
d2ba7a6a	172	return "28";
b0261b12 OS	173	default:
	174	return "??";
	175	}
	176	}
	177
6e9a0a39 MV	178	int print_cpuinfo(void)
6e9a0a39 MV	179	{
bf3b9cb6	180	u32 cpurev;
1e0cf5c3 OS	181	struct mxs_spl_data data = (struct mxs_spl_data )
1e0cf5c3 OS	182	((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
f8c4a86b	183
bf3b9cb6 PF	184	cpurev = get_cpu_rev();
	185	printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
	186	get_imx_type((cpurev & 0xFF000) >> 12),
	187	(cpurev & 0x000F0) >> 4,
	188	(cpurev & 0x0000F) >> 0,
b0261b12	189	mxc_get_clock(MXC_ARM_CLK) / 1000000);
fa7a51cb	190	printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
6e9a0a39 MV	191	return 0;
	192	}
	193	#endif
	194
	195	int do_mx28_showclocks(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	196	{
	197	printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	198	printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
	199	printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
	200	printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
	201	return 0;
	202	}
	203
	204	/*
	205	* Initializes on-chip ethernet controllers.
	206	*/
89ce53ff	207	#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
6e9a0a39 MV	208	int cpu_eth_init(bd_t *bis)
6e9a0a39 MV	209	{
9c471142 OS	210	struct mxs_clkctrl_regs *clkctrl_regs =
9c471142 OS	211	(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
6e9a0a39 MV	212
	213	/* Turn on ENET clocks */
	214	clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
	215	CLKCTRL_ENET_SLEEP \| CLKCTRL_ENET_DISABLE);
	216
	217	/* Set up ENET PLL for 50 MHz */
	218	/* Power on ENET PLL */
	219	writel(CLKCTRL_PLL2CTRL0_POWER,
	220	&clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
	221
	222	udelay(10);
	223
	224	/* Gate on ENET PLL */
	225	writel(CLKCTRL_PLL2CTRL0_CLKGATE,
	226	&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
	227
	228	/* Enable pad output */
	229	setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
	230
	231	return 0;
	232	}
	233	#endif
	234
f0930882	235	__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
5cb525f3 FE	236	{
	237	mac[0] = 0x00;
	238	mac[1] = 0x04; /* Use FSL vendor MAC address by default */
	239
	240	if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
	241	mac[5] += 1;
	242	}
	243
5cb525f3 FE	244	#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
	245
	246	#define MXS_OCOTP_MAX_TIMEOUT 1000000
	247	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
	248	{
9c471142 OS	249	struct mxs_ocotp_regs *ocotp_regs =
9c471142 OS	250	(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
5cb525f3 FE	251	uint32_t data;
	252
	253	memset(mac, 0, 6);
	254
	255	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
	256
fa7a51cb	257	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
5cb525f3 FE	258	MXS_OCOTP_MAX_TIMEOUT)) {
	259	printf("MXS FEC: Can't get MAC from OCOTP\n");
	260	return;
	261	}
	262
	263	data = readl(&ocotp_regs->hw_ocotp_cust0);
	264
	265	mac[2] = (data >> 24) & 0xff;
	266	mac[3] = (data >> 16) & 0xff;
	267	mac[4] = (data >> 8) & 0xff;
	268	mac[5] = data & 0xff;
	269	mx28_adjust_mac(dev_id, mac);
	270	}
	271	#else
	272	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
	273	{
	274	memset(mac, 0, 6);
	275	}
	276	#endif
	277
72f8ebf1	278	int mxs_dram_init(void)
5bcc6a89	279	{
1e0cf5c3 OS	280	struct mxs_spl_data data = (struct mxs_spl_data )
1e0cf5c3 OS	281	((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
5bcc6a89	282
0239c2fb	283	if (data->mem_dram_size == 0) {
72f8ebf1	284	printf("MXS:\n"
0239c2fb	285	"Error, the RAM size passed up from SPL is 0!\n");
5bcc6a89 FE	286	hang();
	287	}
	288
0239c2fb	289	gd->ram_size = data->mem_dram_size;
5bcc6a89 FE	290	return 0;
	291	}
	292
6e9a0a39 MV	293	U_BOOT_CMD(
	294	clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
	295	"display clocks",
	296	""
	297	);