[people/ms/u-boot.git] / arch / arm / cpu / arm946es / start.S

/*
 *  armboot - Startup Code for ARM926EJS CPU-core
 *
 *  Copyright (c) 2003  Texas Instruments
 *
 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
 *
 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:
	b	reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:
	.word undefined_instruction
_software_interrupt:
	.word software_interrupt
_prefetch_abort:
	.word prefetch_abort
_data_abort:
	.word data_abort
_not_used:
	.word not_used
_irq:
	.word irq
_fiq:
	.word fiq

	.balignl 16,0xdeadbeef

_vectors_end:

/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _image_copy_end_ofs
_image_copy_end_ofs:
	.word __image_copy_end - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code(addr_moni)
 *
 * This function relocates the monitor code.
 */
	.globl	relocate_code
relocate_code:
	mov	r6, r0	/* save addr of destination */

	adr	r0, _start
	subs	r9, r6, r0		/* r9 <- relocation offset */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _image_copy_end_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	mov	pc, lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0	/* flush v4 I-cache */
	mcr	p15, 0, r0, c7, c6, 0	/* flush v4 D-cache */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * Go setup Memory and board specific bits prior to relocation.
	 */
	mov	ip, lr		/* perserve link reg across call */
	bl	lowlevel_init	/* go setup memory */
	mov	lr, ip		/* restore link */
	mov	pc, lr		/* back to my caller */
#endif
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	@ carve out a frame on current user stack
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12

	ldr	r2, IRQ_STACK_START_IN
	@ get values for "aborted" pc and cpsr (into parm regs)
	ldmia	r2, {r2 - r3}
	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp		@ save current stack into r0 (param register)
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
	add	r8, sp, #S_PC
	stmdb	r8, {sp, lr}^		@ Calling SP, LR
	str	lr, [r8, #0]		@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]		@ Save CPSR
	str	r0, [r8, #8]		@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]	@ save caller lr in position 0 of saved stack
	mrs	lr, spsr	@ get the spsr
	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
	mov	r13, #MODE_SVC	@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13	@ switch modes, make sure moves will execute
	mov	lr, pc		@ capture return pc
	movs	pc, lr		@ jump to next instruction & switch modes.
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif

# ifdef CONFIG_INTEGRATOR

	/* Satisfied by general board level routine */

#else

	.align	5
.globl reset_cpu
reset_cpu:

	ldr	r1, rstctl1	/* get clkm1 reset ctl */
	mov	r3, #0x0
	strh	r3, [r1]	/* clear it */
	mov	r3, #0x8
	strh	r3, [r1]	/* force dsp+arm reset */
_loop_forever:
	b	_loop_forever

rstctl1:
	.word	0xfffece10

#endif	/* #ifdef CONFIG_INTEGRATOR */
Commit	Line	Data
74f4304e WD	1	/*
	2	* armboot - Startup Code for ARM926EJS CPU-core
	3	*
	4	* Copyright (c) 2003 Texas Instruments
	5	*
	6	* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
	7	*
fa82f871 AA	8	* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
fa82f871 AA	9	* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
792a09eb	10	* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
74f4304e WD	11	* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
74f4304e WD	12	* Copyright (c) 2003 Kshitij <kshitij@ti.com>
57b4bce9	13	* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
74f4304e WD	14	*
	15	* See file CREDITS for list of people who contributed to this
	16	* project.
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License as
	20	* published by the Free Software Foundation; either version 2 of
	21	* the License, or (at your option) any later version.
	22	*
	23	* This program is distributed in the hope that it will be useful,
	24	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	25	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	26	* GNU General Public License for more details.
	27	*
	28	* You should have received a copy of the GNU General Public License
	29	* along with this program; if not, write to the Free Software
	30	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	31	* MA 02111-1307 USA
	32	*/
	33
25ddd1fb	34	#include <asm-offsets.h>
74f4304e WD	35	#include <config.h>
	36	#include <version.h>
	37
	38	/*
	39	*************************************************************************
	40	*
	41	* Jump vector table as in table 3.1 in [1]
	42	*
	43	*************************************************************************
	44	*/
	45
	46
	47	.globl _start
	48	_start:
	49	b reset
	50	ldr pc, _undefined_instruction
	51	ldr pc, _software_interrupt
	52	ldr pc, _prefetch_abort
	53	ldr pc, _data_abort
	54	ldr pc, _not_used
	55	ldr pc, _irq
	56	ldr pc, _fiq
	57
	58	_undefined_instruction:
	59	.word undefined_instruction
	60	_software_interrupt:
	61	.word software_interrupt
	62	_prefetch_abort:
	63	.word prefetch_abort
	64	_data_abort:
	65	.word data_abort
	66	_not_used:
	67	.word not_used
	68	_irq:
	69	.word irq
	70	_fiq:
	71	.word fiq
	72
	73	.balignl 16,0xdeadbeef
	74
3336ca60	75	_vectors_end:
74f4304e WD	76
	77	/*
	78	*************************************************************************
	79	*
	80	* Startup Code (reset vector)
	81	*
	82	* do important init only if we don't start from memory!
	83	* setup Memory and board specific bits prior to relocation.
	84	* relocate armboot to ram
	85	* setup stack
	86	*
	87	*************************************************************************
	88	*/
	89
5a8a87ed	90	.globl _TEXT_BASE
74f4304e	91	_TEXT_BASE:
508611bc BT	92	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	93	.word CONFIG_SPL_TEXT_BASE
	94	#else
14d0a02a	95	.word CONFIG_SYS_TEXT_BASE
508611bc	96	#endif
74f4304e	97
74f4304e WD	98	/*
74f4304e WD	99	* These are defined in the board-specific linker script.
3336ca60 AA	100	* Subtracting _start from them lets the linker put their
	101	* relative position in the executable instead of leaving
	102	* them null.
74f4304e	103	*/
3336ca60 AA	104	.globl _bss_start_ofs
	105	_bss_start_ofs:
	106	.word __bss_start - _start
74f4304e	107
7086e91b BT	108	.globl _image_copy_end_ofs
	109	_image_copy_end_ofs:
	110	.word __image_copy_end - _start
	111
3336ca60 AA	112	.globl _bss_end_ofs
3336ca60 AA	113	_bss_end_ofs:
3929fb0a	114	.word __bss_end - _start
74f4304e	115
f326cbba PYC	116	.globl _end_ofs
	117	_end_ofs:
	118	.word _end - _start
	119
74f4304e WD	120	#ifdef CONFIG_USE_IRQ
	121	/* IRQ stack memory (calculated at run-time) */
	122	.globl IRQ_STACK_START
	123	IRQ_STACK_START:
	124	.word 0x0badc0de
	125
	126	/* IRQ stack memory (calculated at run-time) */
	127	.globl FIQ_STACK_START
	128	FIQ_STACK_START:
	129	.word 0x0badc0de
	130	#endif
	131
5a8a87ed HS	132	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	133	.globl IRQ_STACK_START_IN
	134	IRQ_STACK_START_IN:
	135	.word 0x0badc0de
	136
5a8a87ed HS	137	/*
	138	* the actual reset code
	139	*/
	140
	141	reset:
	142	/*
	143	* set the cpu to SVC32 mode
	144	*/
	145	mrs r0,cpsr
	146	bic r0,r0,#0x1f
	147	orr r0,r0,#0xd3
	148	msr cpsr,r0
	149
	150	/*
	151	* we do sys-critical inits only at reboot,
	152	* not when booting from ram!
	153	*/
	154	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	155	bl cpu_init_crit
	156	#endif
	157
e05e5de7	158	bl _main
5a8a87ed HS	159
	160	/------------------------------------------------------------------------------/
	161
	162	/*
5c6db120	163	* void relocate_code(addr_moni)
5a8a87ed	164	*
959eaa74	165	* This function relocates the monitor code.
5a8a87ed HS	166	*/
	167	.globl relocate_code
	168	relocate_code:
5c6db120	169	mov r6, r0 /* save addr of destination */
5a8a87ed	170
5a8a87ed	171	adr r0, _start
4b3db1cd	172	subs r9, r6, r0 /* r9 <- relocation offset */
e05e5de7	173	beq relocate_done /* skip relocation */
a78fb68f	174	mov r1, r6 /* r1 <- scratch for copy_loop */
7086e91b	175	ldr r3, _image_copy_end_ofs
3336ca60	176	add r2, r0, r3 /* r2 <- source end address */
5a8a87ed	177
5a8a87ed	178	copy_loop:
4b3db1cd BT	179	ldmia r0!, {r10-r11} /* copy from source address [r0] */
4b3db1cd BT	180	stmia r1!, {r10-r11} /* copy to target address [r1] */
da90d4ce AA	181	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	182	blo copy_loop
5a8a87ed	183
401bb30b	184	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	185	/*
	186	* fix .rel.dyn relocations
	187	*/
	188	ldr r0, _TEXT_BASE /* r0 <- Text base */
3336ca60 AA	189	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	190	add r10, r10, r0 /* r10 <- sym table in FLASH */
	191	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	192	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	193	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	194	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
5a8a87ed	195	fixloop:
3336ca60 AA	196	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	197	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	198	ldr r1, [r2, #4]
1f52d89f AB	199	and r7, r1, #0xff
1f52d89f AB	200	cmp r7, #23 /* relative fixup? */
3336ca60	201	beq fixrel
1f52d89f	202	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	203	beq fixabs
	204	/* ignore unknown type of fixup */
	205	b fixnext
	206	fixabs:
	207	/* absolute fix: set location to (offset) symbol value */
	208	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	209	add r1, r10, r1 /* r1 <- address of symbol in table */
	210	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	211	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	212	b fixnext
	213	fixrel:
	214	/* relative fix: increase location by offset */
	215	ldr r1, [r0]
	216	add r1, r1, r9
	217	fixnext:
	218	str r1, [r0]
	219	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
5a8a87ed	220	cmp r2, r3
79e63139	221	blo fixloop
5a8a87ed	222	#endif
5a8a87ed	223
e05e5de7	224	relocate_done:
74f4304e	225
5a8a87ed HS	226	mov pc, lr
5a8a87ed HS	227
3336ca60 AA	228	_rel_dyn_start_ofs:
	229	.word __rel_dyn_start - _start
	230	_rel_dyn_end_ofs:
	231	.word __rel_dyn_end - _start
	232	_dynsym_start_ofs:
	233	.word __dynsym_start - _start
	234
e05e5de7 AA	235	.globl c_runtime_cpu_setup
	236	c_runtime_cpu_setup:
	237
	238	mov pc, lr
	239
74f4304e WD	240	/*
	241	*************************************************************************
	242	*
	243	* CPU_init_critical registers
	244	*
	245	* setup important registers
	246	* setup memory timing
	247	*
	248	*************************************************************************
	249	*/
	250
	251
8fc3bb4b	252	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
74f4304e WD	253	cpu_init_crit:
	254	/*
	255	* flush v4 I/D caches
	256	*/
	257	mov r0, #0
	258	mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
	259	mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
	260
	261	/*
	262	* disable MMU stuff and caches
	263	*/
	264	mrc p15, 0, r0, c1, c0, 0
	265	bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
	266	bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
	267	orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
	268	orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
	269	mcr p15, 0, r0, c1, c0, 0
	270
	271	/*
	272	* Go setup Memory and board specific bits prior to relocation.
	273	*/
	274	mov ip, lr /* perserve link reg across call */
87cb6862	275	bl lowlevel_init /* go setup memory */
74f4304e WD	276	mov lr, ip /* restore link */
74f4304e WD	277	mov pc, lr /* back to my caller */
8fc3bb4b	278	#endif
74f4304e WD	279	/*
	280	*************************************************************************
	281	*
	282	* Interrupt handling
	283	*
	284	*************************************************************************
	285	*/
	286
	287	@
	288	@ IRQ stack frame.
	289	@
	290	#define S_FRAME_SIZE 72
	291
	292	#define S_OLD_R0 68
	293	#define S_PSR 64
	294	#define S_PC 60
	295	#define S_LR 56
	296	#define S_SP 52
	297
	298	#define S_IP 48
	299	#define S_FP 44
	300	#define S_R10 40
	301	#define S_R9 36
	302	#define S_R8 32
	303	#define S_R7 28
	304	#define S_R6 24
	305	#define S_R5 20
	306	#define S_R4 16
	307	#define S_R3 12
	308	#define S_R2 8
	309	#define S_R1 4
	310	#define S_R0 0
	311
	312	#define MODE_SVC 0x13
	313	#define I_BIT 0x80
	314
	315	/*
	316	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	317	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	318	*/
	319
	320	.macro bad_save_user_regs
	321	@ carve out a frame on current user stack
	322	sub sp, sp, #S_FRAME_SIZE
	323	stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
	324
5a8a87ed	325	ldr r2, IRQ_STACK_START_IN
74f4304e WD	326	@ get values for "aborted" pc and cpsr (into parm regs)
	327	ldmia r2, {r2 - r3}
	328	add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
	329	add r5, sp, #S_SP
	330	mov r1, lr
	331	stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
	332	mov r0, sp @ save current stack into r0 (param register)
	333	.endm
	334
	335	.macro irq_save_user_regs
	336	sub sp, sp, #S_FRAME_SIZE
	337	stmia sp, {r0 - r12} @ Calling r0-r12
	338	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
	339	add r8, sp, #S_PC
	340	stmdb r8, {sp, lr}^ @ Calling SP, LR
	341	str lr, [r8, #0] @ Save calling PC
	342	mrs r6, spsr
	343	str r6, [r8, #4] @ Save CPSR
	344	str r0, [r8, #8] @ Save OLD_R0
	345	mov r0, sp
	346	.endm
	347
	348	.macro irq_restore_user_regs
	349	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	350	mov r0, r0
	351	ldr lr, [sp, #S_PC] @ Get PC
	352	add sp, sp, #S_FRAME_SIZE
	353	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	354	.endm
	355
	356	.macro get_bad_stack
5a8a87ed	357	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
74f4304e WD	358
	359	str lr, [r13] @ save caller lr in position 0 of saved stack
	360	mrs lr, spsr @ get the spsr
	361	str lr, [r13, #4] @ save spsr in position 1 of saved stack
	362	mov r13, #MODE_SVC @ prepare SVC-Mode
	363	@ msr spsr_c, r13
	364	msr spsr, r13 @ switch modes, make sure moves will execute
	365	mov lr, pc @ capture return pc
	366	movs pc, lr @ jump to next instruction & switch modes.
	367	.endm
	368
	369	.macro get_irq_stack @ setup IRQ stack
	370	ldr sp, IRQ_STACK_START
	371	.endm
	372
	373	.macro get_fiq_stack @ setup FIQ stack
	374	ldr sp, FIQ_STACK_START
	375	.endm
	376
	377	/*
	378	* exception handlers
	379	*/
	380	.align 5
	381	undefined_instruction:
	382	get_bad_stack
	383	bad_save_user_regs
	384	bl do_undefined_instruction
	385
	386	.align 5
	387	software_interrupt:
	388	get_bad_stack
	389	bad_save_user_regs
	390	bl do_software_interrupt
	391
	392	.align 5
	393	prefetch_abort:
	394	get_bad_stack
	395	bad_save_user_regs
	396	bl do_prefetch_abort
	397
	398	.align 5
	399	data_abort:
	400	get_bad_stack
	401	bad_save_user_regs
	402	bl do_data_abort
	403
	404	.align 5
	405	not_used:
	406	get_bad_stack
	407	bad_save_user_regs
	408	bl do_not_used
	409
	410	#ifdef CONFIG_USE_IRQ
	411
	412	.align 5
	413	irq:
	414	get_irq_stack
	415	irq_save_user_regs
53677ef1	416	bl do_irq
74f4304e WD	417	irq_restore_user_regs
	418
	419	.align 5
	420	fiq:
	421	get_fiq_stack
	422	/* someone ought to write a more effiction fiq_save_user_regs */
	423	irq_save_user_regs
53677ef1	424	bl do_fiq
74f4304e WD	425	irq_restore_user_regs
	426
	427	#else
	428
	429	.align 5
	430	irq:
	431	get_bad_stack
	432	bad_save_user_regs
	433	bl do_irq
	434
	435	.align 5
	436	fiq:
	437	get_bad_stack
	438	bad_save_user_regs
	439	bl do_fiq
	440
	441	#endif
	442
	443	# ifdef CONFIG_INTEGRATOR
	444
	445	/* Satisfied by general board level routine */
	446
	447	#else
	448
	449	.align 5
	450	.globl reset_cpu
	451	reset_cpu:
	452
	453	ldr r1, rstctl1 /* get clkm1 reset ctl */
	454	mov r3, #0x0
	455	strh r3, [r1] /* clear it */
	456	mov r3, #0x8
	457	strh r3, [r1] /* force dsp+arm reset */
	458	_loop_forever:
	459	b _loop_forever
	460
	461	rstctl1:
	462	.word 0xfffece10
	463
	464	#endif /* #ifdef CONFIG_INTEGRATOR */