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Commit | Line | Data |
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5289e83a CN |
1 | /* |
2 | * board.c | |
3 | * | |
4 | * Common board functions for AM33XX based boards | |
5 | * | |
6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
5289e83a CN |
9 | */ |
10 | ||
11 | #include <common.h> | |
d12010b0 | 12 | #include <dm.h> |
973b6638 | 13 | #include <errno.h> |
4119e06d | 14 | #include <ns16550.h> |
47f7bcae | 15 | #include <spl.h> |
5289e83a CN |
16 | #include <asm/arch/cpu.h> |
17 | #include <asm/arch/hardware.h> | |
8a8f084e | 18 | #include <asm/arch/omap.h> |
5289e83a CN |
19 | #include <asm/arch/ddr_defs.h> |
20 | #include <asm/arch/clock.h> | |
3b97152b | 21 | #include <asm/arch/gpio.h> |
8eb16b7f | 22 | #include <asm/arch/mem.h> |
8a8f084e | 23 | #include <asm/arch/mmc_host_def.h> |
db7dd810 | 24 | #include <asm/arch/sys_proto.h> |
5289e83a | 25 | #include <asm/io.h> |
fda35eb9 | 26 | #include <asm/emif.h> |
65d750be | 27 | #include <asm/gpio.h> |
973b6638 TR |
28 | #include <i2c.h> |
29 | #include <miiphy.h> | |
30 | #include <cpsw.h> | |
1221ce45 | 31 | #include <linux/errno.h> |
6a0d803c | 32 | #include <linux/compiler.h> |
7df5cf35 IY |
33 | #include <linux/usb/ch9.h> |
34 | #include <linux/usb/gadget.h> | |
35 | #include <linux/usb/musb.h> | |
36 | #include <asm/omap_musb.h> | |
155d424a | 37 | #include <asm/davinci_rtc.h> |
5289e83a CN |
38 | |
39 | DECLARE_GLOBAL_DATA_PTR; | |
40 | ||
75507d5d | 41 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
4119e06d | 42 | static const struct ns16550_platdata am33xx_serial[] = { |
2f6ed3b8 | 43 | { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, |
1480fdf8 | 44 | # ifdef CONFIG_SYS_NS16550_COM2 |
2f6ed3b8 | 45 | { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, |
1480fdf8 | 46 | # ifdef CONFIG_SYS_NS16550_COM3 |
2f6ed3b8 AF |
47 | { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, |
48 | { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, | |
49 | { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, | |
50 | { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, | |
4119e06d | 51 | # endif |
1480fdf8 | 52 | # endif |
4119e06d SG |
53 | }; |
54 | ||
55 | U_BOOT_DEVICES(am33xx_uarts) = { | |
75507d5d | 56 | { "ns16550_serial", &am33xx_serial[0] }, |
4119e06d | 57 | # ifdef CONFIG_SYS_NS16550_COM2 |
75507d5d | 58 | { "ns16550_serial", &am33xx_serial[1] }, |
4119e06d | 59 | # ifdef CONFIG_SYS_NS16550_COM3 |
75507d5d TR |
60 | { "ns16550_serial", &am33xx_serial[2] }, |
61 | { "ns16550_serial", &am33xx_serial[3] }, | |
62 | { "ns16550_serial", &am33xx_serial[4] }, | |
63 | { "ns16550_serial", &am33xx_serial[5] }, | |
4119e06d SG |
64 | # endif |
65 | # endif | |
66 | }; | |
90345c92 TR |
67 | |
68 | #ifdef CONFIG_DM_GPIO | |
69 | static const struct omap_gpio_platdata am33xx_gpio[] = { | |
70 | { 0, AM33XX_GPIO0_BASE }, | |
71 | { 1, AM33XX_GPIO1_BASE }, | |
72 | { 2, AM33XX_GPIO2_BASE }, | |
73 | { 3, AM33XX_GPIO3_BASE }, | |
74 | #ifdef CONFIG_AM43XX | |
75 | { 4, AM33XX_GPIO4_BASE }, | |
76 | { 5, AM33XX_GPIO5_BASE }, | |
1480fdf8 | 77 | #endif |
90345c92 | 78 | }; |
4119e06d | 79 | |
90345c92 TR |
80 | U_BOOT_DEVICES(am33xx_gpios) = { |
81 | { "gpio_omap", &am33xx_gpio[0] }, | |
82 | { "gpio_omap", &am33xx_gpio[1] }, | |
83 | { "gpio_omap", &am33xx_gpio[2] }, | |
84 | { "gpio_omap", &am33xx_gpio[3] }, | |
85 | #ifdef CONFIG_AM43XX | |
86 | { "gpio_omap", &am33xx_gpio[4] }, | |
87 | { "gpio_omap", &am33xx_gpio[5] }, | |
88 | #endif | |
89 | }; | |
90 | #endif | |
91 | #endif | |
d12010b0 | 92 | |
1480fdf8 | 93 | #ifndef CONFIG_DM_GPIO |
cd8341b7 | 94 | static const struct gpio_bank gpio_bank_am33xx[] = { |
0a9e3405 TR |
95 | { (void *)AM33XX_GPIO0_BASE }, |
96 | { (void *)AM33XX_GPIO1_BASE }, | |
97 | { (void *)AM33XX_GPIO2_BASE }, | |
98 | { (void *)AM33XX_GPIO3_BASE }, | |
cd8341b7 | 99 | #ifdef CONFIG_AM43XX |
0a9e3405 TR |
100 | { (void *)AM33XX_GPIO4_BASE }, |
101 | { (void *)AM33XX_GPIO5_BASE }, | |
cd8341b7 | 102 | #endif |
3b97152b SS |
103 | }; |
104 | ||
105 | const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; | |
d12010b0 SG |
106 | #endif |
107 | ||
876bdd6d | 108 | #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) |
75a23880 | 109 | int cpu_mmc_init(bd_t *bis) |
876bdd6d | 110 | { |
0689a2ef | 111 | int ret; |
75a23880 | 112 | |
e3913f56 | 113 | ret = omap_mmc_init(0, 0, 0, -1, -1); |
0689a2ef TR |
114 | if (ret) |
115 | return ret; | |
116 | ||
e3913f56 | 117 | return omap_mmc_init(1, 0, 0, -1, -1); |
876bdd6d CN |
118 | } |
119 | #endif | |
8a8f084e | 120 | |
7df5cf35 | 121 | /* AM33XX has two MUSB controllers which can be host or gadget */ |
95de1e2f | 122 | #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ |
7df5cf35 IY |
123 | (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) |
124 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; | |
125 | ||
126 | /* USB 2.0 PHY Control */ | |
127 | #define CM_PHY_PWRDN (1 << 0) | |
128 | #define CM_PHY_OTG_PWRDN (1 << 1) | |
129 | #define OTGVDET_EN (1 << 19) | |
130 | #define OTGSESSENDEN (1 << 20) | |
131 | ||
132 | static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) | |
133 | { | |
134 | if (on) { | |
135 | clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, | |
136 | OTGVDET_EN | OTGSESSENDEN); | |
137 | } else { | |
138 | clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); | |
139 | } | |
140 | } | |
141 | ||
142 | static struct musb_hdrc_config musb_config = { | |
143 | .multipoint = 1, | |
144 | .dyn_fifo = 1, | |
145 | .num_eps = 16, | |
146 | .ram_bits = 12, | |
147 | }; | |
148 | ||
149 | #ifdef CONFIG_AM335X_USB0 | |
150 | static void am33xx_otg0_set_phy_power(u8 on) | |
151 | { | |
152 | am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); | |
153 | } | |
154 | ||
155 | struct omap_musb_board_data otg0_board_data = { | |
156 | .set_phy_power = am33xx_otg0_set_phy_power, | |
157 | }; | |
158 | ||
159 | static struct musb_hdrc_platform_data otg0_plat = { | |
160 | .mode = CONFIG_AM335X_USB0_MODE, | |
161 | .config = &musb_config, | |
162 | .power = 50, | |
163 | .platform_ops = &musb_dsps_ops, | |
164 | .board_data = &otg0_board_data, | |
165 | }; | |
166 | #endif | |
167 | ||
168 | #ifdef CONFIG_AM335X_USB1 | |
169 | static void am33xx_otg1_set_phy_power(u8 on) | |
170 | { | |
171 | am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); | |
172 | } | |
173 | ||
174 | struct omap_musb_board_data otg1_board_data = { | |
175 | .set_phy_power = am33xx_otg1_set_phy_power, | |
176 | }; | |
177 | ||
178 | static struct musb_hdrc_platform_data otg1_plat = { | |
179 | .mode = CONFIG_AM335X_USB1_MODE, | |
180 | .config = &musb_config, | |
181 | .power = 50, | |
182 | .platform_ops = &musb_dsps_ops, | |
183 | .board_data = &otg1_board_data, | |
184 | }; | |
185 | #endif | |
186 | #endif | |
187 | ||
188 | int arch_misc_init(void) | |
189 | { | |
190 | #ifdef CONFIG_AM335X_USB0 | |
191 | musb_register(&otg0_plat, &otg0_board_data, | |
81df2bab | 192 | (void *)USB0_OTG_BASE); |
7df5cf35 IY |
193 | #endif |
194 | #ifdef CONFIG_AM335X_USB1 | |
195 | musb_register(&otg1_plat, &otg1_board_data, | |
81df2bab | 196 | (void *)USB1_OTG_BASE); |
7df5cf35 IY |
197 | #endif |
198 | return 0; | |
199 | } | |
49f78365 | 200 | |
d0e6d34d | 201 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
196311dc TR |
202 | /* |
203 | * In the case of non-SPL based booting we'll want to call these | |
204 | * functions a tiny bit later as it will require gd to be set and cleared | |
205 | * and that's not true in s_init in this case so we cannot do it there. | |
206 | */ | |
207 | int board_early_init_f(void) | |
208 | { | |
209 | prcm_init(); | |
210 | set_mux_conf_regs(); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
6a0d803c TR |
215 | /* |
216 | * This function is the place to do per-board things such as ramp up the | |
217 | * MPU clock frequency. | |
218 | */ | |
219 | __weak void am33xx_spl_board_init(void) | |
220 | { | |
52f7d844 SK |
221 | do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); |
222 | do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); | |
6a0d803c TR |
223 | } |
224 | ||
16678eb4 | 225 | #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) |
0660481a | 226 | static void rtc32k_enable(void) |
49f78365 | 227 | { |
155d424a | 228 | struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; |
49f78365 HS |
229 | |
230 | /* | |
231 | * Unlock the RTC's registers. For more details please see the | |
232 | * RTC_SS section of the TRM. In order to unlock we need to | |
233 | * write these specific values (keys) in this order. | |
234 | */ | |
155d424a TR |
235 | writel(RTC_KICK0R_WE, &rtc->kick0r); |
236 | writel(RTC_KICK1R_WE, &rtc->kick1r); | |
49f78365 HS |
237 | |
238 | /* Enable the RTC 32K OSC by setting bits 3 and 6. */ | |
239 | writel((1 << 3) | (1 << 6), &rtc->osc); | |
240 | } | |
16678eb4 | 241 | #endif |
7ea7f689 | 242 | |
0660481a | 243 | static void uart_soft_reset(void) |
7ea7f689 HS |
244 | { |
245 | struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; | |
246 | u32 regval; | |
247 | ||
248 | regval = readl(&uart_base->uartsyscfg); | |
249 | regval |= UART_RESET; | |
250 | writel(regval, &uart_base->uartsyscfg); | |
251 | while ((readl(&uart_base->uartsyssts) & | |
252 | UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) | |
253 | ; | |
254 | ||
255 | /* Disable smart idle */ | |
256 | regval = readl(&uart_base->uartsyscfg); | |
257 | regval |= UART_SMART_IDLE_EN; | |
258 | writel(regval, &uart_base->uartsyscfg); | |
259 | } | |
0660481a HS |
260 | |
261 | static void watchdog_disable(void) | |
262 | { | |
263 | struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; | |
264 | ||
265 | writel(0xAAAA, &wdtimer->wdtwspr); | |
266 | while (readl(&wdtimer->wdtwwps) != 0x0) | |
267 | ; | |
268 | writel(0x5555, &wdtimer->wdtwspr); | |
269 | while (readl(&wdtimer->wdtwwps) != 0x0) | |
270 | ; | |
271 | } | |
0660481a | 272 | |
7ae8350f SG |
273 | #ifdef CONFIG_SPL_BUILD |
274 | void board_init_f(ulong dummy) | |
275 | { | |
276 | board_early_init_f(); | |
277 | sdram_init(); | |
278 | } | |
279 | #endif | |
280 | ||
0660481a HS |
281 | void s_init(void) |
282 | { | |
283 | /* | |
284 | * The ROM will only have set up sufficient pinmux to allow for the | |
285 | * first 4KiB NOR to be read, we must finish doing what we know of | |
286 | * the NOR mux in this space in order to continue. | |
287 | */ | |
288 | #ifdef CONFIG_NOR_BOOT | |
289 | enable_norboot_pin_mux(); | |
0660481a | 290 | #endif |
0660481a | 291 | watchdog_disable(); |
0660481a HS |
292 | set_uart_mux_conf(); |
293 | setup_clocks_for_console(); | |
294 | uart_soft_reset(); | |
16678eb4 | 295 | #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) |
0660481a HS |
296 | /* Enable RTC32K clock */ |
297 | rtc32k_enable(); | |
16678eb4 | 298 | #endif |
0660481a | 299 | } |
d73f38f7 | 300 | #endif |