[people/ms/u-boot.git] / arch / arm / cpu / armv7 / am33xx / emif4.c

/*
 * emif4.c
 *
 * AM33XX emif4 configuration file
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	sdram_init();
#endif

	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size(
			(void *)CONFIG_SYS_SDRAM_BASE,
			CONFIG_MAX_RAM_BANK_SIZE);
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = gd->ram_size;
}


#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_TI81XX
static struct dmm_lisa_map_regs *hw_lisa_map_regs =
				(struct dmm_lisa_map_regs *)DMM_BASE;
#endif
#ifndef CONFIG_TI816X
static struct vtp_reg *vtpreg[2] = {
				(struct vtp_reg *)VTP0_CTRL_ADDR,
				(struct vtp_reg *)VTP1_CTRL_ADDR};
#endif
#ifdef CONFIG_AM33XX
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
#endif
#ifdef CONFIG_AM43XX
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
static struct cm_device_inst *cm_device =
				(struct cm_device_inst *)CM_DEVICE_INST;
#endif

#ifdef CONFIG_TI81XX
void config_dmm(const struct dmm_lisa_map_regs *regs)
{
	enable_dmm_clocks();

	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);

	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
}
#endif

#ifndef CONFIG_TI816X
static void config_vtp(int nr)
{
	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
			&vtpreg[nr]->vtp0ctrlreg);
	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
			&vtpreg[nr]->vtp0ctrlreg);
	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
			&vtpreg[nr]->vtp0ctrlreg);

	/* Poll for READY */
	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
			VTP_CTRL_READY)
		;
}
#endif

void __weak ddr_pll_config(unsigned int ddrpll_m)
{
}

void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
		const struct ddr_data *data, const struct cmd_control *ctrl,
		const struct emif_regs *regs, int nr)
{
	ddr_pll_config(pll);
#ifndef CONFIG_TI816X
	config_vtp(nr);
#endif
	config_cmd_ctrl(ctrl, nr);

	config_ddr_data(data, nr);
#ifdef CONFIG_AM33XX
	config_io_ctrl(ioregs);

	/* Set CKE to be controlled by EMIF/DDR PHY */
	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

#endif
#ifdef CONFIG_AM43XX
	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
	while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
		;

	config_io_ctrl(ioregs);

	/* Set CKE to be controlled by EMIF/DDR PHY */
	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
		/* Allow EMIF to control DDR_RESET */
		writel(0x00000000, &ddrctrl->ddrioctrl);
#endif

	/* Program EMIF instance */
	config_ddr_phy(regs, nr);
	set_sdram_timings(regs, nr);
	if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
		config_sdram_emif4d5(regs, nr);
	else
		config_sdram(regs, nr);
}
#endif
Commit	Line	Data
62d7fe7c CN	1	/*
	2	* emif4.c
	3	*
	4	* AM33XX emif4 configuration file
	5	*
	6	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
62d7fe7c CN	9	*/
	10
	11	#include <common.h>
	12	#include <asm/arch/cpu.h>
	13	#include <asm/arch/ddr_defs.h>
	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/clock.h>
b971dfad	16	#include <asm/arch/sys_proto.h>
62d7fe7c	17	#include <asm/io.h>
fda35eb9	18	#include <asm/emif.h>
62d7fe7c CN	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
62d7fe7c CN	22	int dram_init(void)
62d7fe7c CN	23	{
87acf194 TR	24	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	25	sdram_init();
	26	#endif
	27
62d7fe7c CN	28	/* dram_init must store complete ramsize in gd->ram_size */
	29	gd->ram_size = get_ram_size(
	30	(void *)CONFIG_SYS_SDRAM_BASE,
	31	CONFIG_MAX_RAM_BANK_SIZE);
	32	return 0;
	33	}
	34
	35	void dram_init_banksize(void)
	36	{
	37	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	38	gd->bd->bi_dram[0].size = gd->ram_size;
	39	}
	40
	41
d0e6d34d	42	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
c5c7a7c3	43	#ifdef CONFIG_TI81XX
4fab8d7b MP	44	static struct dmm_lisa_map_regs *hw_lisa_map_regs =
4fab8d7b MP	45	(struct dmm_lisa_map_regs *)DMM_BASE;
c5c7a7c3	46	#endif
dcf846d5	47	#ifndef CONFIG_TI816X
3ba65f97 MP	48	static struct vtp_reg *vtpreg[2] = {
	49	(struct vtp_reg *)VTP0_CTRL_ADDR,
	50	(struct vtp_reg *)VTP1_CTRL_ADDR};
dcf846d5	51	#endif
3ba65f97	52	#ifdef CONFIG_AM33XX
942d3f01	53	static struct ddr_ctrl ddrctrl = (struct ddr_ctrl )DDR_CTRL_ADDR;
3ba65f97	54	#endif
d3daba10 LV	55	#ifdef CONFIG_AM43XX
	56	static struct ddr_ctrl ddrctrl = (struct ddr_ctrl )DDR_CTRL_ADDR;
	57	static struct cm_device_inst *cm_device =
	58	(struct cm_device_inst *)CM_DEVICE_INST;
	59	#endif
942d3f01	60
c5c7a7c3	61	#ifdef CONFIG_TI81XX
4fab8d7b MP	62	void config_dmm(const struct dmm_lisa_map_regs *regs)
	63	{
	64	enable_dmm_clocks();
	65
	66	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
	67	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
	68	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
	69	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
	70
	71	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
	72	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
	73	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
	74	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
	75	}
c5c7a7c3	76	#endif
4fab8d7b	77
dcf846d5	78	#ifndef CONFIG_TI816X
3ba65f97	79	static void config_vtp(int nr)
62d7fe7c	80	{
3ba65f97 MP	81	writel(readl(&vtpreg[nr]->vtp0ctrlreg) \| VTP_CTRL_ENABLE,
	82	&vtpreg[nr]->vtp0ctrlreg);
	83	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
	84	&vtpreg[nr]->vtp0ctrlreg);
	85	writel(readl(&vtpreg[nr]->vtp0ctrlreg) \| VTP_CTRL_START_EN,
	86	&vtpreg[nr]->vtp0ctrlreg);
62d7fe7c CN	87
62d7fe7c CN	88	/* Poll for READY */
3ba65f97	89	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
62d7fe7c CN	90	VTP_CTRL_READY)
	91	;
	92	}
dcf846d5	93	#endif
62d7fe7c	94
94d77fb6 LV	95	void __weak ddr_pll_config(unsigned int ddrpll_m)
	96	{
	97	}
	98
965de8b9	99	void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
c00f69db	100	const struct ddr_data data, const struct cmd_control ctrl,
3ba65f97	101	const struct emif_regs *regs, int nr)
62d7fe7c	102	{
c00f69db	103	ddr_pll_config(pll);
dcf846d5	104	#ifndef CONFIG_TI816X
3ba65f97	105	config_vtp(nr);
dcf846d5	106	#endif
3ba65f97	107	config_cmd_ctrl(ctrl, nr);
62d7fe7c	108
3ba65f97 MP	109	config_ddr_data(data, nr);
3ba65f97 MP	110	#ifdef CONFIG_AM33XX
965de8b9	111	config_io_ctrl(ioregs);
62d7fe7c	112
318f27c9 TR	113	/* Set CKE to be controlled by EMIF/DDR PHY */
318f27c9 TR	114	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
fc46bae2	115
3ba65f97	116	#endif
d3daba10 LV	117	#ifdef CONFIG_AM43XX
d3daba10 LV	118	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
878cae6b	119	while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
d3daba10	120	;
d3daba10 LV	121
	122	config_io_ctrl(ioregs);
	123
	124	/* Set CKE to be controlled by EMIF/DDR PHY */
	125	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
fc46bae2	126
7c352cd3 TR	127	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
	128	/* Allow EMIF to control DDR_RESET */
	129	writel(0x00000000, &ddrctrl->ddrioctrl);
d3daba10 LV	130	#endif
d3daba10 LV	131
318f27c9	132	/* Program EMIF instance */
3ba65f97 MP	133	config_ddr_phy(regs, nr);
3ba65f97 MP	134	set_sdram_timings(regs, nr);
d3daba10 LV	135	if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
	136	config_sdram_emif4d5(regs, nr);
	137	else
	138	config_sdram(regs, nr);
62d7fe7c CN	139	}
62d7fe7c CN	140	#endif