[people/ms/u-boot.git] / arch / arm / cpu / armv7 / am33xx / sys_info.c

/*
 * sys_info.c
 *
 * System information functions
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <power/tps65910.h>

struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;

/**
 * get_cpu_rev(void) - extract rev info
 */
u32 get_cpu_rev(void)
{
	u32 id;
	u32 rev;

	id = readl(DEVICE_ID);
	rev = (id >> 28) & 0xff;

	return rev;
}

/**
 * get_cpu_type(void) - extract cpu info
 */
u32 get_cpu_type(void)
{
	u32 id = 0;
	u32 partnum;

	id = readl(DEVICE_ID);
	partnum = (id >> 12) & 0xffff;

	return partnum;
}

/**
 * get_board_rev() - setup to pass kernel board revision information
 * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
 */
u32 get_board_rev(void)
{
	return BOARD_REV_ID;
}

/**
 * get_device_type(): tell if GP/HS/EMU/TST
 */
u32 get_device_type(void)
{
	int mode;
	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
	return mode >>= 8;
}

/**
 * get_sysboot_value(void) - return SYS_BOOT[4:0]
 */
u32 get_sysboot_value(void)
{
	int mode;
	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
	return mode;
}

#ifdef CONFIG_DISPLAY_CPUINFO
static char *cpu_revs[] = {
		"1.0",
		"2.0",
		"2.1"};


static char *dev_types[] = {
		"TST",
		"EMU",
		"HS",
		"GP"};

/**
 * Print CPU information
 */
int print_cpuinfo(void)
{
	char *cpu_s, *sec_s, *rev_s;

	switch (get_cpu_type()) {
	case AM335X:
		cpu_s = "AM335X";
		break;
	case TI81XX:
		cpu_s = "TI81XX";
		break;
	default:
		cpu_s = "Unknown CPU type";
		break;
	}

	if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
		rev_s = cpu_revs[get_cpu_rev()];
	else
		rev_s = "?";

	if (get_device_type() < ARRAY_SIZE(dev_types))
		sec_s = dev_types[get_device_type()];
	else
		sec_s = "?";

	printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);

	return 0;
}
#endif	/* CONFIG_DISPLAY_CPUINFO */

#ifdef CONFIG_AM33XX
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
{
	int sil_rev;

	sil_rev = readl(&cdev->deviceid) >> 28;

	if (sil_rev == 1)
		/* PG 2.0, efuse may not be set. */
		return MPUPLL_M_800;
	else if (sil_rev >= 2) {
		/* Check what the efuse says our max speed is. */
		int efuse_arm_mpu_max_freq;
		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
		case AM335X_ZCZ_1000:
			return MPUPLL_M_1000;
		case AM335X_ZCZ_800:
			return MPUPLL_M_800;
		case AM335X_ZCZ_720:
			return MPUPLL_M_720;
		case AM335X_ZCZ_600:
		case AM335X_ZCE_600:
			return MPUPLL_M_600;
		case AM335X_ZCZ_300:
		case AM335X_ZCE_300:
			return MPUPLL_M_300;
		}
	}

	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
	return MPUPLL_M_720;
}

int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
{
	/* For PG2.1 and later, we have one set of values. */
	if (sil_rev >= 2) {
		switch (frequency) {
		case MPUPLL_M_1000:
			return TPS65910_OP_REG_SEL_1_3_2_5;
		case MPUPLL_M_800:
			return TPS65910_OP_REG_SEL_1_2_6;
		case MPUPLL_M_720:
			return TPS65910_OP_REG_SEL_1_2_0;
		case MPUPLL_M_600:
		case MPUPLL_M_300:
			return TPS65910_OP_REG_SEL_1_1_3;
		}
	}

	/* Default to PG1.0/PG2.0 values. */
	return TPS65910_OP_REG_SEL_1_1_3;
}
#endif
Commit	Line	Data
5655108a CN	1	/*
	2	* sys_info.c
	3	*
	4	* System information functions
	5	*
	6	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
5655108a CN	13	*/
	14
	15	#include <common.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/sys_proto.h>
	18	#include <asm/arch/cpu.h>
	19	#include <asm/arch/clock.h>
9721027a	20	#include <power/tps65910.h>
5655108a CN	21
	22	struct ctrl_stat cstat = (struct ctrl_stat )CTRL_BASE;
	23
	24	/**
	25	* get_cpu_rev(void) - extract rev info
	26	*/
	27	u32 get_cpu_rev(void)
	28	{
	29	u32 id;
	30	u32 rev;
	31
	32	id = readl(DEVICE_ID);
	33	rev = (id >> 28) & 0xff;
	34
	35	return rev;
	36	}
	37
	38	/**
	39	* get_cpu_type(void) - extract cpu info
	40	*/
	41	u32 get_cpu_type(void)
	42	{
	43	u32 id = 0;
	44	u32 partnum;
	45
	46	id = readl(DEVICE_ID);
	47	partnum = (id >> 12) & 0xffff;
	48
	49	return partnum;
	50	}
	51
	52	/**
	53	* get_board_rev() - setup to pass kernel board revision information
	54	* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
	55	*/
	56	u32 get_board_rev(void)
	57	{
	58	return BOARD_REV_ID;
	59	}
	60
	61	/**
	62	* get_device_type(): tell if GP/HS/EMU/TST
	63	*/
	64	u32 get_device_type(void)
	65	{
	66	int mode;
	67	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
	68	return mode >>= 8;
	69	}
	70
	71	/**
	72	* get_sysboot_value(void) - return SYS_BOOT[4:0]
	73	*/
	74	u32 get_sysboot_value(void)
	75	{
	76	int mode;
	77	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
	78	return mode;
	79	}
	80
	81	#ifdef CONFIG_DISPLAY_CPUINFO
21254713 SA	82	static char *cpu_revs[] = {
	83	"1.0",
	84	"2.0",
	85	"2.1"};
	86
	87
	88	static char *dev_types[] = {
	89	"TST",
	90	"EMU",
	91	"HS",
	92	"GP"};
	93
5655108a CN	94	/**
	95	* Print CPU information
	96	*/
	97	int print_cpuinfo(void)
	98	{
21254713	99	char cpu_s, sec_s, *rev_s;
5655108a CN	100
	101	switch (get_cpu_type()) {
	102	case AM335X:
	103	cpu_s = "AM335X";
	104	break;
8b029f22 MP	105	case TI81XX:
	106	cpu_s = "TI81XX";
	107	break;
5655108a	108	default:
21254713	109	cpu_s = "Unknown CPU type";
5655108a CN	110	break;
	111	}
	112
21254713 SA	113	if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
	114	rev_s = cpu_revs[get_cpu_rev()];
	115	else
	116	rev_s = "?";
	117
	118	if (get_device_type() < ARRAY_SIZE(dev_types))
	119	sec_s = dev_types[get_device_type()];
	120	else
5655108a	121	sec_s = "?";
5655108a	122
21254713	123	printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
5655108a CN	124
	125	return 0;
	126	}
	127	#endif /* CONFIG_DISPLAY_CPUINFO */
9721027a TR	128
	129	#ifdef CONFIG_AM33XX
	130	int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
	131	{
	132	int sil_rev;
	133
	134	sil_rev = readl(&cdev->deviceid) >> 28;
	135
	136	if (sil_rev == 1)
	137	/* PG 2.0, efuse may not be set. */
	138	return MPUPLL_M_800;
	139	else if (sil_rev >= 2) {
	140	/* Check what the efuse says our max speed is. */
	141	int efuse_arm_mpu_max_freq;
	142	efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
	143	switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
	144	case AM335X_ZCZ_1000:
	145	return MPUPLL_M_1000;
	146	case AM335X_ZCZ_800:
	147	return MPUPLL_M_800;
	148	case AM335X_ZCZ_720:
	149	return MPUPLL_M_720;
	150	case AM335X_ZCZ_600:
	151	case AM335X_ZCE_600:
	152	return MPUPLL_M_600;
	153	case AM335X_ZCZ_300:
	154	case AM335X_ZCE_300:
	155	return MPUPLL_M_300;
	156	}
	157	}
	158
	159	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
	160	return MPUPLL_M_720;
	161	}
	162
	163	int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
	164	{
	165	/* For PG2.1 and later, we have one set of values. */
	166	if (sil_rev >= 2) {
	167	switch (frequency) {
	168	case MPUPLL_M_1000:
	169	return TPS65910_OP_REG_SEL_1_3_2_5;
	170	case MPUPLL_M_800:
	171	return TPS65910_OP_REG_SEL_1_2_6;
	172	case MPUPLL_M_720:
	173	return TPS65910_OP_REG_SEL_1_2_0;
	174	case MPUPLL_M_600:
	175	case MPUPLL_M_300:
	176	return TPS65910_OP_REG_SEL_1_1_3;
	177	}
	178	}
	179
	180	/* Default to PG1.0/PG2.0 values. */
	181	return TPS65910_OP_REG_SEL_1_1_3;
	182	}
	183	#endif