[people/ms/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / Kconfig

config ARCH_LS1021A
	bool
	select SYS_FSL_ERRATUM_A008378
	select SYS_FSL_ERRATUM_A008407
	select SYS_FSL_ERRATUM_A008997
	select SYS_FSL_ERRATUM_A009007
	select SYS_FSL_ERRATUM_A009008
	select SYS_FSL_ERRATUM_A009663
	select SYS_FSL_ERRATUM_A009798
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010315
	select SYS_FSL_HAS_CCI400
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES
	select SYS_FSL_DDR_BE if SYS_FSL_DDR
	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
	select SYS_FSL_HAS_SEC
	select SYS_FSL_SEC_COMPAT_5
	select SYS_FSL_SEC_LE
	imply SCSI
	imply SCSI_AHCI
	imply CMD_PCI

menu "LS102xA architecture"
	depends on ARCH_LS1021A

config FSL_PCIE_COMPAT
	string "PCIe compatible of Kernel DT"
	depends on PCIE_LAYERSCAPE
	default "fsl,ls1021a-pcie" if ARCH_LS1021A
	help
	  This compatible is used to find pci controller node in Kernel DT
	  to complete fixup.

config LS1_DEEP_SLEEP
	bool "Deep sleep"
	depends on ARCH_LS1021A

config MAX_CPUS
	int "Maximum number of CPUs permitted for LS102xA"
	depends on ARCH_LS1021A
	default 2
	help
	  Set this number to the maximum number of possible CPUs in the SoC.
	  SoCs may have multiple clusters with each cluster may have multiple
	  ports. If some ports are reserved but higher ports are used for
	  cores, count the reserved ports. This will allocate enough memory
	  in spin table to properly handle all cores.

config SECURE_BOOT
	bool	"Secure Boot"
	help
		Enable Freescale Secure Boot feature. Normally selected
		by defconfig. If unsure, do not change.

config SYS_CCI400_OFFSET
	hex "Offset for CCI400 base"
	depends on SYS_FSL_HAS_CCI400
	default 0x180000
	help
	  Offset for CCI400 base.
	  CCI400 base addr = CCSRBAR + CCI400_OFFSET

config SYS_FSL_ERRATUM_A008997
	bool
	help
	  Workaround for USB PHY erratum A008997

config SYS_FSL_ERRATUM_A009007
	bool
	help
	  Workaround for USB PHY erratum A009007

config SYS_FSL_ERRATUM_A009008
	bool
	help
	  Workaround for USB PHY erratum A009008

config SYS_FSL_ERRATUM_A009798
	bool
	help
	  Workaround for USB PHY erratum A009798

config SYS_FSL_ERRATUM_A010315
	bool "Workaround for PCIe erratum A010315"

config SYS_FSL_HAS_CCI400
	bool

config SYS_FSL_SRDS_1
	bool

config SYS_FSL_SRDS_2
	bool

config SYS_HAS_SERDES
	bool

config SYS_FSL_IFC_BANK_COUNT
	int "Maximum banks of Integrated flash controller"
	depends on ARCH_LS1021A
	default 8

config SYS_FSL_ERRATUM_A008407
	bool

endmenu
Commit	Line	Data
0a37cf8f	1	config ARCH_LS1021A
4a444176	2	bool
ba1b6fb5 YS	3	select SYS_FSL_ERRATUM_A008378
ba1b6fb5 YS	4	select SYS_FSL_ERRATUM_A008407
e10d1142	5	select SYS_FSL_ERRATUM_A008997
0e8a4264	6	select SYS_FSL_ERRATUM_A009007
83fa7118	7	select SYS_FSL_ERRATUM_A009008
ba1b6fb5	8	select SYS_FSL_ERRATUM_A009663
c1853f6f	9	select SYS_FSL_ERRATUM_A009798
ba1b6fb5	10	select SYS_FSL_ERRATUM_A009942
0a37cf8f	11	select SYS_FSL_ERRATUM_A010315
63b2316c	12	select SYS_FSL_HAS_CCI400
f534b8f5 YS	13	select SYS_FSL_SRDS_1
f534b8f5 YS	14	select SYS_HAS_SERDES
d26e34c4 YS	15	select SYS_FSL_DDR_BE if SYS_FSL_DDR
	16	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
	17	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
	18	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
2c2e2c9e YS	19	select SYS_FSL_HAS_SEC
2c2e2c9e YS	20	select SYS_FSL_SEC_COMPAT_5
90b80386	21	select SYS_FSL_SEC_LE
fedb428c	22	imply SCSI
9fd95ef0	23	imply SCSI_AHCI
6500ec7a	24	imply CMD_PCI
5e8bd7e1	25
fb2bf8c2 YS	26	menu "LS102xA architecture"
	27	depends on ARCH_LS1021A
	28
19538f30 HZ	29	config FSL_PCIE_COMPAT
	30	string "PCIe compatible of Kernel DT"
	31	depends on PCIE_LAYERSCAPE
	32	default "fsl,ls1021a-pcie" if ARCH_LS1021A
	33	help
	34	This compatible is used to find pci controller node in Kernel DT
	35	to complete fixup.
	36
5e8bd7e1	37	config LS1_DEEP_SLEEP
4a444176 YS	38	bool "Deep sleep"
4a444176 YS	39	depends on ARCH_LS1021A
fb2bf8c2	40
b4b60d06 YS	41	config MAX_CPUS
	42	int "Maximum number of CPUs permitted for LS102xA"
	43	depends on ARCH_LS1021A
	44	default 2
	45	help
	46	Set this number to the maximum number of possible CPUs in the SoC.
	47	SoCs may have multiple clusters with each cluster may have multiple
	48	ports. If some ports are reserved but higher ports are used for
	49	cores, count the reserved ports. This will allocate enough memory
	50	in spin table to properly handle all cores.
	51
72ccd31e YS	52	config SECURE_BOOT
	53	bool "Secure Boot"
	54	help
	55	Enable Freescale Secure Boot feature. Normally selected
	56	by defconfig. If unsure, do not change.
	57
63b2316c AK	58	config SYS_CCI400_OFFSET
	59	hex "Offset for CCI400 base"
	60	depends on SYS_FSL_HAS_CCI400
	61	default 0x180000
	62	help
	63	Offset for CCI400 base.
	64	CCI400 base addr = CCSRBAR + CCI400_OFFSET
	65
e10d1142 RW	66	config SYS_FSL_ERRATUM_A008997
	67	bool
	68	help
	69	Workaround for USB PHY erratum A008997
	70
0e8a4264 RW	71	config SYS_FSL_ERRATUM_A009007
	72	bool
	73	help
	74	Workaround for USB PHY erratum A009007
	75
83fa7118 RW	76	config SYS_FSL_ERRATUM_A009008
	77	bool
	78	help
	79	Workaround for USB PHY erratum A009008
	80
c1853f6f RW	81	config SYS_FSL_ERRATUM_A009798
	82	bool
	83	help
	84	Workaround for USB PHY erratum A009798
	85
fb2bf8c2 YS	86	config SYS_FSL_ERRATUM_A010315
	87	bool "Workaround for PCIe erratum A010315"
	88
63b2316c AK	89	config SYS_FSL_HAS_CCI400
	90	bool
	91
f534b8f5 YS	92	config SYS_FSL_SRDS_1
	93	bool
	94
	95	config SYS_FSL_SRDS_2
	96	bool
	97
	98	config SYS_HAS_SERDES
	99	bool
	100
25af7dc1 YS	101	config SYS_FSL_IFC_BANK_COUNT
	102	int "Maximum banks of Integrated flash controller"
	103	depends on ARCH_LS1021A
	104	default 8
	105
ba1b6fb5 YS	106	config SYS_FSL_ERRATUM_A008407
	107	bool
	108
fb2bf8c2	109	endmenu