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Commit | Line | Data |
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7ba02618 YY |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/arch/clock.h> | |
9 | #include <asm/io.h> | |
b392a6d4 | 10 | #include <asm/arch/fsl_serdes.h> |
7ba02618 YY |
11 | #include <asm/arch/immap_ls102xa.h> |
12 | #include <asm/arch/ls102xa_soc.h> | |
a08b1921 | 13 | #include <asm/arch/ls102xa_stream_id.h> |
341238fd | 14 | #include <fsl_csu.h> |
a08b1921 AW |
15 | |
16 | struct liodn_id_table sec_liodn_tbl[] = { | |
17 | SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), | |
18 | SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), | |
19 | SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), | |
20 | SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), | |
21 | SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), | |
22 | SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), | |
23 | SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), | |
24 | SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), | |
25 | SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), | |
26 | SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), | |
27 | SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), | |
28 | SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), | |
29 | SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), | |
30 | SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), | |
31 | SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), | |
32 | SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), | |
33 | }; | |
34 | ||
35 | struct smmu_stream_id dev_stream_id[] = { | |
36 | { 0x100, 0x01, "ETSEC MAC1" }, | |
37 | { 0x104, 0x02, "ETSEC MAC2" }, | |
38 | { 0x108, 0x03, "ETSEC MAC3" }, | |
39 | { 0x10c, 0x04, "PEX1" }, | |
40 | { 0x110, 0x05, "PEX2" }, | |
41 | { 0x114, 0x06, "qDMA" }, | |
42 | { 0x118, 0x07, "SATA" }, | |
43 | { 0x11c, 0x08, "USB3" }, | |
44 | { 0x120, 0x09, "QE" }, | |
45 | { 0x124, 0x0a, "eSDHC" }, | |
46 | { 0x128, 0x0b, "eMA" }, | |
47 | { 0x14c, 0x0c, "2D-ACE" }, | |
48 | { 0x150, 0x0d, "USB2" }, | |
49 | { 0x18c, 0x0e, "DEBUG" }, | |
50 | }; | |
7ba02618 YY |
51 | |
52 | unsigned int get_soc_major_rev(void) | |
53 | { | |
54 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); | |
55 | unsigned int svr, major; | |
56 | ||
57 | svr = in_be32(&gur->svr); | |
58 | major = SVR_MAJ(svr); | |
59 | ||
60 | return major; | |
61 | } | |
62 | ||
f85a8e8d XY |
63 | void s_init(void) |
64 | { | |
65 | } | |
66 | ||
b392a6d4 HZ |
67 | #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 |
68 | void erratum_a010315(void) | |
69 | { | |
70 | int i; | |
71 | ||
72 | for (i = PCIE1; i <= PCIE2; i++) | |
73 | if (!is_serdes_configured(i)) { | |
74 | debug("PCIe%d: disabled all R/W permission!\n", i); | |
75 | set_pcie_ns_access(i, 0); | |
76 | } | |
77 | } | |
78 | #endif | |
79 | ||
7ba02618 YY |
80 | int arch_soc_init(void) |
81 | { | |
82 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; | |
83 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; | |
84 | unsigned int major; | |
85 | ||
341238fd HZ |
86 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
87 | enable_layerscape_ns_access(); | |
88 | #endif | |
89 | ||
7ba02618 YY |
90 | #ifdef CONFIG_FSL_QSPI |
91 | out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); | |
92 | #endif | |
93 | ||
b215fb3f | 94 | #ifdef CONFIG_VIDEO_FSL_DCU_FB |
7ba02618 YY |
95 | out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); |
96 | #endif | |
97 | ||
98 | /* Configure Little endian for SAI, ASRC and SPDIF */ | |
99 | out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); | |
100 | ||
101 | /* | |
102 | * Enable snoop requests and DVM message requests for | |
0b8bc631 | 103 | * All the slave insterfaces. |
7ba02618 | 104 | */ |
0b8bc631 YY |
105 | out_le32(&cci->slave[0].snoop_ctrl, |
106 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); | |
107 | out_le32(&cci->slave[1].snoop_ctrl, | |
108 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); | |
109 | out_le32(&cci->slave[2].snoop_ctrl, | |
110 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); | |
7ba02618 YY |
111 | out_le32(&cci->slave[4].snoop_ctrl, |
112 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); | |
113 | ||
114 | major = get_soc_major_rev(); | |
115 | if (major == SOC_MAJOR_VER_1_0) { | |
116 | /* | |
117 | * Set CCI-400 Slave interface S1, S2 Shareable Override | |
118 | * Register All transactions are treated as non-shareable | |
119 | */ | |
120 | out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); | |
121 | out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); | |
122 | ||
123 | /* Workaround for the issue that DDR could not respond to | |
124 | * barrier transaction which is generated by executing DSB/ISB | |
125 | * instruction. Set CCI-400 control override register to | |
126 | * terminate the barrier transaction. After DDR is initialized, | |
127 | * allow barrier transaction to DDR again */ | |
128 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); | |
129 | } | |
130 | ||
762b3535 YY |
131 | /* Enable all the snoop signal for various masters */ |
132 | out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | | |
133 | SCFG_SNPCNFGCR_DCU_RD_WR | | |
134 | SCFG_SNPCNFGCR_SATA_RD_WR | | |
135 | SCFG_SNPCNFGCR_USB3_RD_WR | | |
136 | SCFG_SNPCNFGCR_DBG_RD_WR | | |
137 | SCFG_SNPCNFGCR_EDMA_SNP); | |
138 | ||
6c4a1eba YY |
139 | /* |
140 | * Memory controller require a register write before being enabled. | |
141 | * Affects: DDR | |
142 | * Register: EDDRTQCFG | |
143 | * Description: Memory controller performance is not optimal with | |
144 | * default internal target queue register values. | |
145 | * Workaround: Write a value of 63b2_0042h to address: 157_020Ch. | |
146 | */ | |
147 | out_be32(&scfg->eddrtqcfg, 0x63b20042); | |
148 | ||
7ba02618 YY |
149 | return 0; |
150 | } | |
a08b1921 AW |
151 | |
152 | int ls102xa_smmu_stream_id_init(void) | |
153 | { | |
154 | ls1021x_config_caam_stream_id(sec_liodn_tbl, | |
155 | ARRAY_SIZE(sec_liodn_tbl)); | |
156 | ||
157 | ls102xa_config_smmu_stream_id(dev_stream_id, | |
158 | ARRAY_SIZE(dev_stream_id)); | |
159 | ||
160 | return 0; | |
161 | } |