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64fdf452 SB |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Sascha Hauer, Pengutronix | |
4 | * | |
5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
64fdf452 SB |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <asm/arch/imx-regs.h> | |
e4d34492 | 12 | #include <asm/arch/clock.h> |
77f11a99 FE |
13 | #include <asm/arch/sys_proto.h> |
14 | ||
64fdf452 SB |
15 | #include <asm/errno.h> |
16 | #include <asm/io.h> | |
124a06d7 | 17 | #include <asm/imx-common/boot_mode.h> |
64fdf452 | 18 | |
595f3e56 | 19 | #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53)) |
ff9f475d JL |
20 | #error "CPU_TYPE not defined" |
21 | #endif | |
22 | ||
64fdf452 SB |
23 | u32 get_cpu_rev(void) |
24 | { | |
595f3e56 LHR |
25 | #ifdef CONFIG_MX51 |
26 | int system_rev = 0x51000; | |
27 | #else | |
28 | int system_rev = 0x53000; | |
29 | #endif | |
ff9f475d | 30 | int reg = __raw_readl(ROM_SI_REV); |
64fdf452 | 31 | |
595f3e56 | 32 | #if defined(CONFIG_MX51) |
64fdf452 SB |
33 | switch (reg) { |
34 | case 0x02: | |
ff9f475d | 35 | system_rev |= CHIP_REV_1_1; |
64fdf452 SB |
36 | break; |
37 | case 0x10: | |
38 | if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) | |
ff9f475d | 39 | system_rev |= CHIP_REV_2_5; |
64fdf452 | 40 | else |
ff9f475d | 41 | system_rev |= CHIP_REV_2_0; |
64fdf452 SB |
42 | break; |
43 | case 0x20: | |
ff9f475d | 44 | system_rev |= CHIP_REV_3_0; |
64fdf452 | 45 | break; |
64fdf452 | 46 | default: |
ff9f475d | 47 | system_rev |= CHIP_REV_1_0; |
64fdf452 SB |
48 | break; |
49 | } | |
595f3e56 | 50 | #else |
aa1cb689 | 51 | if (reg < 0x20) |
595f3e56 | 52 | system_rev |= CHIP_REV_1_0; |
aa1cb689 FE |
53 | else |
54 | system_rev |= reg; | |
595f3e56 | 55 | #endif |
64fdf452 SB |
56 | return system_rev; |
57 | } | |
58 | ||
11c08d4e FE |
59 | #ifdef CONFIG_REVISION_TAG |
60 | u32 __weak get_board_rev(void) | |
61 | { | |
62 | return get_cpu_rev(); | |
63 | } | |
64 | #endif | |
65 | ||
78ff1a6c BT |
66 | #ifndef CONFIG_SYS_DCACHE_OFF |
67 | void enable_caches(void) | |
68 | { | |
69 | /* Enable D-cache. I-cache is already enabled in start.S */ | |
70 | dcache_enable(); | |
71 | } | |
72 | #endif | |
73 | ||
565e39c5 | 74 | #if defined(CONFIG_FEC_MXC) |
0d8a7499 | 75 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) |
565e39c5 LHR |
76 | { |
77 | int i; | |
78 | struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; | |
79 | struct fuse_bank *bank = &iim->bank[1]; | |
80 | struct fuse_bank1_regs *fuse = | |
81 | (struct fuse_bank1_regs *)bank->fuse_regs; | |
82 | ||
83 | for (i = 0; i < 6; i++) | |
84 | mac[i] = readl(&fuse->mac_addr[i]) & 0xff; | |
85 | } | |
86 | #endif | |
87 | ||
a6e961c2 FE |
88 | void set_chipselect_size(int const cs_size) |
89 | { | |
90 | unsigned int reg; | |
91 | struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
92 | reg = readl(&iomuxc_regs->gpr1); | |
93 | ||
94 | switch (cs_size) { | |
95 | case CS0_128: | |
96 | reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ | |
97 | reg |= 0x5; | |
98 | break; | |
99 | case CS0_64M_CS1_64M: | |
100 | reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ | |
101 | reg |= 0x1B; | |
102 | break; | |
103 | case CS0_64M_CS1_32M_CS2_32M: | |
104 | reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ | |
105 | reg |= 0x4B; | |
106 | break; | |
107 | case CS0_32M_CS1_32M_CS2_32M_CS3_32M: | |
108 | reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ | |
109 | reg |= 0x249; | |
110 | break; | |
111 | default: | |
112 | printf("Unknown chip select size: %d\n", cs_size); | |
113 | break; | |
114 | } | |
115 | ||
116 | writel(reg, &iomuxc_regs->gpr1); | |
117 | } | |
124a06d7 TK |
118 | |
119 | #ifdef CONFIG_MX53 | |
120 | void boot_mode_apply(unsigned cfg_val) | |
121 | { | |
122 | writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr); | |
123 | } | |
124 | /* | |
125 | * cfg_val will be used for | |
126 | * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] | |
127 | * | |
128 | * If bit 28 of LPGR is set upon watchdog reset, | |
129 | * bits[25:0] of LPGR will move to SBMR. | |
130 | */ | |
131 | const struct boot_mode soc_boot_modes[] = { | |
132 | {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, | |
133 | /* usb or serial download */ | |
134 | {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)}, | |
135 | {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)}, | |
136 | {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)}, | |
137 | {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)}, | |
138 | {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)}, | |
139 | {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)}, | |
140 | /* 4 bit bus width */ | |
141 | {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, | |
142 | {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, | |
143 | {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)}, | |
144 | {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)}, | |
145 | {NULL, 0}, | |
146 | }; | |
147 | #endif |