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23608e23 JL |
1 | /* |
2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <asm/io.h> | |
25 | #include <asm/errno.h> | |
26 | #include <asm/arch/imx-regs.h> | |
27 | #include <asm/arch/ccm_regs.h> | |
28 | #include <asm/arch/clock.h> | |
29 | ||
30 | enum pll_clocks { | |
31 | PLL_SYS, /* System PLL */ | |
32 | PLL_BUS, /* System Bus PLL*/ | |
33 | PLL_USBOTG, /* OTG USB PLL */ | |
34 | PLL_ENET, /* ENET PLL */ | |
35 | }; | |
36 | ||
37 | struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR; | |
38 | ||
3f467529 WG |
39 | void enable_usboh3_clk(unsigned char enable) |
40 | { | |
41 | u32 reg; | |
42 | ||
43 | reg = __raw_readl(&imx_ccm->CCGR6); | |
44 | if (enable) | |
45 | reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET; | |
46 | else | |
47 | reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET); | |
48 | __raw_writel(reg, &imx_ccm->CCGR6); | |
49 | ||
50 | } | |
51 | ||
23608e23 JL |
52 | static u32 decode_pll(enum pll_clocks pll, u32 infreq) |
53 | { | |
54 | u32 div; | |
55 | ||
56 | switch (pll) { | |
57 | case PLL_SYS: | |
58 | div = __raw_readl(&imx_ccm->analog_pll_sys); | |
59 | div &= BM_ANADIG_PLL_SYS_DIV_SELECT; | |
60 | ||
61 | return infreq * (div >> 1); | |
62 | case PLL_BUS: | |
63 | div = __raw_readl(&imx_ccm->analog_pll_528); | |
64 | div &= BM_ANADIG_PLL_528_DIV_SELECT; | |
65 | ||
66 | return infreq * (20 + (div << 1)); | |
67 | case PLL_USBOTG: | |
68 | div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); | |
69 | div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; | |
70 | ||
71 | return infreq * (20 + (div << 1)); | |
72 | case PLL_ENET: | |
73 | div = __raw_readl(&imx_ccm->analog_pll_enet); | |
74 | div &= BM_ANADIG_PLL_ENET_DIV_SELECT; | |
75 | ||
76 | return (div == 3 ? 125000000 : 25000000 * (div << 1)); | |
77 | default: | |
78 | return 0; | |
79 | } | |
80 | /* NOTREACHED */ | |
81 | } | |
82 | ||
83 | static u32 get_mcu_main_clk(void) | |
84 | { | |
85 | u32 reg, freq; | |
86 | ||
87 | reg = __raw_readl(&imx_ccm->cacrr); | |
88 | reg &= MXC_CCM_CACRR_ARM_PODF_MASK; | |
89 | reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; | |
90 | freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK); | |
91 | ||
92 | return freq / (reg + 1); | |
93 | } | |
94 | ||
95 | static u32 get_periph_clk(void) | |
96 | { | |
97 | u32 reg, freq = 0; | |
98 | ||
99 | reg = __raw_readl(&imx_ccm->cbcdr); | |
100 | if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { | |
101 | reg = __raw_readl(&imx_ccm->cbcmr); | |
102 | reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; | |
103 | reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET; | |
104 | ||
105 | switch (reg) { | |
106 | case 0: | |
107 | freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK); | |
108 | break; | |
109 | case 1: | |
110 | case 2: | |
111 | freq = CONFIG_SYS_MX6_HCLK; | |
112 | break; | |
113 | default: | |
114 | break; | |
115 | } | |
116 | } else { | |
117 | reg = __raw_readl(&imx_ccm->cbcmr); | |
118 | reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; | |
119 | reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; | |
120 | ||
121 | switch (reg) { | |
122 | case 0: | |
123 | freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK); | |
124 | break; | |
125 | case 1: | |
126 | freq = PLL2_PFD2_FREQ; | |
127 | break; | |
128 | case 2: | |
129 | freq = PLL2_PFD0_FREQ; | |
130 | break; | |
131 | case 3: | |
132 | freq = PLL2_PFD2_DIV_FREQ; | |
133 | break; | |
134 | default: | |
135 | break; | |
136 | } | |
137 | } | |
138 | ||
139 | return freq; | |
140 | } | |
141 | ||
142 | ||
143 | static u32 get_ahb_clk(void) | |
144 | { | |
145 | u32 reg, ahb_podf; | |
146 | ||
147 | reg = __raw_readl(&imx_ccm->cbcdr); | |
148 | reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; | |
149 | ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; | |
150 | ||
151 | return get_periph_clk() / (ahb_podf + 1); | |
152 | } | |
153 | ||
154 | static u32 get_ipg_clk(void) | |
155 | { | |
156 | u32 reg, ipg_podf; | |
157 | ||
158 | reg = __raw_readl(&imx_ccm->cbcdr); | |
159 | reg &= MXC_CCM_CBCDR_IPG_PODF_MASK; | |
160 | ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET; | |
161 | ||
162 | return get_ahb_clk() / (ipg_podf + 1); | |
163 | } | |
164 | ||
165 | static u32 get_ipg_per_clk(void) | |
166 | { | |
167 | u32 reg, perclk_podf; | |
168 | ||
169 | reg = __raw_readl(&imx_ccm->cscmr1); | |
170 | perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; | |
171 | ||
172 | return get_ipg_clk() / (perclk_podf + 1); | |
173 | } | |
174 | ||
175 | static u32 get_uart_clk(void) | |
176 | { | |
177 | u32 reg, uart_podf; | |
178 | ||
179 | reg = __raw_readl(&imx_ccm->cscdr1); | |
180 | reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; | |
181 | uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; | |
182 | ||
183 | return PLL3_80M / (uart_podf + 1); | |
184 | } | |
185 | ||
186 | static u32 get_cspi_clk(void) | |
187 | { | |
188 | u32 reg, cspi_podf; | |
189 | ||
190 | reg = __raw_readl(&imx_ccm->cscdr2); | |
191 | reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; | |
192 | cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; | |
193 | ||
194 | return PLL3_60M / (cspi_podf + 1); | |
195 | } | |
196 | ||
197 | static u32 get_axi_clk(void) | |
198 | { | |
199 | u32 root_freq, axi_podf; | |
200 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
201 | ||
202 | axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK; | |
203 | axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET; | |
204 | ||
205 | if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { | |
206 | if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) | |
207 | root_freq = PLL2_PFD2_FREQ; | |
208 | else | |
209 | root_freq = PLL3_PFD1_FREQ; | |
210 | } else | |
211 | root_freq = get_periph_clk(); | |
212 | ||
213 | return root_freq / (axi_podf + 1); | |
214 | } | |
215 | ||
216 | static u32 get_emi_slow_clk(void) | |
217 | { | |
218 | u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0; | |
219 | ||
220 | cscmr1 = __raw_readl(&imx_ccm->cscmr1); | |
221 | emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; | |
222 | emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; | |
223 | emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; | |
224 | emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; | |
225 | ||
226 | switch (emi_clk_sel) { | |
227 | case 0: | |
228 | root_freq = get_axi_clk(); | |
229 | break; | |
230 | case 1: | |
231 | root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK); | |
232 | break; | |
233 | case 2: | |
234 | root_freq = PLL2_PFD2_FREQ; | |
235 | break; | |
236 | case 3: | |
237 | root_freq = PLL2_PFD0_FREQ; | |
238 | break; | |
239 | } | |
240 | ||
241 | return root_freq / (emi_slow_pof + 1); | |
242 | } | |
243 | ||
244 | static u32 get_mmdc_ch0_clk(void) | |
245 | { | |
246 | u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); | |
247 | u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> | |
248 | MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; | |
249 | ||
250 | return get_periph_clk() / (mmdc_ch0_podf + 1); | |
251 | } | |
252 | ||
253 | static u32 get_usdhc_clk(u32 port) | |
254 | { | |
255 | u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; | |
256 | u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); | |
257 | u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); | |
258 | ||
259 | switch (port) { | |
260 | case 0: | |
261 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> | |
262 | MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; | |
263 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL; | |
264 | ||
265 | break; | |
266 | case 1: | |
267 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> | |
268 | MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; | |
269 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL; | |
270 | ||
271 | break; | |
272 | case 2: | |
273 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> | |
274 | MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; | |
275 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL; | |
276 | ||
277 | break; | |
278 | case 3: | |
279 | usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> | |
280 | MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; | |
281 | clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL; | |
282 | ||
283 | break; | |
284 | default: | |
285 | break; | |
286 | } | |
287 | ||
288 | if (clk_sel) | |
289 | root_freq = PLL2_PFD0_FREQ; | |
290 | else | |
291 | root_freq = PLL2_PFD2_FREQ; | |
292 | ||
293 | return root_freq / (usdhc_podf + 1); | |
294 | } | |
295 | ||
296 | u32 imx_get_uartclk(void) | |
297 | { | |
298 | return get_uart_clk(); | |
299 | } | |
300 | ||
ff167df5 JL |
301 | u32 imx_get_fecclk(void) |
302 | { | |
303 | return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK); | |
304 | } | |
305 | ||
23608e23 JL |
306 | unsigned int mxc_get_clock(enum mxc_clock clk) |
307 | { | |
308 | switch (clk) { | |
309 | case MXC_ARM_CLK: | |
310 | return get_mcu_main_clk(); | |
311 | case MXC_PER_CLK: | |
312 | return get_periph_clk(); | |
313 | case MXC_AHB_CLK: | |
314 | return get_ahb_clk(); | |
315 | case MXC_IPG_CLK: | |
316 | return get_ipg_clk(); | |
317 | case MXC_IPG_PERCLK: | |
318 | return get_ipg_per_clk(); | |
319 | case MXC_UART_CLK: | |
320 | return get_uart_clk(); | |
321 | case MXC_CSPI_CLK: | |
322 | return get_cspi_clk(); | |
323 | case MXC_AXI_CLK: | |
324 | return get_axi_clk(); | |
325 | case MXC_EMI_SLOW_CLK: | |
326 | return get_emi_slow_clk(); | |
327 | case MXC_DDR_CLK: | |
328 | return get_mmdc_ch0_clk(); | |
329 | case MXC_ESDHC_CLK: | |
330 | return get_usdhc_clk(0); | |
331 | case MXC_ESDHC2_CLK: | |
332 | return get_usdhc_clk(1); | |
333 | case MXC_ESDHC3_CLK: | |
334 | return get_usdhc_clk(2); | |
335 | case MXC_ESDHC4_CLK: | |
336 | return get_usdhc_clk(3); | |
337 | case MXC_SATA_CLK: | |
338 | return get_ahb_clk(); | |
339 | default: | |
340 | break; | |
341 | } | |
342 | ||
343 | return -1; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Dump some core clockes. | |
348 | */ | |
349 | int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | |
350 | { | |
351 | u32 freq; | |
352 | freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK); | |
353 | printf("PLL_SYS %8d MHz\n", freq / 1000000); | |
354 | freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK); | |
355 | printf("PLL_BUS %8d MHz\n", freq / 1000000); | |
356 | freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK); | |
357 | printf("PLL_OTG %8d MHz\n", freq / 1000000); | |
358 | freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK); | |
359 | printf("PLL_NET %8d MHz\n", freq / 1000000); | |
360 | ||
361 | printf("\n"); | |
362 | printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); | |
363 | printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); | |
364 | printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); | |
365 | printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); | |
366 | printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); | |
367 | printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); | |
368 | printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); | |
369 | printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); | |
370 | printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); | |
371 | printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000); | |
372 | printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000); | |
373 | printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
378 | /***************************************************/ | |
379 | ||
380 | U_BOOT_CMD( | |
381 | clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks, | |
382 | "display clocks", | |
383 | "" | |
384 | ); |