[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <asm/imx-common/hab.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <imx_thermal.h>
#include <mmc.h>

enum ldo_reg {
	LDO_ARM,
	LDO_SOC,
	LDO_PU,
};

struct scu_regs {
	u32	ctrl;
	u32	config;
	u32	status;
	u32	invalidate;
	u32	fpga_rev;
};

#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
	.regs = (void *)ANATOP_BASE_ADDR,
	.fuse_bank = 1,
	.fuse_word = 6,
};

U_BOOT_DEVICE(imx6_thermal) = {
	.name = "imx_thermal",
	.platdata = &imx6_thermal_plat,
};
#endif

#if defined(CONFIG_SECURE_BOOT)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
	.bank = 0,
	.word = 6,
};
#endif

u32 get_nr_cpus(void)
{
	struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
	return readl(&scu->config) & 3;
}

u32 get_cpu_rev(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 reg = readl(&anatop->digprog_sololite);
	u32 type = ((reg >> 16) & 0xff);
	u32 major, cfg = 0;

	if (type != MXC_CPU_MX6SL) {
		reg = readl(&anatop->digprog);
		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
		cfg = readl(&scu->config) & 3;
		type = ((reg >> 16) & 0xff);
		if (type == MXC_CPU_MX6DL) {
			if (!cfg)
				type = MXC_CPU_MX6SOLO;
		}

		if (type == MXC_CPU_MX6Q) {
			if (cfg == 1)
				type = MXC_CPU_MX6D;
		}

	}
	major = ((reg >> 8) & 0xff);
	if ((major >= 1) &&
	    ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
		major--;
		type = MXC_CPU_MX6QP;
		if (cfg == 1)
			type = MXC_CPU_MX6DP;
	}
	reg &= 0xff;		/* mx6 silicon revision */
	return (type << 12) | (reg + (0x10 * (major + 1)));
}

/*
 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
 * defines a 2-bit SPEED_GRADING
 */
#define OCOTP_CFG3_SPEED_SHIFT	16
#define OCOTP_CFG3_SPEED_800MHZ	0
#define OCOTP_CFG3_SPEED_850MHZ	1
#define OCOTP_CFG3_SPEED_1GHZ	2
#define OCOTP_CFG3_SPEED_1P2GHZ	3

/*
 * For i.MX6UL
 */
#define OCOTP_CFG3_SPEED_528MHZ 1
#define OCOTP_CFG3_SPEED_696MHZ 2

u32 get_cpu_speed_grade_hz(void)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[0];
	struct fuse_bank0_regs *fuse =
		(struct fuse_bank0_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->cfg3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;

	if (is_mx6ul()) {
		if (val == OCOTP_CFG3_SPEED_528MHZ)
			return 528000000;
		else if (val == OCOTP_CFG3_SPEED_696MHZ)
			return 69600000;
		else
			return 0;
	}

	switch (val) {
	/* Valid for IMX6DQ */
	case OCOTP_CFG3_SPEED_1P2GHZ:
		if (is_mx6dq() || is_mx6dqp())
			return 1200000000;
	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
	case OCOTP_CFG3_SPEED_1GHZ:
		return 996000000;
	/* Valid for IMX6DQ */
	case OCOTP_CFG3_SPEED_850MHZ:
		if (is_mx6dq() || is_mx6dqp())
			return 852000000;
	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
	case OCOTP_CFG3_SPEED_800MHZ:
		return 792000000;
	}
	return 0;
}

/*
 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
 * defines a 2-bit Temperature Grade
 *
 * return temperature grade and min/max temperature in celcius
 */
#define OCOTP_MEM0_TEMP_SHIFT          6

u32 get_cpu_temp_grade(int *minc, int *maxc)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->mem0);
	val >>= OCOTP_MEM0_TEMP_SHIFT;
	val &= 0x3;

	if (minc && maxc) {
		if (val == TEMP_AUTOMOTIVE) {
			*minc = -40;
			*maxc = 125;
		} else if (val == TEMP_INDUSTRIAL) {
			*minc = -40;
			*maxc = 105;
		} else if (val == TEMP_EXTCOMMERCIAL) {
			*minc = -20;
			*maxc = 105;
		} else {
			*minc = 0;
			*maxc = 95;
		}
	}
	return val;
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	u32 cpurev = get_cpu_rev();
	u32 type = ((cpurev >> 12) & 0xff);
	if (type == MXC_CPU_MX6SOLO)
		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);

	if (type == MXC_CPU_MX6D)
		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);

	return cpurev;
}
#endif

static void clear_ldo_ramp(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	int reg;

	/* ROM may modify LDO ramp up time according to fuse setting, so in
	 * order to be in the safe side we neeed to reset these settings to
	 * match the reset value: 0'b00
	 */
	reg = readl(&anatop->ana_misc2);
	reg &= ~(0x3f << 24);
	writel(reg, &anatop->ana_misc2);
}

/*
 * Set the PMU_REG_CORE register
 *
 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 * Possible values are from 0.725V to 1.450V in steps of
 * 0.025V (25mV).
 */
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 val, step, old, reg = readl(&anatop->reg_core);
	u8 shift;

	if (mv < 725)
		val = 0x00;	/* Power gated off */
	else if (mv > 1450)
		val = 0x1F;	/* Power FET switched full on. No regulation */
	else
		val = (mv - 700) / 25;

	clear_ldo_ramp();

	switch (ldo) {
	case LDO_SOC:
		shift = 18;
		break;
	case LDO_PU:
		shift = 9;
		break;
	case LDO_ARM:
		shift = 0;
		break;
	default:
		return -EINVAL;
	}

	old = (reg & (0x1F << shift)) >> shift;
	step = abs(val - old);
	if (step == 0)
		return 0;

	reg = (reg & ~(0x1F << shift)) | (val << shift);
	writel(reg, &anatop->reg_core);

	/*
	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	 * step
	 */
	udelay(3 * step);

	return 0;
}

static void set_ahb_rate(u32 val)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, div;

	div = get_periph_clk() / val - 1;
	reg = readl(&mxc_ccm->cbcdr);

	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}

static void clear_mmdc_ch_mask(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg;
	reg = readl(&mxc_ccm->ccdr);

	/* Clear MMDC channel mask */
	if (is_mx6sx() || is_mx6ul() || is_mx6sl())
		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
	else
		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
	writel(reg, &mxc_ccm->ccdr);
}

static void init_bandgap(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	/*
	 * Ensure the bandgap has stabilized.
	 */
	while (!(readl(&anatop->ana_misc0) & 0x80))
		;
	/*
	 * For best noise performance of the analog blocks using the
	 * outputs of the bandgap, the reftop_selfbiasoff bit should
	 * be set.
	 */
	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
}


#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg;

	reg = readl(&mxc_ccm->cscmr1);
	reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	writel(reg, &mxc_ccm->cscmr1);
}
#endif

int arch_cpu_init(void)
{
	init_aips();

	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	clear_mmdc_ch_mask();

	/*
	 * Disable self-bias circuit in the analog bandap.
	 * The self-bias circuit is used by the bandgap during startup.
	 * This bit should be set after the bandgap has initialized.
	 */
	init_bandgap();

	if (!is_mx6ul() && !is_mx6ull()) {
		/*
		 * When low freq boot is enabled, ROM will not set AHB
		 * freq, so we need to ensure AHB freq is 132MHz in such
		 * scenario.
		 *
		 * To i.MX6UL, when power up, default ARM core and
		 * AHB rate is 396M and 132M.
		 */
		if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
			set_ahb_rate(132000000);
	}

	if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
		/*
		 * According to the design team's requirement on i.MX6UL,
		 * the PMIC_STBY_REQ PAD should be configured as open
		 * drain 100K (0x0000b8a0).
		 * Only exists on TO1.0
		 */
		writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
	}

	/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
	set_preclk_from_osc();
#endif

	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

	init_src();

	return 0;
}

#ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno)
{
	return CONFIG_SYS_MMC_ENV_DEV;
}

static int mmc_get_boot_dev(void)
{
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
	u32 soc_sbmr = readl(&src_regs->sbmr1);
	u32 bootsel;
	int devno;

	/*
	 * Refer to
	 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
	 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
	 * i.MX6SL/SX/UL has same layout.
	 */
	bootsel = (soc_sbmr & 0x000000FF) >> 6;

	/* No boot from sd/mmc */
	if (bootsel != 1)
		return -1;

	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
	devno = (soc_sbmr & 0x00001800) >> 11;

	return devno;
}

int mmc_get_env_dev(void)
{
	int devno = mmc_get_boot_dev();

	/* If not boot from sd/mmc, use default value */
	if (devno < 0)
		return CONFIG_SYS_MMC_ENV_DEV;

	return board_mmc_get_env_dev(devno);
}

#ifdef CONFIG_SYS_MMC_ENV_PART
__weak int board_mmc_get_env_part(int devno)
{
	return CONFIG_SYS_MMC_ENV_PART;
}

uint mmc_get_env_part(struct mmc *mmc)
{
	int devno = mmc_get_boot_dev();

	/* If not boot from sd/mmc, use default value */
	if (devno < 0)
		return CONFIG_SYS_MMC_ENV_PART;

	return board_mmc_get_env_part(devno);
}
#endif
#endif

int board_postclk_init(void)
{
	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */

	return 0;
}

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
		u32 value = readl(&fuse->mac_addr2);
		mac[0] = value >> 24 ;
		mac[1] = value >> 16 ;
		mac[2] = value >> 8 ;
		mac[3] = value ;

		value = readl(&fuse->mac_addr1);
		mac[4] = value >> 24 ;
		mac[5] = value >> 16 ;
		
	} else {
		u32 value = readl(&fuse->mac_addr1);
		mac[0] = (value >> 8);
		mac[1] = value ;

		value = readl(&fuse->mac_addr0);
		mac[2] = value >> 24 ;
		mac[3] = value >> 16 ;
		mac[4] = value >> 8 ;
		mac[5] = value ;
	}

}
#endif

/*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
 * instead of SBMR1 to determine the boot device.
 */
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	/* reserved value should start rom usb */
	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	{"ecspi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	{"ecspi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
	/* 4 bit bus width */
	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"esdhc3",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	{NULL,		0},
};

void reset_misc(void)
{
#ifdef CONFIG_VIDEO_MXS
	lcdif_power_down();
#endif
}

void s_init(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 mask480;
	u32 mask528;
	u32 reg, periph1, periph2;

	if (is_mx6sx() || is_mx6ul())
		return;

	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	 * to make sure PFD is working right, otherwise, PFDs may
	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
	 * workaround in ROM code, as bus clock need it
	 */

	mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
		ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(2) |
		ANATOP_PFD_CLKGATE_MASK(3);
	mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(3);

	reg = readl(&ccm->cbcmr);
	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);

	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	if ((periph2 != 0x2) && (periph1 != 0x2))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(0);

	if ((periph2 != 0x1) && (periph1 != 0x1) &&
		(periph2 != 0x3) && (periph1 != 0x3))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);

	writel(mask480, &anatop->pfd_480_set);
	writel(mask528, &anatop->pfd_528_set);
	writel(mask480, &anatop->pfd_480_clr);
	writel(mask528, &anatop->pfd_528_clr);
}

#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	u8 reg;
	reg = readb(&hdmi->phy_conf0);
	reg |= HDMI_PHY_CONF0_PDZ_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	writeb(reg, &hdmi->phy_conf0);
	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}

void imx_setup_hdmi(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	int reg, count;
	u8 val;

	/* Turn on HDMI PHY clock */
	reg = readl(&mxc_ccm->CCGR2);
	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	writel(reg, &mxc_ccm->CCGR2);
	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	reg = readl(&mxc_ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);

	/* Clear the overflow condition */
	if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
		/* TMDS software reset */
		writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
		val = readb(&hdmi->fc_invidconf);
		/* Need minimum 3 times to write to clear the register */
		for (count = 0 ; count < 5 ; count++)
			writeb(val, &hdmi->fc_invidconf);
	}
}
#endif

#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
	struct src *src_reg;
	u32 stack, pc;

	if (!boot_private_data)
		return -EINVAL;

	stack = *(u32 *)boot_private_data;
	pc = *(u32 *)(boot_private_data + 4);

	/* Set the stack and pc to M4 bootROM */
	writel(stack, M4_BOOTROM_BASE_ADDR);
	writel(pc, M4_BOOTROM_BASE_ADDR + 4);

	/* Enable M4 */
	src_reg = (struct src *)SRC_BASE_ADDR;
	clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
			SRC_SCR_M4_ENABLE_MASK);

	return 0;
}

int arch_auxiliary_core_check_up(u32 core_id)
{
	struct src *src_reg = (struct src *)SRC_BASE_ADDR;
	unsigned val;

	val = readl(&src_reg->scr);

	if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
		return 0;  /* assert in reset */

	return 1;
}
#endif
Commit	Line	Data
23608e23 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	8	*/
	9
	10	#include <common.h>
1221ce45	11	#include <linux/errno.h>
23608e23 JL	12	#include <asm/io.h>
	13	#include <asm/arch/imx-regs.h>
	14	#include <asm/arch/clock.h>
	15	#include <asm/arch/sys_proto.h>
124a06d7	16	#include <asm/imx-common/boot_mode.h>
ae695b18	17	#include <asm/imx-common/dma.h>
6b50bfe5	18	#include <asm/imx-common/hab.h>
76c91e66	19	#include <stdbool.h>
5ea7f0e3 PKS	20	#include <asm/arch/mxc_hdmi.h>
5ea7f0e3 PKS	21	#include <asm/arch/crm_regs.h>
7a264168 YL	22	#include <dm.h>
7a264168 YL	23	#include <imx_thermal.h>
1a43dc11	24	#include <mmc.h>
23608e23	25
3d622b78 FE	26	enum ldo_reg {
	27	LDO_ARM,
	28	LDO_SOC,
	29	LDO_PU,
	30	};
	31
20332a06 TK	32	struct scu_regs {
	33	u32 ctrl;
	34	u32 config;
	35	u32 status;
	36	u32 invalidate;
	37	u32 fpga_rev;
	38	};
	39
1368f993	40	#if defined(CONFIG_IMX_THERMAL)
7a264168 YL	41	static const struct imx_thermal_plat imx6_thermal_plat = {
	42	.regs = (void *)ANATOP_BASE_ADDR,
	43	.fuse_bank = 1,
	44	.fuse_word = 6,
	45	};
	46
	47	U_BOOT_DEVICE(imx6_thermal) = {
	48	.name = "imx_thermal",
	49	.platdata = &imx6_thermal_plat,
	50	};
	51	#endif
	52
6b50bfe5 AA	53	#if defined(CONFIG_SECURE_BOOT)
	54	struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
	55	.bank = 0,
	56	.word = 6,
	57	};
	58	#endif
	59
a76df709 GH	60	u32 get_nr_cpus(void)
	61	{
	62	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	63	return readl(&scu->config) & 3;
	64	}
	65
23608e23 JL	66	u32 get_cpu_rev(void)
23608e23 JL	67	{
a7683867	68	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
20332a06 TK	69	u32 reg = readl(&anatop->digprog_sololite);
20332a06 TK	70	u32 type = ((reg >> 16) & 0xff);
d0acd993	71	u32 major, cfg = 0;
a7683867	72
20332a06 TK	73	if (type != MXC_CPU_MX6SL) {
20332a06 TK	74	reg = readl(&anatop->digprog);
94db6655	75	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
d0acd993	76	cfg = readl(&scu->config) & 3;
20332a06 TK	77	type = ((reg >> 16) & 0xff);
20332a06 TK	78	if (type == MXC_CPU_MX6DL) {
20332a06 TK	79	if (!cfg)
	80	type = MXC_CPU_MX6SOLO;
	81	}
94db6655 FE	82
	83	if (type == MXC_CPU_MX6Q) {
	84	if (cfg == 1)
	85	type = MXC_CPU_MX6D;
	86	}
	87
20332a06	88	}
dfd4861c	89	major = ((reg >> 8) & 0xff);
d0acd993 PF	90	if ((major >= 1) &&
	91	((type == MXC_CPU_MX6Q) \|\| (type == MXC_CPU_MX6D))) {
	92	major--;
	93	type = MXC_CPU_MX6QP;
	94	if (cfg == 1)
	95	type = MXC_CPU_MX6DP;
	96	}
20332a06	97	reg &= 0xff; /* mx6 silicon revision */
dfd4861c	98	return (type << 12) \| (reg + (0x10 * (major + 1)));
23608e23 JL	99	}
23608e23 JL	100
9b9449c3 TH	101	/*
	102	* OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
	103	* defines a 2-bit SPEED_GRADING
	104	*/
	105	#define OCOTP_CFG3_SPEED_SHIFT 16
	106	#define OCOTP_CFG3_SPEED_800MHZ 0
	107	#define OCOTP_CFG3_SPEED_850MHZ 1
	108	#define OCOTP_CFG3_SPEED_1GHZ 2
	109	#define OCOTP_CFG3_SPEED_1P2GHZ 3
	110
d15a244b PF	111	/*
	112	* For i.MX6UL
	113	*/
	114	#define OCOTP_CFG3_SPEED_528MHZ 1
	115	#define OCOTP_CFG3_SPEED_696MHZ 2
	116
9b9449c3 TH	117	u32 get_cpu_speed_grade_hz(void)
	118	{
	119	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	120	struct fuse_bank *bank = &ocotp->bank[0];
	121	struct fuse_bank0_regs *fuse =
	122	(struct fuse_bank0_regs *)bank->fuse_regs;
	123	uint32_t val;
	124
	125	val = readl(&fuse->cfg3);
	126	val >>= OCOTP_CFG3_SPEED_SHIFT;
	127	val &= 0x3;
	128
b949fd2c	129	if (is_mx6ul()) {
d15a244b PF	130	if (val == OCOTP_CFG3_SPEED_528MHZ)
	131	return 528000000;
	132	else if (val == OCOTP_CFG3_SPEED_696MHZ)
	133	return 69600000;
	134	else
	135	return 0;
	136	}
	137
9b9449c3 TH	138	switch (val) {
	139	/* Valid for IMX6DQ */
	140	case OCOTP_CFG3_SPEED_1P2GHZ:
04cb3c0b	141	if (is_mx6dq() \|\| is_mx6dqp())
9b9449c3 TH	142	return 1200000000;
	143	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
	144	case OCOTP_CFG3_SPEED_1GHZ:
	145	return 996000000;
	146	/* Valid for IMX6DQ */
	147	case OCOTP_CFG3_SPEED_850MHZ:
04cb3c0b	148	if (is_mx6dq() \|\| is_mx6dqp())
9b9449c3 TH	149	return 852000000;
	150	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
	151	case OCOTP_CFG3_SPEED_800MHZ:
	152	return 792000000;
	153	}
	154	return 0;
	155	}
	156
f0e8e894 TH	157	/*
	158	* OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
	159	* defines a 2-bit Temperature Grade
	160	*
	161	* return temperature grade and min/max temperature in celcius
	162	*/
	163	#define OCOTP_MEM0_TEMP_SHIFT 6
	164
	165	u32 get_cpu_temp_grade(int minc, int maxc)
	166	{
	167	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	168	struct fuse_bank *bank = &ocotp->bank[1];
	169	struct fuse_bank1_regs *fuse =
	170	(struct fuse_bank1_regs *)bank->fuse_regs;
	171	uint32_t val;
	172
	173	val = readl(&fuse->mem0);
	174	val >>= OCOTP_MEM0_TEMP_SHIFT;
	175	val &= 0x3;
	176
	177	if (minc && maxc) {
	178	if (val == TEMP_AUTOMOTIVE) {
	179	*minc = -40;
	180	*maxc = 125;
	181	} else if (val == TEMP_INDUSTRIAL) {
	182	*minc = -40;
	183	*maxc = 105;
	184	} else if (val == TEMP_EXTCOMMERCIAL) {
	185	*minc = -20;
	186	*maxc = 105;
	187	} else {
	188	*minc = 0;
	189	*maxc = 95;
	190	}
	191	}
	192	return val;
	193	}
	194
38e70077 FE	195	#ifdef CONFIG_REVISION_TAG
	196	u32 __weak get_board_rev(void)
	197	{
	198	u32 cpurev = get_cpu_rev();
	199	u32 type = ((cpurev >> 12) & 0xff);
	200	if (type == MXC_CPU_MX6SOLO)
	201	cpurev = (MXC_CPU_MX6DL) << 12 \| (cpurev & 0xFFF);
	202
94db6655 FE	203	if (type == MXC_CPU_MX6D)
	204	cpurev = (MXC_CPU_MX6Q) << 12 \| (cpurev & 0xFFF);
	205
38e70077 FE	206	return cpurev;
	207	}
	208	#endif
	209
e113fd19 FE	210	static void clear_ldo_ramp(void)
	211	{
	212	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	213	int reg;
	214
	215	/* ROM may modify LDO ramp up time according to fuse setting, so in
	216	* order to be in the safe side we neeed to reset these settings to
	217	* match the reset value: 0'b00
	218	*/
	219	reg = readl(&anatop->ana_misc2);
	220	reg &= ~(0x3f << 24);
	221	writel(reg, &anatop->ana_misc2);
	222	}
	223
cac833a9	224	/*
157f45da	225	* Set the PMU_REG_CORE register
cac833a9	226	*
157f45da	227	* Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
cac833a9 DB	228	* Possible values are from 0.725V to 1.450V in steps of
	229	* 0.025V (25mV).
	230	*/
3d622b78	231	static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
cac833a9 DB	232	{
cac833a9 DB	233	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
39f0ac93	234	u32 val, step, old, reg = readl(&anatop->reg_core);
3d622b78	235	u8 shift;
cac833a9 DB	236
	237	if (mv < 725)
	238	val = 0x00; /* Power gated off */
	239	else if (mv > 1450)
	240	val = 0x1F; /* Power FET switched full on. No regulation */
	241	else
	242	val = (mv - 700) / 25;
	243
e113fd19 FE	244	clear_ldo_ramp();
e113fd19 FE	245
3d622b78 FE	246	switch (ldo) {
	247	case LDO_SOC:
	248	shift = 18;
	249	break;
	250	case LDO_PU:
	251	shift = 9;
	252	break;
	253	case LDO_ARM:
	254	shift = 0;
	255	break;
	256	default:
	257	return -EINVAL;
	258	}
	259
39f0ac93 FE	260	old = (reg & (0x1F << shift)) >> shift;
	261	step = abs(val - old);
	262	if (step == 0)
	263	return 0;
	264
3d622b78	265	reg = (reg & ~(0x1F << shift)) \| (val << shift);
cac833a9	266	writel(reg, &anatop->reg_core);
3d622b78	267
39f0ac93 FE	268	/*
	269	* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	270	* step
	271	*/
	272	udelay(3 * step);
	273
3d622b78	274	return 0;
cac833a9 DB	275	}
cac833a9 DB	276
5c92edc2 AH	277	static void set_ahb_rate(u32 val)
	278	{
	279	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	280	u32 reg, div;
	281
	282	div = get_periph_clk() / val - 1;
	283	reg = readl(&mxc_ccm->cbcdr);
	284
	285	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) \|
	286	(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
	287	}
	288
16197bb8 AH	289	static void clear_mmdc_ch_mask(void)
	290	{
	291	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
e1c2d68b PF	292	u32 reg;
e1c2d68b PF	293	reg = readl(&mxc_ccm->ccdr);
16197bb8 AH	294
16197bb8 AH	295	/* Clear MMDC channel mask */
b949fd2c	296	if (is_mx6sx() \|\| is_mx6ul() \|\| is_mx6sl())
b777789e YL	297	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
	298	else
	299	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK \| MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
e1c2d68b	300	writel(reg, &mxc_ccm->ccdr);
16197bb8 AH	301	}
16197bb8 AH	302
1f516faa PF	303	static void init_bandgap(void)
	304	{
	305	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	306	/*
	307	* Ensure the bandgap has stabilized.
	308	*/
	309	while (!(readl(&anatop->ana_misc0) & 0x80))
	310	;
	311	/*
	312	* For best noise performance of the analog blocks using the
	313	* outputs of the bandgap, the reftop_selfbiasoff bit should
	314	* be set.
	315	*/
	316	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
	317	}
	318
	319
0f8ec145 YL	320	#ifdef CONFIG_MX6SL
	321	static void set_preclk_from_osc(void)
	322	{
	323	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	324	u32 reg;
	325
	326	reg = readl(&mxc_ccm->cscmr1);
	327	reg \|= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	328	writel(reg, &mxc_ccm->cscmr1);
	329	}
	330	#endif
	331
23608e23 JL	332	int arch_cpu_init(void)
	333	{
	334	init_aips();
	335
16197bb8 AH	336	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	337	clear_mmdc_ch_mask();
	338
1f516faa PF	339	/*
	340	* Disable self-bias circuit in the analog bandap.
	341	* The self-bias circuit is used by the bandgap during startup.
	342	* This bit should be set after the bandgap has initialized.
	343	*/
	344	init_bandgap();
	345
cdf33c94	346	if (!is_mx6ul() && !is_mx6ull()) {
e4dc3fc0 PF	347	/*
	348	* When low freq boot is enabled, ROM will not set AHB
	349	* freq, so we need to ensure AHB freq is 132MHz in such
	350	* scenario.
	351	*
	352	* To i.MX6UL, when power up, default ARM core and
	353	* AHB rate is 396M and 132M.
	354	*/
	355	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
	356	set_ahb_rate(132000000);
	357	}
5c92edc2	358
7082d879 PF	359	if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
	360	/*
	361	* According to the design team's requirement on i.MX6UL,
	362	* the PMIC_STBY_REQ PAD should be configured as open
	363	* drain 100K (0x0000b8a0).
	364	* Only exists on TO1.0
	365	*/
	366	writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
	367	}
	368
	369	/* Set perclk to source from OSC 24MHz */
0f8ec145 YL	370	#if defined(CONFIG_MX6SL)
	371	set_preclk_from_osc();
	372	#endif
	373
76c91e66	374	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
ae695b18 SR	375
	376	#ifdef CONFIG_APBH_DMA
	377	/* Start APBH DMA */
	378	mxs_dma_init();
	379	#endif
	380
9d16c52f DB	381	init_src();
9d16c52f DB	382
23608e23 JL	383	return 0;
23608e23 JL	384	}
23608e23	385
216d286c PF	386	#ifdef CONFIG_ENV_IS_IN_MMC
	387	__weak int board_mmc_get_env_dev(int devno)
	388	{
	389	return CONFIG_SYS_MMC_ENV_DEV;
	390	}
	391
1a43dc11	392	static int mmc_get_boot_dev(void)
216d286c PF	393	{
	394	struct src src_regs = (struct src )SRC_BASE_ADDR;
	395	u32 soc_sbmr = readl(&src_regs->sbmr1);
	396	u32 bootsel;
	397	int devno;
	398
	399	/*
	400	* Refer to
	401	* "i.MX 6Dual/6Quad Applications Processor Reference Manual"
	402	* Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
	403	* i.MX6SL/SX/UL has same layout.
	404	*/
	405	bootsel = (soc_sbmr & 0x000000FF) >> 6;
	406
1a43dc11	407	/* No boot from sd/mmc */
216d286c	408	if (bootsel != 1)
1a43dc11	409	return -1;
216d286c PF	410
	411	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
	412	devno = (soc_sbmr & 0x00001800) >> 11;
	413
1a43dc11 SM	414	return devno;
	415	}
	416
	417	int mmc_get_env_dev(void)
	418	{
	419	int devno = mmc_get_boot_dev();
	420
	421	/* If not boot from sd/mmc, use default value */
	422	if (devno < 0)
	423	return CONFIG_SYS_MMC_ENV_DEV;
	424
216d286c PF	425	return board_mmc_get_env_dev(devno);
216d286c PF	426	}
1a43dc11 SM	427
	428	#ifdef CONFIG_SYS_MMC_ENV_PART
	429	__weak int board_mmc_get_env_part(int devno)
	430	{
	431	return CONFIG_SYS_MMC_ENV_PART;
	432	}
	433
	434	uint mmc_get_env_part(struct mmc *mmc)
	435	{
	436	int devno = mmc_get_boot_dev();
	437
	438	/* If not boot from sd/mmc, use default value */
	439	if (devno < 0)
	440	return CONFIG_SYS_MMC_ENV_PART;
	441
	442	return board_mmc_get_env_part(devno);
	443	}
	444	#endif
216d286c PF	445	#endif
216d286c PF	446
39f0ac93 FE	447	int board_postclk_init(void)
	448	{
	449	set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
	450
	451	return 0;
	452	}
	453
23608e23	454	#if defined(CONFIG_FEC_MXC)
be252b65	455	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
23608e23	456	{
8f3ff11c BT	457	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	458	struct fuse_bank *bank = &ocotp->bank[4];
23608e23 JL	459	struct fuse_bank4_regs *fuse =
	460	(struct fuse_bank4_regs *)bank->fuse_regs;
	461
b949fd2c	462	if ((is_mx6sx() \|\| is_mx6ul()) && dev_id == 1) {
d4d1dd67 YL	463	u32 value = readl(&fuse->mac_addr2);
	464	mac[0] = value >> 24 ;
	465	mac[1] = value >> 16 ;
	466	mac[2] = value >> 8 ;
	467	mac[3] = value ;
	468
	469	value = readl(&fuse->mac_addr1);
	470	mac[4] = value >> 24 ;
	471	mac[5] = value >> 16 ;
	472
	473	} else {
	474	u32 value = readl(&fuse->mac_addr1);
	475	mac[0] = (value >> 8);
	476	mac[1] = value ;
	477
	478	value = readl(&fuse->mac_addr0);
	479	mac[2] = value >> 24 ;
	480	mac[3] = value >> 16 ;
	481	mac[4] = value >> 8 ;
	482	mac[5] = value ;
	483	}
23608e23 JL	484
	485	}
	486	#endif
124a06d7	487
124a06d7 TK	488	/*
	489	* cfg_val will be used for
	490	* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
f2863ff3 NK	491	* After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
f2863ff3 NK	492	* instead of SBMR1 to determine the boot device.
124a06d7 TK	493	*/
	494	const struct boot_mode soc_boot_modes[] = {
	495	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	496	/* reserved value should start rom usb */
	497	{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	498	{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
2d59e3ec ND	499	{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	500	{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	501	{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	502	{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
124a06d7 TK	503	/* 4 bit bus width */
	504	{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	505	{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	506	{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	507	{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	508	{NULL, 0},
	509	};
8f393776	510
eb111bb3 PF	511	void reset_misc(void)
	512	{
	513	#ifdef CONFIG_VIDEO_MXS
	514	lcdif_power_down();
	515	#endif
	516	}
	517
8f393776 SW	518	void s_init(void)
8f393776 SW	519	{
8467faef	520	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
9293d7fd	521	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
8467faef EN	522	u32 mask480;
8467faef EN	523	u32 mask528;
9293d7fd	524	u32 reg, periph1, periph2;
a3df99b5	525
b949fd2c	526	if (is_mx6sx() \|\| is_mx6ul())
a3df99b5 FE	527	return;
a3df99b5 FE	528
8467faef EN	529	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	530	* to make sure PFD is working right, otherwise, PFDs may
	531	* not output clock after reset, MX6DL and MX6SL have added 396M pfd
	532	* workaround in ROM code, as bus clock need it
	533	*/
	534
	535	mask480 = ANATOP_PFD_CLKGATE_MASK(0) \|
	536	ANATOP_PFD_CLKGATE_MASK(1) \|
	537	ANATOP_PFD_CLKGATE_MASK(2) \|
	538	ANATOP_PFD_CLKGATE_MASK(3);
9293d7fd	539	mask528 = ANATOP_PFD_CLKGATE_MASK(1) \|
8467faef EN	540	ANATOP_PFD_CLKGATE_MASK(3);
8467faef EN	541
9293d7fd YL	542	reg = readl(&ccm->cbcmr);
	543	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
	544	>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	545	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
	546	>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
	547
	548	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	549	if ((periph2 != 0x2) && (periph1 != 0x2))
	550	mask528 \|= ANATOP_PFD_CLKGATE_MASK(0);
	551
	552	if ((periph2 != 0x1) && (periph1 != 0x1) &&
	553	(periph2 != 0x3) && (periph1 != 0x3))
8467faef	554	mask528 \|= ANATOP_PFD_CLKGATE_MASK(2);
9293d7fd	555
8467faef EN	556	writel(mask480, &anatop->pfd_480_set);
	557	writel(mask528, &anatop->pfd_528_set);
	558	writel(mask480, &anatop->pfd_480_clr);
	559	writel(mask528, &anatop->pfd_528_clr);
8f393776	560	}
5ea7f0e3 PKS	561
	562	#ifdef CONFIG_IMX_HDMI
	563	void imx_enable_hdmi_phy(void)
	564	{
	565	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	566	u8 reg;
	567	reg = readb(&hdmi->phy_conf0);
	568	reg \|= HDMI_PHY_CONF0_PDZ_MASK;
	569	writeb(reg, &hdmi->phy_conf0);
	570	udelay(3000);
	571	reg \|= HDMI_PHY_CONF0_ENTMDS_MASK;
	572	writeb(reg, &hdmi->phy_conf0);
	573	udelay(3000);
	574	reg \|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	575	writeb(reg, &hdmi->phy_conf0);
	576	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
	577	}
	578
	579	void imx_setup_hdmi(void)
	580	{
	581	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	582	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
00b1d2d3 PF	583	int reg, count;
00b1d2d3 PF	584	u8 val;
5ea7f0e3 PKS	585
	586	/* Turn on HDMI PHY clock */
	587	reg = readl(&mxc_ccm->CCGR2);
	588	reg \|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK\|
	589	MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	590	writel(reg, &mxc_ccm->CCGR2);
	591	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	592	reg = readl(&mxc_ccm->chsccdr);
	593	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK\|
	594	MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK\|
	595	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	596	reg \|= (CHSCCDR_PODF_DIVIDE_BY_3
	597	<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
	598	\|(CHSCCDR_IPU_PRE_CLK_540M_PFD
	599	<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	600	writel(reg, &mxc_ccm->chsccdr);
00b1d2d3 PF	601
	602	/* Clear the overflow condition */
	603	if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
	604	/* TMDS software reset */
	605	writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
	606	val = readb(&hdmi->fc_invidconf);
	607	/* Need minimum 3 times to write to clear the register */
	608	for (count = 0 ; count < 5 ; count++)
	609	writeb(val, &hdmi->fc_invidconf);
	610	}
5ea7f0e3 PKS	611	}
5ea7f0e3 PKS	612	#endif
0623d375 PF	613
	614	#ifdef CONFIG_IMX_BOOTAUX
	615	int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
	616	{
	617	struct src *src_reg;
	618	u32 stack, pc;
	619
	620	if (!boot_private_data)
	621	return -EINVAL;
	622
	623	stack = (u32 )boot_private_data;
	624	pc = (u32 )(boot_private_data + 4);
	625
	626	/* Set the stack and pc to M4 bootROM */
	627	writel(stack, M4_BOOTROM_BASE_ADDR);
	628	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
	629
	630	/* Enable M4 */
	631	src_reg = (struct src *)SRC_BASE_ADDR;
	632	clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
	633	SRC_SCR_M4_ENABLE_MASK);
	634
	635	return 0;
	636	}
	637
	638	int arch_auxiliary_core_check_up(u32 core_id)
	639	{
	640	struct src src_reg = (struct src )SRC_BASE_ADDR;
	641	unsigned val;
	642
	643	val = readl(&src_reg->scr);
	644
	645	if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
	646	return 0; /* assert in reset */
	647
	648	return 1;
	649	}
	650	#endif