[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/armv7.h>
#include <asm/bootm.h>
#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>

enum ldo_reg {
	LDO_ARM,
	LDO_SOC,
	LDO_PU,
};

struct scu_regs {
	u32	ctrl;
	u32	config;
	u32	status;
	u32	invalidate;
	u32	fpga_rev;
};

u32 get_nr_cpus(void)
{
	struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
	return readl(&scu->config) & 3;
}

u32 get_cpu_rev(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 reg = readl(&anatop->digprog_sololite);
	u32 type = ((reg >> 16) & 0xff);

	if (type != MXC_CPU_MX6SL) {
		reg = readl(&anatop->digprog);
		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
		u32 cfg = readl(&scu->config) & 3;
		type = ((reg >> 16) & 0xff);
		if (type == MXC_CPU_MX6DL) {
			if (!cfg)
				type = MXC_CPU_MX6SOLO;
		}

		if (type == MXC_CPU_MX6Q) {
			if (cfg == 1)
				type = MXC_CPU_MX6D;
		}

	}
	reg &= 0xff;		/* mx6 silicon revision */
	return (type << 12) | (reg + 0x10);
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	u32 cpurev = get_cpu_rev();
	u32 type = ((cpurev >> 12) & 0xff);
	if (type == MXC_CPU_MX6SOLO)
		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);

	if (type == MXC_CPU_MX6D)
		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);

	return cpurev;
}
#endif

void init_aips(void)
{
	struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
	struct aipstz_regs *aips3;
#endif

	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
	aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
#endif

	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips1->mprot0);
	writel(0x77777777, &aips1->mprot1);
	writel(0x77777777, &aips2->mprot0);
	writel(0x77777777, &aips2->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips1->opacr0);
	writel(0x00000000, &aips1->opacr1);
	writel(0x00000000, &aips1->opacr2);
	writel(0x00000000, &aips1->opacr3);
	writel(0x00000000, &aips1->opacr4);
	writel(0x00000000, &aips2->opacr0);
	writel(0x00000000, &aips2->opacr1);
	writel(0x00000000, &aips2->opacr2);
	writel(0x00000000, &aips2->opacr3);
	writel(0x00000000, &aips2->opacr4);

#ifdef CONFIG_MX6SX
	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips3->mprot0);
	writel(0x77777777, &aips3->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips3->opacr0);
	writel(0x00000000, &aips3->opacr1);
	writel(0x00000000, &aips3->opacr2);
	writel(0x00000000, &aips3->opacr3);
	writel(0x00000000, &aips3->opacr4);
#endif
}

static void clear_ldo_ramp(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	int reg;

	/* ROM may modify LDO ramp up time according to fuse setting, so in
	 * order to be in the safe side we neeed to reset these settings to
	 * match the reset value: 0'b00
	 */
	reg = readl(&anatop->ana_misc2);
	reg &= ~(0x3f << 24);
	writel(reg, &anatop->ana_misc2);
}

/*
 * Set the PMU_REG_CORE register
 *
 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 * Possible values are from 0.725V to 1.450V in steps of
 * 0.025V (25mV).
 */
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 val, step, old, reg = readl(&anatop->reg_core);
	u8 shift;

	if (mv < 725)
		val = 0x00;	/* Power gated off */
	else if (mv > 1450)
		val = 0x1F;	/* Power FET switched full on. No regulation */
	else
		val = (mv - 700) / 25;

	clear_ldo_ramp();

	switch (ldo) {
	case LDO_SOC:
		shift = 18;
		break;
	case LDO_PU:
		shift = 9;
		break;
	case LDO_ARM:
		shift = 0;
		break;
	default:
		return -EINVAL;
	}

	old = (reg & (0x1F << shift)) >> shift;
	step = abs(val - old);
	if (step == 0)
		return 0;

	reg = (reg & ~(0x1F << shift)) | (val << shift);
	writel(reg, &anatop->reg_core);

	/*
	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	 * step
	 */
	udelay(3 * step);

	return 0;
}

static void imx_set_wdog_powerdown(bool enable)
{
	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;

	/* Write to the PDE (Power Down Enable) bit */
	writew(enable, &wdog1->wmcr);
	writew(enable, &wdog2->wmcr);
}

static void set_ahb_rate(u32 val)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, div;

	div = get_periph_clk() / val - 1;
	reg = readl(&mxc_ccm->cbcdr);

	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}

static void clear_mmdc_ch_mask(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* Clear MMDC channel mask */
	writel(0, &mxc_ccm->ccdr);
}

#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg;

	reg = readl(&mxc_ccm->cscmr1);
	reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	writel(reg, &mxc_ccm->cscmr1);
}
#endif

int arch_cpu_init(void)
{
	init_aips();

	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	clear_mmdc_ch_mask();

	/*
	 * When low freq boot is enabled, ROM will not set AHB
	 * freq, so we need to ensure AHB freq is 132MHz in such
	 * scenario.
	 */
	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
		set_ahb_rate(132000000);

		/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
	set_preclk_from_osc();
#endif

	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

	return 0;
}

int board_postclk_init(void)
{
	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */

	return 0;
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	enum dcache_option option = DCACHE_WRITETHROUGH;
#else
	enum dcache_option option = DCACHE_WRITEBACK;
#endif

	/* Avoid random hang when download by usb */
	invalidate_dcache_all();

	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();

	/* Enable caching on OCRAM and ROM */
	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
					ROMCP_ARB_END_ADDR,
					option);
	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
					IRAM_SIZE,
					option);
}
#endif

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	u32 value = readl(&fuse->mac_addr_high);
	mac[0] = (value >> 8);
	mac[1] = value ;

	value = readl(&fuse->mac_addr_low);
	mac[2] = value >> 24 ;
	mac[3] = value >> 16 ;
	mac[4] = value >> 8 ;
	mac[5] = value ;

}
#endif

void boot_mode_apply(unsigned cfg_val)
{
	unsigned reg;
	struct src *psrc = (struct src *)SRC_BASE_ADDR;
	writel(cfg_val, &psrc->gpr9);
	reg = readl(&psrc->gpr10);
	if (cfg_val)
		reg |= 1 << 28;
	else
		reg &= ~(1 << 28);
	writel(reg, &psrc->gpr10);
}
/*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
 * instead of SBMR1 to determine the boot device.
 */
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	/* reserved value should start rom usb */
	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	{"ecspi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	{"ecspi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
	/* 4 bit bus width */
	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"esdhc3",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	{NULL,		0},
};

void s_init(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 mask480;
	u32 mask528;
	u32 reg, periph1, periph2;

	if (is_cpu_type(MXC_CPU_MX6SX))
		return;

	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	 * to make sure PFD is working right, otherwise, PFDs may
	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
	 * workaround in ROM code, as bus clock need it
	 */

	mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
		ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(2) |
		ANATOP_PFD_CLKGATE_MASK(3);
	mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(3);

	reg = readl(&ccm->cbcmr);
	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);

	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	if ((periph2 != 0x2) && (periph1 != 0x2))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(0);

	if ((periph2 != 0x1) && (periph1 != 0x1) &&
		(periph2 != 0x3) && (periph1 != 0x3))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);

	writel(mask480, &anatop->pfd_480_set);
	writel(mask528, &anatop->pfd_528_set);
	writel(mask480, &anatop->pfd_480_clr);
	writel(mask528, &anatop->pfd_528_clr);
}

#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	u8 reg;
	reg = readb(&hdmi->phy_conf0);
	reg |= HDMI_PHY_CONF0_PDZ_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	writeb(reg, &hdmi->phy_conf0);
	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}

void imx_setup_hdmi(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	int reg;

	/* Turn on HDMI PHY clock */
	reg = readl(&mxc_ccm->CCGR2);
	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	writel(reg, &mxc_ccm->CCGR2);
	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	reg = readl(&mxc_ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);
}
#endif

#ifndef CONFIG_SYS_L2CACHE_OFF
#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
void v7_outer_cache_enable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
	unsigned int val;

#if defined CONFIG_MX6SL
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
	val = readl(&iomux->gpr[11]);
	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
		/* L2 cache configured as OCRAM, reset it */
		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
		writel(val, &iomux->gpr[11]);
	}
#endif

	/* Must disable the L2 before changing the latency parameters */
	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);

	writel(0x132, &pl310->pl310_tag_latency_ctrl);
	writel(0x132, &pl310->pl310_data_latency_ctrl);

	val = readl(&pl310->pl310_prefetch_ctrl);

	/* Turn on the L2 I/D prefetch */
	val |= 0x30000000;

	/*
	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
	 * But according to ARM PL310 errata: 752271
	 * ID: 752271: Double linefill feature can cause data corruption
	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
	 * Workaround: The only workaround to this erratum is to disable the
	 * double linefill feature. This is the default behavior.
	 */

#ifndef CONFIG_MX6Q
	val |= 0x40800000;
#endif
	writel(val, &pl310->pl310_prefetch_ctrl);

	val = readl(&pl310->pl310_power_ctrl);
	val |= L2X0_DYNAMIC_CLK_GATING_EN;
	val |= L2X0_STNDBY_MODE_EN;
	writel(val, &pl310->pl310_power_ctrl);

	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}

void v7_outer_cache_disable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;

	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
23608e23 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	8	*/
	9
	10	#include <common.h>
6d73c234	11	#include <asm/armv7.h>
5624c6bd	12	#include <asm/bootm.h>
6d73c234	13	#include <asm/pl310.h>
23608e23 JL	14	#include <asm/errno.h>
	15	#include <asm/io.h>
	16	#include <asm/arch/imx-regs.h>
	17	#include <asm/arch/clock.h>
	18	#include <asm/arch/sys_proto.h>
124a06d7	19	#include <asm/imx-common/boot_mode.h>
ae695b18	20	#include <asm/imx-common/dma.h>
76c91e66	21	#include <stdbool.h>
5ea7f0e3 PKS	22	#include <asm/arch/mxc_hdmi.h>
5ea7f0e3 PKS	23	#include <asm/arch/crm_regs.h>
f6d48b29	24	#include <asm/bootm.h>
23608e23	25
3d622b78 FE	26	enum ldo_reg {
	27	LDO_ARM,
	28	LDO_SOC,
	29	LDO_PU,
	30	};
	31
20332a06 TK	32	struct scu_regs {
	33	u32 ctrl;
	34	u32 config;
	35	u32 status;
	36	u32 invalidate;
	37	u32 fpga_rev;
	38	};
	39
a76df709 GH	40	u32 get_nr_cpus(void)
	41	{
	42	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	43	return readl(&scu->config) & 3;
	44	}
	45
23608e23 JL	46	u32 get_cpu_rev(void)
23608e23 JL	47	{
a7683867	48	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
20332a06 TK	49	u32 reg = readl(&anatop->digprog_sololite);
20332a06 TK	50	u32 type = ((reg >> 16) & 0xff);
a7683867	51
20332a06 TK	52	if (type != MXC_CPU_MX6SL) {
20332a06 TK	53	reg = readl(&anatop->digprog);
94db6655 FE	54	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
94db6655 FE	55	u32 cfg = readl(&scu->config) & 3;
20332a06 TK	56	type = ((reg >> 16) & 0xff);
20332a06 TK	57	if (type == MXC_CPU_MX6DL) {
20332a06 TK	58	if (!cfg)
	59	type = MXC_CPU_MX6SOLO;
	60	}
94db6655 FE	61
	62	if (type == MXC_CPU_MX6Q) {
	63	if (cfg == 1)
	64	type = MXC_CPU_MX6D;
	65	}
	66
20332a06 TK	67	}
	68	reg &= 0xff; /* mx6 silicon revision */
	69	return (type << 12) \| (reg + 0x10);
23608e23 JL	70	}
23608e23 JL	71
38e70077 FE	72	#ifdef CONFIG_REVISION_TAG
	73	u32 __weak get_board_rev(void)
	74	{
	75	u32 cpurev = get_cpu_rev();
	76	u32 type = ((cpurev >> 12) & 0xff);
	77	if (type == MXC_CPU_MX6SOLO)
	78	cpurev = (MXC_CPU_MX6DL) << 12 \| (cpurev & 0xFFF);
	79
94db6655 FE	80	if (type == MXC_CPU_MX6D)
	81	cpurev = (MXC_CPU_MX6Q) << 12 \| (cpurev & 0xFFF);
	82
38e70077 FE	83	return cpurev;
	84	}
	85	#endif
	86
23608e23 JL	87	void init_aips(void)
23608e23 JL	88	{
f2f77458	89	struct aipstz_regs aips1, aips2;
05d54b82 FE	90	#ifdef CONFIG_MX6SX
	91	struct aipstz_regs *aips3;
	92	#endif
f2f77458 JL	93
	94	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	95	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
05d54b82 FE	96	#ifdef CONFIG_MX6SX
	97	aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
	98	#endif
23608e23 JL	99
	100	/*
	101	* Set all MPROTx to be non-bufferable, trusted for R/W,
	102	* not forced to user-mode.
	103	*/
f2f77458 JL	104	writel(0x77777777, &aips1->mprot0);
	105	writel(0x77777777, &aips1->mprot1);
	106	writel(0x77777777, &aips2->mprot0);
	107	writel(0x77777777, &aips2->mprot1);
23608e23	108
f2f77458 JL	109	/*
	110	* Set all OPACRx to be non-bufferable, not require
	111	* supervisor privilege level for access,allow for
	112	* write access and untrusted master access.
	113	*/
	114	writel(0x00000000, &aips1->opacr0);
	115	writel(0x00000000, &aips1->opacr1);
	116	writel(0x00000000, &aips1->opacr2);
	117	writel(0x00000000, &aips1->opacr3);
	118	writel(0x00000000, &aips1->opacr4);
	119	writel(0x00000000, &aips2->opacr0);
	120	writel(0x00000000, &aips2->opacr1);
	121	writel(0x00000000, &aips2->opacr2);
	122	writel(0x00000000, &aips2->opacr3);
	123	writel(0x00000000, &aips2->opacr4);
05d54b82 FE	124
	125	#ifdef CONFIG_MX6SX
	126	/*
	127	* Set all MPROTx to be non-bufferable, trusted for R/W,
	128	* not forced to user-mode.
	129	*/
	130	writel(0x77777777, &aips3->mprot0);
	131	writel(0x77777777, &aips3->mprot1);
	132
	133	/*
	134	* Set all OPACRx to be non-bufferable, not require
	135	* supervisor privilege level for access,allow for
	136	* write access and untrusted master access.
	137	*/
	138	writel(0x00000000, &aips3->opacr0);
	139	writel(0x00000000, &aips3->opacr1);
	140	writel(0x00000000, &aips3->opacr2);
	141	writel(0x00000000, &aips3->opacr3);
	142	writel(0x00000000, &aips3->opacr4);
	143	#endif
23608e23 JL	144	}
23608e23 JL	145
e113fd19 FE	146	static void clear_ldo_ramp(void)
	147	{
	148	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	149	int reg;
	150
	151	/* ROM may modify LDO ramp up time according to fuse setting, so in
	152	* order to be in the safe side we neeed to reset these settings to
	153	* match the reset value: 0'b00
	154	*/
	155	reg = readl(&anatop->ana_misc2);
	156	reg &= ~(0x3f << 24);
	157	writel(reg, &anatop->ana_misc2);
	158	}
	159
cac833a9	160	/*
157f45da	161	* Set the PMU_REG_CORE register
cac833a9	162	*
157f45da	163	* Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
cac833a9 DB	164	* Possible values are from 0.725V to 1.450V in steps of
	165	* 0.025V (25mV).
	166	*/
3d622b78	167	static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
cac833a9 DB	168	{
cac833a9 DB	169	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
39f0ac93	170	u32 val, step, old, reg = readl(&anatop->reg_core);
3d622b78	171	u8 shift;
cac833a9 DB	172
	173	if (mv < 725)
	174	val = 0x00; /* Power gated off */
	175	else if (mv > 1450)
	176	val = 0x1F; /* Power FET switched full on. No regulation */
	177	else
	178	val = (mv - 700) / 25;
	179
e113fd19 FE	180	clear_ldo_ramp();
e113fd19 FE	181
3d622b78 FE	182	switch (ldo) {
	183	case LDO_SOC:
	184	shift = 18;
	185	break;
	186	case LDO_PU:
	187	shift = 9;
	188	break;
	189	case LDO_ARM:
	190	shift = 0;
	191	break;
	192	default:
	193	return -EINVAL;
	194	}
	195
39f0ac93 FE	196	old = (reg & (0x1F << shift)) >> shift;
	197	step = abs(val - old);
	198	if (step == 0)
	199	return 0;
	200
3d622b78	201	reg = (reg & ~(0x1F << shift)) \| (val << shift);
cac833a9	202	writel(reg, &anatop->reg_core);
3d622b78	203
39f0ac93 FE	204	/*
	205	* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	206	* step
	207	*/
	208	udelay(3 * step);
	209
3d622b78	210	return 0;
cac833a9 DB	211	}
cac833a9 DB	212
76c91e66 FE	213	static void imx_set_wdog_powerdown(bool enable)
	214	{
	215	struct wdog_regs wdog1 = (struct wdog_regs )WDOG1_BASE_ADDR;
	216	struct wdog_regs wdog2 = (struct wdog_regs )WDOG2_BASE_ADDR;
	217
	218	/* Write to the PDE (Power Down Enable) bit */
	219	writew(enable, &wdog1->wmcr);
	220	writew(enable, &wdog2->wmcr);
	221	}
	222
5c92edc2 AH	223	static void set_ahb_rate(u32 val)
	224	{
	225	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	226	u32 reg, div;
	227
	228	div = get_periph_clk() / val - 1;
	229	reg = readl(&mxc_ccm->cbcdr);
	230
	231	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) \|
	232	(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
	233	}
	234
16197bb8 AH	235	static void clear_mmdc_ch_mask(void)
	236	{
	237	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	238
	239	/* Clear MMDC channel mask */
	240	writel(0, &mxc_ccm->ccdr);
	241	}
	242
0f8ec145 YL	243	#ifdef CONFIG_MX6SL
	244	static void set_preclk_from_osc(void)
	245	{
	246	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	247	u32 reg;
	248
	249	reg = readl(&mxc_ccm->cscmr1);
	250	reg \|= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	251	writel(reg, &mxc_ccm->cscmr1);
	252	}
	253	#endif
	254
23608e23 JL	255	int arch_cpu_init(void)
	256	{
	257	init_aips();
	258
16197bb8 AH	259	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	260	clear_mmdc_ch_mask();
	261
5c92edc2 AH	262	/*
	263	* When low freq boot is enabled, ROM will not set AHB
	264	* freq, so we need to ensure AHB freq is 132MHz in such
	265	* scenario.
	266	*/
	267	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
	268	set_ahb_rate(132000000);
	269
0f8ec145 YL	270	/* Set perclk to source from OSC 24MHz */
	271	#if defined(CONFIG_MX6SL)
	272	set_preclk_from_osc();
	273	#endif
	274
76c91e66	275	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
ae695b18 SR	276
	277	#ifdef CONFIG_APBH_DMA
	278	/* Start APBH DMA */
	279	mxs_dma_init();
	280	#endif
	281
23608e23 JL	282	return 0;
23608e23 JL	283	}
23608e23	284
39f0ac93 FE	285	int board_postclk_init(void)
	286	{
	287	set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
	288
	289	return 0;
	290	}
	291
4d422fe2 EN	292	#ifndef CONFIG_SYS_DCACHE_OFF
	293	void enable_caches(void)
	294	{
36c1ca4d NG	295	#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	296	enum dcache_option option = DCACHE_WRITETHROUGH;
	297	#else
	298	enum dcache_option option = DCACHE_WRITEBACK;
	299	#endif
	300
ebaf6b26 FL	301	/* Avoid random hang when download by usb */
ebaf6b26 FL	302	invalidate_dcache_all();
36c1ca4d	303
4d422fe2 EN	304	/* Enable D-cache. I-cache is already enabled in start.S */
4d422fe2 EN	305	dcache_enable();
36c1ca4d NG	306
	307	/* Enable caching on OCRAM and ROM */
	308	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
	309	ROMCP_ARB_END_ADDR,
	310	option);
	311	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
	312	IRAM_SIZE,
	313	option);
4d422fe2 EN	314	}
	315	#endif
	316
23608e23	317	#if defined(CONFIG_FEC_MXC)
be252b65	318	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
23608e23	319	{
8f3ff11c BT	320	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	321	struct fuse_bank *bank = &ocotp->bank[4];
23608e23 JL	322	struct fuse_bank4_regs *fuse =
	323	(struct fuse_bank4_regs *)bank->fuse_regs;
	324
bd2e27c0 JL	325	u32 value = readl(&fuse->mac_addr_high);
	326	mac[0] = (value >> 8);
	327	mac[1] = value ;
23608e23	328
bd2e27c0 JL	329	value = readl(&fuse->mac_addr_low);
	330	mac[2] = value >> 24 ;
	331	mac[3] = value >> 16 ;
	332	mac[4] = value >> 8 ;
	333	mac[5] = value ;
23608e23 JL	334
	335	}
	336	#endif
124a06d7 TK	337
	338	void boot_mode_apply(unsigned cfg_val)
	339	{
	340	unsigned reg;
2af7e810	341	struct src psrc = (struct src )SRC_BASE_ADDR;
124a06d7 TK	342	writel(cfg_val, &psrc->gpr9);
	343	reg = readl(&psrc->gpr10);
	344	if (cfg_val)
	345	reg \|= 1 << 28;
	346	else
	347	reg &= ~(1 << 28);
	348	writel(reg, &psrc->gpr10);
	349	}
	350	/*
	351	* cfg_val will be used for
	352	* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
f2863ff3 NK	353	* After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
f2863ff3 NK	354	* instead of SBMR1 to determine the boot device.
124a06d7 TK	355	*/
	356	const struct boot_mode soc_boot_modes[] = {
	357	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	358	/* reserved value should start rom usb */
	359	{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	360	{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
2d59e3ec ND	361	{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	362	{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	363	{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	364	{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
124a06d7 TK	365	/* 4 bit bus width */
	366	{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	367	{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	368	{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	369	{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	370	{NULL, 0},
	371	};
8f393776 SW	372
	373	void s_init(void)
	374	{
8467faef	375	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
9293d7fd	376	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
8467faef EN	377	u32 mask480;
8467faef EN	378	u32 mask528;
9293d7fd	379	u32 reg, periph1, periph2;
a3df99b5 FE	380
	381	if (is_cpu_type(MXC_CPU_MX6SX))
	382	return;
	383
8467faef EN	384	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	385	* to make sure PFD is working right, otherwise, PFDs may
	386	* not output clock after reset, MX6DL and MX6SL have added 396M pfd
	387	* workaround in ROM code, as bus clock need it
	388	*/
	389
	390	mask480 = ANATOP_PFD_CLKGATE_MASK(0) \|
	391	ANATOP_PFD_CLKGATE_MASK(1) \|
	392	ANATOP_PFD_CLKGATE_MASK(2) \|
	393	ANATOP_PFD_CLKGATE_MASK(3);
9293d7fd	394	mask528 = ANATOP_PFD_CLKGATE_MASK(1) \|
8467faef EN	395	ANATOP_PFD_CLKGATE_MASK(3);
8467faef EN	396
9293d7fd YL	397	reg = readl(&ccm->cbcmr);
	398	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
	399	>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	400	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
	401	>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
	402
	403	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	404	if ((periph2 != 0x2) && (periph1 != 0x2))
	405	mask528 \|= ANATOP_PFD_CLKGATE_MASK(0);
	406
	407	if ((periph2 != 0x1) && (periph1 != 0x1) &&
	408	(periph2 != 0x3) && (periph1 != 0x3))
8467faef	409	mask528 \|= ANATOP_PFD_CLKGATE_MASK(2);
9293d7fd	410
8467faef EN	411	writel(mask480, &anatop->pfd_480_set);
	412	writel(mask528, &anatop->pfd_528_set);
	413	writel(mask480, &anatop->pfd_480_clr);
	414	writel(mask528, &anatop->pfd_528_clr);
8f393776	415	}
5ea7f0e3 PKS	416
	417	#ifdef CONFIG_IMX_HDMI
	418	void imx_enable_hdmi_phy(void)
	419	{
	420	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	421	u8 reg;
	422	reg = readb(&hdmi->phy_conf0);
	423	reg \|= HDMI_PHY_CONF0_PDZ_MASK;
	424	writeb(reg, &hdmi->phy_conf0);
	425	udelay(3000);
	426	reg \|= HDMI_PHY_CONF0_ENTMDS_MASK;
	427	writeb(reg, &hdmi->phy_conf0);
	428	udelay(3000);
	429	reg \|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	430	writeb(reg, &hdmi->phy_conf0);
	431	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
	432	}
	433
	434	void imx_setup_hdmi(void)
	435	{
	436	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	437	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	438	int reg;
	439
	440	/* Turn on HDMI PHY clock */
	441	reg = readl(&mxc_ccm->CCGR2);
	442	reg \|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK\|
	443	MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	444	writel(reg, &mxc_ccm->CCGR2);
	445	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	446	reg = readl(&mxc_ccm->chsccdr);
	447	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK\|
	448	MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK\|
	449	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	450	reg \|= (CHSCCDR_PODF_DIVIDE_BY_3
	451	<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
	452	\|(CHSCCDR_IPU_PRE_CLK_540M_PFD
	453	<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	454	writel(reg, &mxc_ccm->chsccdr);
	455	}
	456	#endif
6d73c234 FE	457
	458	#ifndef CONFIG_SYS_L2CACHE_OFF
	459	#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
	460	void v7_outer_cache_enable(void)
	461	{
	462	struct pl310_regs const pl310 = (struct pl310_regs )L2_PL310_BASE;
	463	unsigned int val;
	464
	465	#if defined CONFIG_MX6SL
	466	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	467	val = readl(&iomux->gpr[11]);
	468	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
	469	/* L2 cache configured as OCRAM, reset it */
	470	val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
	471	writel(val, &iomux->gpr[11]);
	472	}
	473	#endif
	474
4aa7ac30 YL	475	/* Must disable the L2 before changing the latency parameters */
	476	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	477
6d73c234 FE	478	writel(0x132, &pl310->pl310_tag_latency_ctrl);
	479	writel(0x132, &pl310->pl310_data_latency_ctrl);
	480
	481	val = readl(&pl310->pl310_prefetch_ctrl);
	482
	483	/* Turn on the L2 I/D prefetch */
	484	val \|= 0x30000000;
	485
	486	/*
	487	* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
	488	* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
	489	* But according to ARM PL310 errata: 752271
	490	* ID: 752271: Double linefill feature can cause data corruption
	491	* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
	492	* Workaround: The only workaround to this erratum is to disable the
	493	* double linefill feature. This is the default behavior.
	494	*/
	495
	496	#ifndef CONFIG_MX6Q
	497	val \|= 0x40800000;
	498	#endif
	499	writel(val, &pl310->pl310_prefetch_ctrl);
	500
	501	val = readl(&pl310->pl310_power_ctrl);
	502	val \|= L2X0_DYNAMIC_CLK_GATING_EN;
	503	val \|= L2X0_STNDBY_MODE_EN;
	504	writel(val, &pl310->pl310_power_ctrl);
	505
	506	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	507	}
	508
	509	void v7_outer_cache_disable(void)
	510	{
	511	struct pl310_regs const pl310 = (struct pl310_regs )L2_PL310_BASE;
	512
	513	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	514	}
	515	#endif /* !CONFIG_SYS_L2CACHE_OFF */