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c5752f73 AA |
1 | /* |
2 | * Copyright (C) 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
9 | #include <asm/arch/imx-regs.h> | |
10 | #include <asm/arch/clock.h> | |
11 | #include <asm/arch/sys_proto.h> | |
12 | #include <asm/imx-common/boot_mode.h> | |
13 | #include <asm/imx-common/dma.h> | |
bb955146 | 14 | #include <asm/imx-common/hab.h> |
35c4ce5e PF |
15 | #include <asm/imx-common/rdc-sema.h> |
16 | #include <asm/arch/imx-rdc.h> | |
c5752f73 AA |
17 | #include <asm/arch/crm_regs.h> |
18 | #include <dm.h> | |
19 | #include <imx_thermal.h> | |
20 | ||
c5752f73 AA |
21 | #if defined(CONFIG_IMX_THERMAL) |
22 | static const struct imx_thermal_plat imx7_thermal_plat = { | |
23 | .regs = (void *)ANATOP_BASE_ADDR, | |
24 | .fuse_bank = 3, | |
25 | .fuse_word = 3, | |
26 | }; | |
27 | ||
28 | U_BOOT_DEVICE(imx7_thermal) = { | |
29 | .name = "imx_thermal", | |
30 | .platdata = &imx7_thermal_plat, | |
31 | }; | |
32 | #endif | |
33 | ||
35c4ce5e PF |
34 | #ifdef CONFIG_IMX_RDC |
35 | /* | |
36 | * In current design, if any peripheral was assigned to both A7 and M4, | |
37 | * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter | |
38 | * low power mode. So M4 sleep will cause some peripherals fail to work | |
39 | * at A7 core side. At default, all resources are in domain 0 - 3. | |
40 | * | |
41 | * There are 26 peripherals impacted by this IC issue: | |
42 | * SIM2(sim2/emvsim2) | |
43 | * SIM1(sim1/emvsim1) | |
44 | * UART1/UART2/UART3/UART4/UART5/UART6/UART7 | |
45 | * SAI1/SAI2/SAI3 | |
46 | * WDOG1/WDOG2/WDOG3/WDOG4 | |
47 | * GPT1/GPT2/GPT3/GPT4 | |
48 | * PWM1/PWM2/PWM3/PWM4 | |
49 | * ENET1/ENET2 | |
50 | * Software Workaround: | |
51 | * Here we setup some resources to domain 0 where M4 codes will move | |
52 | * the M4 out of this domain. Then M4 is not able to access them any longer. | |
53 | * This is a workaround for ic issue. So the peripherals are not shared | |
54 | * by them. This way requires the uboot implemented the RDC driver and | |
55 | * set the 26 IPs above to domain 0 only. M4 code will assign resource | |
56 | * to its own domain, if it want to use the resource. | |
57 | */ | |
58 | static rdc_peri_cfg_t const resources[] = { | |
59 | (RDC_PER_SIM1 | RDC_DOMAIN(0)), | |
60 | (RDC_PER_SIM2 | RDC_DOMAIN(0)), | |
61 | (RDC_PER_UART1 | RDC_DOMAIN(0)), | |
62 | (RDC_PER_UART2 | RDC_DOMAIN(0)), | |
63 | (RDC_PER_UART3 | RDC_DOMAIN(0)), | |
64 | (RDC_PER_UART4 | RDC_DOMAIN(0)), | |
65 | (RDC_PER_UART5 | RDC_DOMAIN(0)), | |
66 | (RDC_PER_UART6 | RDC_DOMAIN(0)), | |
67 | (RDC_PER_UART7 | RDC_DOMAIN(0)), | |
68 | (RDC_PER_SAI1 | RDC_DOMAIN(0)), | |
69 | (RDC_PER_SAI2 | RDC_DOMAIN(0)), | |
70 | (RDC_PER_SAI3 | RDC_DOMAIN(0)), | |
71 | (RDC_PER_WDOG1 | RDC_DOMAIN(0)), | |
72 | (RDC_PER_WDOG2 | RDC_DOMAIN(0)), | |
73 | (RDC_PER_WDOG3 | RDC_DOMAIN(0)), | |
74 | (RDC_PER_WDOG4 | RDC_DOMAIN(0)), | |
75 | (RDC_PER_GPT1 | RDC_DOMAIN(0)), | |
76 | (RDC_PER_GPT2 | RDC_DOMAIN(0)), | |
77 | (RDC_PER_GPT3 | RDC_DOMAIN(0)), | |
78 | (RDC_PER_GPT4 | RDC_DOMAIN(0)), | |
79 | (RDC_PER_PWM1 | RDC_DOMAIN(0)), | |
80 | (RDC_PER_PWM2 | RDC_DOMAIN(0)), | |
81 | (RDC_PER_PWM3 | RDC_DOMAIN(0)), | |
82 | (RDC_PER_PWM4 | RDC_DOMAIN(0)), | |
83 | (RDC_PER_ENET1 | RDC_DOMAIN(0)), | |
84 | (RDC_PER_ENET2 | RDC_DOMAIN(0)), | |
85 | }; | |
86 | ||
87 | static void isolate_resource(void) | |
88 | { | |
89 | imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources)); | |
90 | } | |
91 | #endif | |
92 | ||
bb955146 AA |
93 | #if defined(CONFIG_SECURE_BOOT) |
94 | struct imx_sec_config_fuse_t const imx_sec_config_fuse = { | |
95 | .bank = 1, | |
96 | .word = 3, | |
97 | }; | |
98 | #endif | |
99 | ||
c5752f73 AA |
100 | /* |
101 | * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) | |
102 | * defines a 2-bit SPEED_GRADING | |
103 | */ | |
104 | #define OCOTP_TESTER3_SPEED_SHIFT 8 | |
105 | #define OCOTP_TESTER3_SPEED_800MHZ 0 | |
31b8a901 | 106 | #define OCOTP_TESTER3_SPEED_500MHZ 1 |
c5752f73 AA |
107 | #define OCOTP_TESTER3_SPEED_1GHZ 2 |
108 | ||
109 | u32 get_cpu_speed_grade_hz(void) | |
110 | { | |
111 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
112 | struct fuse_bank *bank = &ocotp->bank[1]; | |
113 | struct fuse_bank1_regs *fuse = | |
114 | (struct fuse_bank1_regs *)bank->fuse_regs; | |
115 | uint32_t val; | |
116 | ||
117 | val = readl(&fuse->tester3); | |
118 | val >>= OCOTP_TESTER3_SPEED_SHIFT; | |
119 | val &= 0x3; | |
120 | ||
121 | switch(val) { | |
122 | case OCOTP_TESTER3_SPEED_800MHZ: | |
123 | return 792000000; | |
31b8a901 FE |
124 | case OCOTP_TESTER3_SPEED_500MHZ: |
125 | return 500000000; | |
c5752f73 AA |
126 | case OCOTP_TESTER3_SPEED_1GHZ: |
127 | return 996000000; | |
128 | } | |
129 | return 0; | |
130 | } | |
131 | ||
132 | /* | |
133 | * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440) | |
134 | * defines a 2-bit SPEED_GRADING | |
135 | */ | |
136 | #define OCOTP_TESTER3_TEMP_SHIFT 6 | |
137 | ||
138 | u32 get_cpu_temp_grade(int *minc, int *maxc) | |
139 | { | |
140 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
141 | struct fuse_bank *bank = &ocotp->bank[1]; | |
142 | struct fuse_bank1_regs *fuse = | |
143 | (struct fuse_bank1_regs *)bank->fuse_regs; | |
144 | uint32_t val; | |
145 | ||
146 | val = readl(&fuse->tester3); | |
147 | val >>= OCOTP_TESTER3_TEMP_SHIFT; | |
148 | val &= 0x3; | |
149 | ||
150 | if (minc && maxc) { | |
f697c2ac | 151 | if (val == TEMP_AUTOMOTIVE) { |
c5752f73 AA |
152 | *minc = -40; |
153 | *maxc = 125; | |
154 | } else if (val == TEMP_INDUSTRIAL) { | |
155 | *minc = -40; | |
156 | *maxc = 105; | |
157 | } else if (val == TEMP_EXTCOMMERCIAL) { | |
158 | *minc = -20; | |
159 | *maxc = 105; | |
160 | } else { | |
161 | *minc = 0; | |
162 | *maxc = 95; | |
163 | } | |
164 | } | |
165 | return val; | |
166 | } | |
167 | ||
e25a0656 FE |
168 | static bool is_mx7d(void) |
169 | { | |
170 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
171 | struct fuse_bank *bank = &ocotp->bank[1]; | |
172 | struct fuse_bank1_regs *fuse = | |
173 | (struct fuse_bank1_regs *)bank->fuse_regs; | |
174 | int val; | |
175 | ||
176 | val = readl(&fuse->tester4); | |
177 | if (val & 1) | |
178 | return false; | |
179 | else | |
180 | return true; | |
181 | } | |
182 | ||
c5752f73 AA |
183 | u32 get_cpu_rev(void) |
184 | { | |
185 | struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) | |
186 | ANATOP_BASE_ADDR; | |
187 | u32 reg = readl(&ccm_anatop->digprog); | |
188 | u32 type = (reg >> 16) & 0xff; | |
189 | ||
e25a0656 FE |
190 | if (!is_mx7d()) |
191 | type = MXC_CPU_MX7S; | |
192 | ||
c5752f73 AA |
193 | reg &= 0xff; |
194 | return (type << 12) | reg; | |
195 | } | |
196 | ||
197 | #ifdef CONFIG_REVISION_TAG | |
198 | u32 __weak get_board_rev(void) | |
199 | { | |
200 | return get_cpu_rev(); | |
201 | } | |
202 | #endif | |
203 | ||
7de47036 PF |
204 | /* enable all periherial can be accessed in nosec mode */ |
205 | static void init_csu(void) | |
206 | { | |
207 | int i = 0; | |
208 | for (i = 0; i < CSU_NUM_REGS; i++) | |
209 | writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4); | |
210 | } | |
211 | ||
d9699de8 PF |
212 | static void imx_enet_mdio_fixup(void) |
213 | { | |
214 | struct iomuxc_gpr_base_regs *gpr_regs = | |
215 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; | |
216 | ||
217 | /* | |
218 | * The management data input/output (MDIO) requires open-drain, | |
219 | * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports | |
220 | * this feature. So to TO1.1, need to enable open drain by setting | |
221 | * bits GPR0[8:7]. | |
222 | */ | |
223 | ||
224 | if (soc_rev() >= CHIP_REV_1_1) { | |
225 | setbits_le32(&gpr_regs->gpr[0], | |
226 | IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); | |
227 | } | |
228 | } | |
229 | ||
c5752f73 AA |
230 | int arch_cpu_init(void) |
231 | { | |
232 | init_aips(); | |
233 | ||
7de47036 | 234 | init_csu(); |
c5752f73 AA |
235 | /* Disable PDE bit of WMCR register */ |
236 | imx_set_wdog_powerdown(false); | |
237 | ||
d9699de8 PF |
238 | imx_enet_mdio_fixup(); |
239 | ||
c5752f73 AA |
240 | #ifdef CONFIG_APBH_DMA |
241 | /* Start APBH DMA */ | |
242 | mxs_dma_init(); | |
243 | #endif | |
244 | ||
35c4ce5e PF |
245 | if (IS_ENABLED(CONFIG_IMX_RDC)) |
246 | isolate_resource(); | |
247 | ||
c5752f73 AA |
248 | return 0; |
249 | } | |
250 | ||
ec7fde3e SA |
251 | #ifdef CONFIG_ARCH_MISC_INIT |
252 | int arch_misc_init(void) | |
253 | { | |
254 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
255 | if (is_mx7d()) | |
256 | setenv("soc", "imx7d"); | |
257 | else | |
258 | setenv("soc", "imx7s"); | |
259 | #endif | |
260 | ||
261 | return 0; | |
262 | } | |
263 | #endif | |
264 | ||
c5752f73 AA |
265 | #ifdef CONFIG_SERIAL_TAG |
266 | void get_board_serial(struct tag_serialnr *serialnr) | |
267 | { | |
268 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
269 | struct fuse_bank *bank = &ocotp->bank[0]; | |
270 | struct fuse_bank0_regs *fuse = | |
271 | (struct fuse_bank0_regs *)bank->fuse_regs; | |
272 | ||
273 | serialnr->low = fuse->tester0; | |
274 | serialnr->high = fuse->tester1; | |
275 | } | |
276 | #endif | |
277 | ||
278 | #if defined(CONFIG_FEC_MXC) | |
279 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) | |
280 | { | |
281 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
282 | struct fuse_bank *bank = &ocotp->bank[9]; | |
283 | struct fuse_bank9_regs *fuse = | |
284 | (struct fuse_bank9_regs *)bank->fuse_regs; | |
285 | ||
286 | if (0 == dev_id) { | |
287 | u32 value = readl(&fuse->mac_addr1); | |
288 | mac[0] = (value >> 8); | |
289 | mac[1] = value; | |
290 | ||
291 | value = readl(&fuse->mac_addr0); | |
292 | mac[2] = value >> 24; | |
293 | mac[3] = value >> 16; | |
294 | mac[4] = value >> 8; | |
295 | mac[5] = value; | |
296 | } else { | |
297 | u32 value = readl(&fuse->mac_addr2); | |
298 | mac[0] = value >> 24; | |
299 | mac[1] = value >> 16; | |
300 | mac[2] = value >> 8; | |
301 | mac[3] = value; | |
302 | ||
303 | value = readl(&fuse->mac_addr1); | |
304 | mac[4] = value >> 24; | |
305 | mac[5] = value >> 16; | |
306 | } | |
307 | } | |
308 | #endif | |
309 | ||
83703a1c PF |
310 | #ifdef CONFIG_IMX_BOOTAUX |
311 | int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) | |
312 | { | |
313 | u32 stack, pc; | |
314 | struct src *src_reg = (struct src *)SRC_BASE_ADDR; | |
315 | ||
316 | if (!boot_private_data) | |
317 | return 1; | |
318 | ||
319 | stack = *(u32 *)boot_private_data; | |
320 | pc = *(u32 *)(boot_private_data + 4); | |
321 | ||
322 | /* Set the stack and pc to M4 bootROM */ | |
323 | writel(stack, M4_BOOTROM_BASE_ADDR); | |
324 | writel(pc, M4_BOOTROM_BASE_ADDR + 4); | |
325 | ||
326 | /* Enable M4 */ | |
327 | clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK, | |
328 | SRC_M4RCR_ENABLE_M4_MASK); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | int arch_auxiliary_core_check_up(u32 core_id) | |
334 | { | |
335 | uint32_t val; | |
336 | struct src *src_reg = (struct src *)SRC_BASE_ADDR; | |
337 | ||
338 | val = readl(&src_reg->m4rcr); | |
339 | if (val & 0x00000001) | |
340 | return 0; /* assert in reset */ | |
341 | ||
342 | return 1; | |
343 | } | |
344 | #endif | |
345 | ||
c5752f73 AA |
346 | void set_wdog_reset(struct wdog_regs *wdog) |
347 | { | |
348 | u32 reg = readw(&wdog->wcr); | |
349 | /* | |
350 | * Output WDOG_B signal to reset external pmic or POR_B decided by | |
351 | * the board desgin. Without external reset, the peripherals/DDR/ | |
352 | * PMIC are not reset, that may cause system working abnormal. | |
353 | */ | |
354 | reg = readw(&wdog->wcr); | |
355 | reg |= 1 << 3; | |
356 | /* | |
357 | * WDZST bit is write-once only bit. Align this bit in kernel, | |
358 | * otherwise kernel code will have no chance to set this bit. | |
359 | */ | |
360 | reg |= 1 << 0; | |
361 | writew(reg, &wdog->wcr); | |
362 | } | |
363 | ||
364 | /* | |
365 | * cfg_val will be used for | |
366 | * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] | |
367 | * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] | |
368 | * to SBMR1, which will determine the boot device. | |
369 | */ | |
370 | const struct boot_mode soc_boot_modes[] = { | |
371 | {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)}, | |
372 | {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)}, | |
373 | {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)}, | |
374 | {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)}, | |
375 | ||
376 | {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)}, | |
377 | {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)}, | |
378 | /* 4 bit bus width */ | |
379 | {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, | |
380 | {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)}, | |
381 | {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)}, | |
382 | {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)}, | |
383 | {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)}, | |
384 | {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)}, | |
385 | {NULL, 0}, | |
386 | }; | |
387 | ||
388 | enum boot_device get_boot_device(void) | |
389 | { | |
390 | struct bootrom_sw_info **p = | |
391 | (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; | |
392 | ||
393 | enum boot_device boot_dev = SD1_BOOT; | |
394 | u8 boot_type = (*p)->boot_dev_type; | |
395 | u8 boot_instance = (*p)->boot_dev_instance; | |
396 | ||
397 | switch (boot_type) { | |
398 | case BOOT_TYPE_SD: | |
399 | boot_dev = boot_instance + SD1_BOOT; | |
400 | break; | |
401 | case BOOT_TYPE_MMC: | |
402 | boot_dev = boot_instance + MMC1_BOOT; | |
403 | break; | |
404 | case BOOT_TYPE_NAND: | |
405 | boot_dev = NAND_BOOT; | |
406 | break; | |
407 | case BOOT_TYPE_QSPI: | |
408 | boot_dev = QSPI_BOOT; | |
409 | break; | |
410 | case BOOT_TYPE_WEIM: | |
411 | boot_dev = WEIM_NOR_BOOT; | |
412 | break; | |
413 | case BOOT_TYPE_SPINOR: | |
414 | boot_dev = SPI_NOR_BOOT; | |
415 | break; | |
416 | default: | |
417 | break; | |
418 | } | |
419 | ||
420 | return boot_dev; | |
421 | } | |
422 | ||
62d8cce9 PF |
423 | #ifdef CONFIG_ENV_IS_IN_MMC |
424 | __weak int board_mmc_get_env_dev(int devno) | |
425 | { | |
426 | return CONFIG_SYS_MMC_ENV_DEV; | |
427 | } | |
428 | ||
429 | int mmc_get_env_dev(void) | |
430 | { | |
431 | struct bootrom_sw_info **p = | |
432 | (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; | |
433 | int devno = (*p)->boot_dev_instance; | |
434 | u8 boot_type = (*p)->boot_dev_type; | |
435 | ||
436 | /* If not boot from sd/mmc, use default value */ | |
437 | if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) | |
438 | return CONFIG_SYS_MMC_ENV_DEV; | |
439 | ||
440 | return board_mmc_get_env_dev(devno); | |
441 | } | |
442 | #endif | |
443 | ||
c5752f73 AA |
444 | void s_init(void) |
445 | { | |
446 | #if !defined CONFIG_SPL_BUILD | |
447 | /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ | |
448 | asm volatile( | |
449 | "mrc p15, 0, r0, c1, c0, 1\n" | |
450 | "orr r0, r0, #1 << 6\n" | |
451 | "mcr p15, 0, r0, c1, c0, 1\n"); | |
452 | #endif | |
453 | /* clock configuration. */ | |
454 | clock_init(); | |
455 | ||
456 | return; | |
457 | } | |
9f8fa184 PF |
458 | |
459 | void reset_misc(void) | |
460 | { | |
461 | #ifdef CONFIG_VIDEO_MXS | |
462 | lcdif_power_down(); | |
463 | #endif | |
464 | } | |
465 |