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2ae610f0 A |
1 | /* |
2 | * EMIF programming | |
3 | * | |
4 | * (C) Copyright 2010 | |
5 | * Texas Instruments, <www.ti.com> | |
6 | * | |
7 | * Aneesh V <aneesh@ti.com> | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
2ae610f0 A |
10 | */ |
11 | ||
12 | #include <common.h> | |
bb772a59 | 13 | #include <asm/emif.h> |
af1d002f | 14 | #include <asm/arch/clock.h> |
2ae610f0 A |
15 | #include <asm/arch/sys_proto.h> |
16 | #include <asm/omap_common.h> | |
17 | #include <asm/utils.h> | |
25476382 | 18 | #include <linux/compiler.h> |
2ae610f0 | 19 | |
86021143 LV |
20 | static int emif1_enabled = -1, emif2_enabled = -1; |
21 | ||
38f25b12 LV |
22 | void set_lpmode_selfrefresh(u32 base) |
23 | { | |
24 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
25 | u32 reg; | |
26 | ||
27 | reg = readl(&emif->emif_pwr_mgmt_ctrl); | |
28 | reg &= ~EMIF_REG_LP_MODE_MASK; | |
29 | reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; | |
30 | reg &= ~EMIF_REG_SR_TIM_MASK; | |
31 | writel(reg, &emif->emif_pwr_mgmt_ctrl); | |
32 | ||
33 | /* dummy read for the new SR_TIM to be loaded */ | |
34 | readl(&emif->emif_pwr_mgmt_ctrl); | |
35 | } | |
36 | ||
37 | void force_emif_self_refresh() | |
38 | { | |
39 | set_lpmode_selfrefresh(EMIF1_BASE); | |
40 | set_lpmode_selfrefresh(EMIF2_BASE); | |
41 | } | |
42 | ||
bb772a59 | 43 | inline u32 emif_num(u32 base) |
2ae610f0 | 44 | { |
bb772a59 | 45 | if (base == EMIF1_BASE) |
2ae610f0 | 46 | return 1; |
bb772a59 | 47 | else if (base == EMIF2_BASE) |
2ae610f0 A |
48 | return 2; |
49 | else | |
50 | return 0; | |
51 | } | |
52 | ||
53 | static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) | |
54 | { | |
55 | u32 mr; | |
56 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
57 | ||
bb772a59 | 58 | mr_addr |= cs << EMIF_REG_CS_SHIFT; |
2ae610f0 A |
59 | writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); |
60 | if (omap_revision() == OMAP4430_ES2_0) | |
61 | mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); | |
62 | else | |
63 | mr = readl(&emif->emif_lpddr2_mode_reg_data); | |
64 | debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), | |
65 | cs, mr_addr, mr); | |
55c12849 SS |
66 | if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && |
67 | ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && | |
68 | ((mr & 0xff000000) >> 24) == (mr & 0xff)) | |
69 | return mr & 0xff; | |
70 | else | |
71 | return mr; | |
2ae610f0 A |
72 | } |
73 | ||
74 | static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) | |
75 | { | |
76 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
77 | ||
bb772a59 | 78 | mr_addr |= cs << EMIF_REG_CS_SHIFT; |
2ae610f0 A |
79 | writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); |
80 | writel(mr_val, &emif->emif_lpddr2_mode_reg_data); | |
81 | } | |
82 | ||
83 | void emif_reset_phy(u32 base) | |
84 | { | |
85 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
86 | u32 iodft; | |
87 | ||
88 | iodft = readl(&emif->emif_iodft_tlgc); | |
bb772a59 | 89 | iodft |= EMIF_REG_RESET_PHY_MASK; |
2ae610f0 A |
90 | writel(iodft, &emif->emif_iodft_tlgc); |
91 | } | |
92 | ||
93 | static void do_lpddr2_init(u32 base, u32 cs) | |
94 | { | |
95 | u32 mr_addr; | |
e05a4f1f | 96 | const struct lpddr2_mr_regs *mr_regs; |
2ae610f0 | 97 | |
e05a4f1f | 98 | get_lpddr2_mr_regs(&mr_regs); |
2ae610f0 A |
99 | /* Wait till device auto initialization is complete */ |
100 | while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) | |
101 | ; | |
e05a4f1f | 102 | set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); |
2ae610f0 A |
103 | /* |
104 | * tZQINIT = 1 us | |
105 | * Enough loops assuming a maximum of 2GHz | |
106 | */ | |
f4010734 | 107 | |
2ae610f0 | 108 | sdelay(2000); |
f4010734 | 109 | |
e05a4f1f LV |
110 | set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); |
111 | set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); | |
f4010734 | 112 | |
2ae610f0 A |
113 | /* |
114 | * Enable refresh along with writing MR2 | |
115 | * Encoding of RL in MR2 is (RL - 2) | |
116 | */ | |
bb772a59 | 117 | mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; |
e05a4f1f | 118 | set_mr(base, cs, mr_addr, mr_regs->mr2); |
f4010734 | 119 | |
e05a4f1f LV |
120 | if (mr_regs->mr3 > 0) |
121 | set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); | |
2ae610f0 A |
122 | } |
123 | ||
124 | static void lpddr2_init(u32 base, const struct emif_regs *regs) | |
125 | { | |
126 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
127 | ||
128 | /* Not NVM */ | |
bb772a59 | 129 | clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); |
2ae610f0 A |
130 | |
131 | /* | |
132 | * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM | |
133 | * when EMIF_SDRAM_CONFIG register is written | |
134 | */ | |
bb772a59 | 135 | setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); |
2ae610f0 A |
136 | |
137 | /* | |
138 | * Set the SDRAM_CONFIG and PHY_CTRL for the | |
139 | * un-locked frequency & default RL | |
140 | */ | |
141 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
0474fb0e | 142 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); |
f4010734 | 143 | |
25476382 | 144 | do_ext_phy_settings(base, regs); |
2ae610f0 A |
145 | |
146 | do_lpddr2_init(base, CS0); | |
bb772a59 | 147 | if (regs->sdram_config & EMIF_REG_EBANK_MASK) |
2ae610f0 A |
148 | do_lpddr2_init(base, CS1); |
149 | ||
150 | writel(regs->sdram_config, &emif->emif_sdram_config); | |
151 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); | |
152 | ||
153 | /* Enable refresh now */ | |
bb772a59 | 154 | clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); |
2ae610f0 | 155 | |
25476382 S |
156 | } |
157 | ||
158 | __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) | |
159 | { | |
2ae610f0 A |
160 | } |
161 | ||
bb772a59 | 162 | void emif_update_timings(u32 base, const struct emif_regs *regs) |
2ae610f0 A |
163 | { |
164 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
165 | ||
166 | writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); | |
167 | writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); | |
168 | writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); | |
169 | writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); | |
170 | if (omap_revision() == OMAP4430_ES1_0) { | |
171 | /* ES1 bug EMIF should be in force idle during freq_update */ | |
172 | writel(0, &emif->emif_pwr_mgmt_ctrl); | |
173 | } else { | |
174 | writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); | |
175 | writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); | |
176 | } | |
177 | writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); | |
178 | writel(regs->zq_config, &emif->emif_zq_config); | |
179 | writel(regs->temp_alert_config, &emif->emif_temp_alert_config); | |
180 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); | |
924eb369 | 181 | |
3ac8c0bf | 182 | if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { |
bb772a59 S |
183 | writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, |
184 | &emif->emif_l3_config); | |
185 | } else if (omap_revision() >= OMAP4460_ES1_0) { | |
924eb369 A |
186 | writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, |
187 | &emif->emif_l3_config); | |
188 | } else { | |
189 | writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, | |
190 | &emif->emif_l3_config); | |
2ae610f0 A |
191 | } |
192 | } | |
193 | ||
6c70935d | 194 | static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) |
784ab7c5 LV |
195 | { |
196 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
197 | ||
198 | /* keep sdram in self-refresh */ | |
199 | writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) | |
200 | & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); | |
201 | __udelay(130); | |
202 | ||
203 | /* | |
204 | * Set invert_clkout (if activated)--DDR_PHYCTRL_1 | |
6c70935d S |
205 | * Invert clock adds an additional half cycle delay on the |
206 | * command interface. The additional half cycle, is usually | |
207 | * meant to enable leveling in the situation that DQS is later | |
208 | * than CK on the board.It also helps provide some additional | |
209 | * margin for leveling. | |
784ab7c5 | 210 | */ |
6c70935d S |
211 | writel(regs->emif_ddr_phy_ctlr_1, |
212 | &emif->emif_ddr_phy_ctrl_1); | |
213 | ||
214 | writel(regs->emif_ddr_phy_ctlr_1, | |
215 | &emif->emif_ddr_phy_ctrl_1_shdw); | |
784ab7c5 LV |
216 | __udelay(130); |
217 | ||
218 | writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) | |
6c70935d | 219 | & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); |
784ab7c5 LV |
220 | |
221 | /* Launch Full leveling */ | |
222 | writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); | |
223 | ||
224 | /* Wait till full leveling is complete */ | |
225 | readl(&emif->emif_rd_wr_lvl_ctl); | |
6c70935d | 226 | __udelay(130); |
784ab7c5 LV |
227 | |
228 | /* Read data eye leveling no of samples */ | |
229 | config_data_eye_leveling_samples(base); | |
230 | ||
6c70935d S |
231 | /* |
232 | * Launch 8 incremental WR_LVL- to compensate for | |
233 | * PHY limitation. | |
234 | */ | |
235 | writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, | |
236 | &emif->emif_rd_wr_lvl_ctl); | |
237 | ||
784ab7c5 LV |
238 | __udelay(130); |
239 | ||
240 | /* Launch Incremental leveling */ | |
241 | writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); | |
6c70935d | 242 | __udelay(130); |
784ab7c5 LV |
243 | } |
244 | ||
6213db78 | 245 | static void update_hwleveling_output(u32 base, const struct emif_regs *regs) |
6c70935d | 246 | { |
6213db78 LV |
247 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
248 | u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; | |
249 | u32 reg, i; | |
250 | ||
251 | emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; | |
252 | ||
253 | /* Update PHY_REG_RDDQS_RATIO */ | |
254 | emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; | |
255 | for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { | |
256 | reg = readl(emif_phy_status++); | |
257 | writel(reg, emif_ext_phy_ctrl_reg++); | |
258 | writel(reg, emif_ext_phy_ctrl_reg++); | |
259 | } | |
260 | ||
261 | /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ | |
262 | emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; | |
263 | for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { | |
264 | reg = readl(emif_phy_status++); | |
265 | writel(reg, emif_ext_phy_ctrl_reg++); | |
266 | writel(reg, emif_ext_phy_ctrl_reg++); | |
267 | } | |
268 | ||
269 | /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ | |
270 | emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; | |
271 | for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { | |
272 | reg = readl(emif_phy_status++); | |
273 | writel(reg, emif_ext_phy_ctrl_reg++); | |
274 | writel(reg, emif_ext_phy_ctrl_reg++); | |
275 | } | |
276 | ||
277 | /* Disable Leveling */ | |
278 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); | |
279 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); | |
280 | writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); | |
92b0482c S |
281 | } |
282 | ||
6213db78 LV |
283 | static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) |
284 | { | |
285 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
286 | ||
287 | /* Clear Error Status */ | |
288 | clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, | |
289 | EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, | |
290 | EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); | |
291 | ||
292 | clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, | |
293 | EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, | |
294 | EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); | |
295 | ||
296 | /* Disable refreshed before leveling */ | |
297 | clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT, | |
298 | EMIF_REG_INITREF_DIS_SHIFT); | |
299 | ||
300 | /* Start Full leveling */ | |
301 | writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); | |
302 | ||
303 | __udelay(300); | |
304 | ||
305 | /* Check for leveling timeout */ | |
306 | if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { | |
307 | printf("Leveling timeout on EMIF%d\n", emif_num(base)); | |
308 | return; | |
309 | } | |
310 | ||
311 | /* Enable refreshes after leveling */ | |
312 | clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT); | |
313 | ||
314 | debug("HW leveling success\n"); | |
315 | /* | |
316 | * Update slave ratios in EXT_PHY_CTRLx registers | |
317 | * as per HW leveling output | |
318 | */ | |
319 | update_hwleveling_output(base, regs); | |
320 | } | |
321 | ||
322 | static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) | |
323 | { | |
324 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
325 | ||
326 | if (warm_reset()) | |
327 | emif_reset_phy(base); | |
328 | do_ext_phy_settings(base, regs); | |
329 | ||
330 | writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, | |
331 | &emif->emif_sdram_ref_ctrl); | |
332 | /* Update timing registers */ | |
333 | writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); | |
334 | writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); | |
335 | writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); | |
336 | ||
337 | writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); | |
338 | writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); | |
339 | writel(regs->zq_config, &emif->emif_zq_config); | |
340 | writel(regs->temp_alert_config, &emif->emif_temp_alert_config); | |
341 | writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); | |
342 | writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); | |
343 | ||
344 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); | |
345 | writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); | |
346 | ||
347 | writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); | |
348 | ||
349 | writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); | |
350 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
351 | ||
352 | __udelay(1000); | |
353 | ||
354 | writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); | |
355 | ||
356 | if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) | |
357 | dra7_ddr3_leveling(base, regs); | |
358 | } | |
359 | ||
360 | static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) | |
784ab7c5 LV |
361 | { |
362 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
784ab7c5 | 363 | |
802bb57a LV |
364 | writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); |
365 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
784ab7c5 LV |
366 | /* |
367 | * Set SDRAM_CONFIG and PHY control registers to locked frequency | |
368 | * and RL =7. As the default values of the Mode Registers are not | |
369 | * defined, contents of mode Registers must be fully initialized. | |
370 | * H/W takes care of this initialization | |
371 | */ | |
784ab7c5 LV |
372 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); |
373 | ||
374 | /* Update timing registers */ | |
375 | writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); | |
376 | writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); | |
377 | writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); | |
378 | ||
784ab7c5 LV |
379 | writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); |
380 | ||
6213db78 LV |
381 | writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); |
382 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
383 | do_ext_phy_settings(base, regs); | |
784ab7c5 | 384 | |
784ab7c5 | 385 | writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); |
6213db78 LV |
386 | omap5_ddr3_leveling(base, regs); |
387 | } | |
784ab7c5 | 388 | |
6213db78 LV |
389 | static void ddr3_init(u32 base, const struct emif_regs *regs) |
390 | { | |
391 | if (is_omap54xx()) | |
392 | omap5_ddr3_init(base, regs); | |
393 | else | |
394 | dra7_ddr3_init(base, regs); | |
784ab7c5 LV |
395 | } |
396 | ||
095aea29 A |
397 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
398 | #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) | |
399 | ||
095aea29 A |
400 | /* |
401 | * Organization and refresh requirements for LPDDR2 devices of different | |
402 | * types and densities. Derived from JESD209-2 section 2.4 | |
403 | */ | |
404 | const struct lpddr2_addressing addressing_table[] = { | |
405 | /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ | |
406 | {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ | |
407 | {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ | |
408 | {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ | |
409 | {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ | |
410 | {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ | |
411 | {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ | |
412 | {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ | |
413 | {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ | |
414 | {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ | |
415 | {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ | |
416 | }; | |
417 | ||
418 | static const u32 lpddr2_density_2_size_in_mbytes[] = { | |
419 | 8, /* 64Mb */ | |
420 | 16, /* 128Mb */ | |
421 | 32, /* 256Mb */ | |
422 | 64, /* 512Mb */ | |
423 | 128, /* 1Gb */ | |
424 | 256, /* 2Gb */ | |
425 | 512, /* 4Gb */ | |
426 | 1024, /* 8Gb */ | |
427 | 2048, /* 16Gb */ | |
428 | 4096 /* 32Gb */ | |
429 | }; | |
430 | ||
431 | /* | |
432 | * Calculate the period of DDR clock from frequency value and set the | |
433 | * denominator and numerator in global variables for easy access later | |
434 | */ | |
435 | static void set_ddr_clk_period(u32 freq) | |
436 | { | |
437 | /* | |
438 | * period = 1/freq | |
439 | * period_in_ns = 10^9/freq | |
440 | */ | |
441 | *T_num = 1000000000; | |
442 | *T_den = freq; | |
443 | cancel_out(T_num, T_den, 200); | |
444 | ||
445 | } | |
446 | ||
447 | /* | |
448 | * Convert time in nano seconds to number of cycles of DDR clock | |
449 | */ | |
450 | static inline u32 ns_2_cycles(u32 ns) | |
451 | { | |
452 | return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); | |
453 | } | |
454 | ||
455 | /* | |
456 | * ns_2_cycles with the difference that the time passed is 2 times the actual | |
457 | * value(to avoid fractions). The cycles returned is for the original value of | |
458 | * the timing parameter | |
459 | */ | |
460 | static inline u32 ns_x2_2_cycles(u32 ns) | |
461 | { | |
462 | return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); | |
463 | } | |
464 | ||
465 | /* | |
466 | * Find addressing table index based on the device's type(S2 or S4) and | |
467 | * density | |
468 | */ | |
469 | s8 addressing_table_index(u8 type, u8 density, u8 width) | |
470 | { | |
471 | u8 index; | |
472 | if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) | |
473 | return -1; | |
474 | ||
475 | /* | |
476 | * Look at the way ADDR_TABLE_INDEX* values have been defined | |
477 | * in emif.h compared to LPDDR2_DENSITY_* values | |
478 | * The table is layed out in the increasing order of density | |
479 | * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed | |
480 | * at the end | |
481 | */ | |
482 | if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) | |
483 | index = ADDR_TABLE_INDEX1GS2; | |
484 | else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) | |
485 | index = ADDR_TABLE_INDEX2GS2; | |
486 | else | |
487 | index = density; | |
488 | ||
489 | debug("emif: addressing table index %d\n", index); | |
490 | ||
491 | return index; | |
492 | } | |
493 | ||
494 | /* | |
495 | * Find the the right timing table from the array of timing | |
496 | * tables of the device using DDR clock frequency | |
497 | */ | |
498 | static const struct lpddr2_ac_timings *get_timings_table(const struct | |
499 | lpddr2_ac_timings const *const *device_timings, | |
500 | u32 freq) | |
501 | { | |
502 | u32 i, temp, freq_nearest; | |
503 | const struct lpddr2_ac_timings *timings = 0; | |
504 | ||
505 | emif_assert(freq <= MAX_LPDDR2_FREQ); | |
506 | emif_assert(device_timings); | |
507 | ||
508 | /* | |
509 | * Start with the maximum allowed frequency - that is always safe | |
510 | */ | |
511 | freq_nearest = MAX_LPDDR2_FREQ; | |
512 | /* | |
513 | * Find the timings table that has the max frequency value: | |
514 | * i. Above or equal to the DDR frequency - safe | |
515 | * ii. The lowest that satisfies condition (i) - optimal | |
516 | */ | |
517 | for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { | |
518 | temp = device_timings[i]->max_freq; | |
519 | if ((temp >= freq) && (temp <= freq_nearest)) { | |
520 | freq_nearest = temp; | |
521 | timings = device_timings[i]; | |
522 | } | |
523 | } | |
524 | debug("emif: timings table: %d\n", freq_nearest); | |
525 | return timings; | |
526 | } | |
527 | ||
528 | /* | |
529 | * Finds the value of emif_sdram_config_reg | |
530 | * All parameters are programmed based on the device on CS0. | |
531 | * If there is a device on CS1, it will be same as that on CS0 or | |
532 | * it will be NVM. We don't support NVM yet. | |
533 | * If cs1_device pointer is NULL it is assumed that there is no device | |
534 | * on CS1 | |
535 | */ | |
536 | static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, | |
537 | const struct lpddr2_device_details *cs1_device, | |
538 | const struct lpddr2_addressing *addressing, | |
539 | u8 RL) | |
540 | { | |
541 | u32 config_reg = 0; | |
542 | ||
bb772a59 | 543 | config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; |
095aea29 | 544 | config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << |
bb772a59 | 545 | EMIF_REG_IBANK_POS_SHIFT; |
095aea29 | 546 | |
bb772a59 | 547 | config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; |
095aea29 | 548 | |
bb772a59 | 549 | config_reg |= RL << EMIF_REG_CL_SHIFT; |
095aea29 A |
550 | |
551 | config_reg |= addressing->row_sz[cs0_device->io_width] << | |
bb772a59 | 552 | EMIF_REG_ROWSIZE_SHIFT; |
095aea29 | 553 | |
bb772a59 | 554 | config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; |
095aea29 A |
555 | |
556 | config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << | |
bb772a59 | 557 | EMIF_REG_EBANK_SHIFT; |
095aea29 A |
558 | |
559 | config_reg |= addressing->col_sz[cs0_device->io_width] << | |
bb772a59 | 560 | EMIF_REG_PAGESIZE_SHIFT; |
095aea29 A |
561 | |
562 | return config_reg; | |
563 | } | |
564 | ||
565 | static u32 get_sdram_ref_ctrl(u32 freq, | |
566 | const struct lpddr2_addressing *addressing) | |
567 | { | |
568 | u32 ref_ctrl = 0, val = 0, freq_khz; | |
569 | freq_khz = freq / 1000; | |
570 | /* | |
571 | * refresh rate to be set is 'tREFI * freq in MHz | |
572 | * division by 10000 to account for khz and x10 in t_REFI_us_x10 | |
573 | */ | |
574 | val = addressing->t_REFI_us_x10 * freq_khz / 10000; | |
bb772a59 | 575 | ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; |
095aea29 A |
576 | |
577 | return ref_ctrl; | |
578 | } | |
579 | ||
580 | static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, | |
581 | const struct lpddr2_min_tck *min_tck, | |
582 | const struct lpddr2_addressing *addressing) | |
583 | { | |
584 | u32 tim1 = 0, val = 0; | |
585 | val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; | |
bb772a59 | 586 | tim1 |= val << EMIF_REG_T_WTR_SHIFT; |
095aea29 A |
587 | |
588 | if (addressing->num_banks == BANKS8) | |
589 | val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / | |
590 | (4 * (*T_num)) - 1; | |
591 | else | |
592 | val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; | |
593 | ||
bb772a59 | 594 | tim1 |= val << EMIF_REG_T_RRD_SHIFT; |
095aea29 A |
595 | |
596 | val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; | |
bb772a59 | 597 | tim1 |= val << EMIF_REG_T_RC_SHIFT; |
095aea29 A |
598 | |
599 | val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; | |
bb772a59 | 600 | tim1 |= val << EMIF_REG_T_RAS_SHIFT; |
095aea29 A |
601 | |
602 | val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; | |
bb772a59 | 603 | tim1 |= val << EMIF_REG_T_WR_SHIFT; |
095aea29 A |
604 | |
605 | val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; | |
bb772a59 | 606 | tim1 |= val << EMIF_REG_T_RCD_SHIFT; |
095aea29 A |
607 | |
608 | val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; | |
bb772a59 | 609 | tim1 |= val << EMIF_REG_T_RP_SHIFT; |
095aea29 A |
610 | |
611 | return tim1; | |
612 | } | |
613 | ||
614 | static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, | |
615 | const struct lpddr2_min_tck *min_tck) | |
616 | { | |
617 | u32 tim2 = 0, val = 0; | |
618 | val = max(min_tck->tCKE, timings->tCKE) - 1; | |
bb772a59 | 619 | tim2 |= val << EMIF_REG_T_CKE_SHIFT; |
095aea29 A |
620 | |
621 | val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; | |
bb772a59 | 622 | tim2 |= val << EMIF_REG_T_RTP_SHIFT; |
095aea29 A |
623 | |
624 | /* | |
625 | * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the | |
626 | * same value | |
627 | */ | |
628 | val = ns_2_cycles(timings->tXSR) - 1; | |
bb772a59 S |
629 | tim2 |= val << EMIF_REG_T_XSRD_SHIFT; |
630 | tim2 |= val << EMIF_REG_T_XSNR_SHIFT; | |
095aea29 A |
631 | |
632 | val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; | |
bb772a59 | 633 | tim2 |= val << EMIF_REG_T_XP_SHIFT; |
095aea29 A |
634 | |
635 | return tim2; | |
636 | } | |
637 | ||
638 | static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, | |
639 | const struct lpddr2_min_tck *min_tck, | |
640 | const struct lpddr2_addressing *addressing) | |
641 | { | |
642 | u32 tim3 = 0, val = 0; | |
643 | val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); | |
bb772a59 | 644 | tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; |
095aea29 A |
645 | |
646 | val = ns_2_cycles(timings->tRFCab) - 1; | |
bb772a59 | 647 | tim3 |= val << EMIF_REG_T_RFC_SHIFT; |
095aea29 A |
648 | |
649 | val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; | |
bb772a59 | 650 | tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; |
095aea29 A |
651 | |
652 | val = ns_2_cycles(timings->tZQCS) - 1; | |
bb772a59 | 653 | tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; |
095aea29 A |
654 | |
655 | val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; | |
bb772a59 | 656 | tim3 |= val << EMIF_REG_T_CKESR_SHIFT; |
095aea29 A |
657 | |
658 | return tim3; | |
659 | } | |
660 | ||
661 | static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, | |
662 | const struct lpddr2_addressing *addressing, | |
663 | u8 volt_ramp) | |
664 | { | |
665 | u32 zq = 0, val = 0; | |
666 | if (volt_ramp) | |
667 | val = | |
668 | EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / | |
669 | addressing->t_REFI_us_x10; | |
670 | else | |
671 | val = | |
672 | EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / | |
673 | addressing->t_REFI_us_x10; | |
bb772a59 | 674 | zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; |
095aea29 | 675 | |
bb772a59 | 676 | zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; |
095aea29 | 677 | |
bb772a59 | 678 | zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; |
095aea29 | 679 | |
bb772a59 | 680 | zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; |
095aea29 A |
681 | |
682 | /* | |
683 | * Assuming that two chipselects have a single calibration resistor | |
684 | * If there are indeed two calibration resistors, then this flag should | |
685 | * be enabled to take advantage of dual calibration feature. | |
686 | * This data should ideally come from board files. But considering | |
687 | * that none of the boards today have calibration resistors per CS, | |
688 | * it would be an unnecessary overhead. | |
689 | */ | |
bb772a59 | 690 | zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; |
095aea29 | 691 | |
bb772a59 | 692 | zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; |
095aea29 | 693 | |
bb772a59 | 694 | zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; |
095aea29 A |
695 | |
696 | return zq; | |
697 | } | |
698 | ||
699 | static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, | |
700 | const struct lpddr2_addressing *addressing, | |
701 | u8 is_derated) | |
702 | { | |
703 | u32 alert = 0, interval; | |
704 | interval = | |
705 | TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; | |
706 | if (is_derated) | |
707 | interval *= 4; | |
bb772a59 | 708 | alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT; |
095aea29 | 709 | |
bb772a59 | 710 | alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT; |
095aea29 | 711 | |
bb772a59 | 712 | alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT; |
095aea29 | 713 | |
bb772a59 | 714 | alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT; |
095aea29 | 715 | |
bb772a59 | 716 | alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT; |
095aea29 | 717 | |
bb772a59 | 718 | alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT; |
095aea29 A |
719 | |
720 | return alert; | |
721 | } | |
722 | ||
723 | static u32 get_read_idle_ctrl_reg(u8 volt_ramp) | |
724 | { | |
725 | u32 idle = 0, val = 0; | |
726 | if (volt_ramp) | |
924eb369 | 727 | val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; |
095aea29 A |
728 | else |
729 | /*Maximum value in normal conditions - suggested by hw team */ | |
730 | val = 0x1FF; | |
bb772a59 | 731 | idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT; |
095aea29 | 732 | |
bb772a59 | 733 | idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT; |
095aea29 A |
734 | |
735 | return idle; | |
736 | } | |
737 | ||
738 | static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) | |
739 | { | |
740 | u32 phy = 0, val = 0; | |
741 | ||
bb772a59 | 742 | phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; |
095aea29 A |
743 | |
744 | if (freq <= 100000000) | |
745 | val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; | |
746 | else if (freq <= 200000000) | |
747 | val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; | |
748 | else | |
749 | val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; | |
bb772a59 | 750 | phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT; |
095aea29 A |
751 | |
752 | /* Other fields are constant magic values. Hardcode them together */ | |
753 | phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << | |
bb772a59 | 754 | EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; |
095aea29 A |
755 | |
756 | return phy; | |
757 | } | |
758 | ||
d3d82e9f | 759 | static u32 get_emif_mem_size(u32 base) |
095aea29 A |
760 | { |
761 | u32 size_mbytes = 0, temp; | |
d3d82e9f LV |
762 | struct emif_device_details dev_details; |
763 | struct lpddr2_device_details cs0_dev_details, cs1_dev_details; | |
764 | u32 emif_nr = emif_num(base); | |
095aea29 | 765 | |
d3d82e9f LV |
766 | emif_reset_phy(base); |
767 | dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, | |
768 | &cs0_dev_details); | |
769 | dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, | |
770 | &cs1_dev_details); | |
771 | emif_reset_phy(base); | |
095aea29 | 772 | |
d3d82e9f LV |
773 | if (dev_details.cs0_device_details) { |
774 | temp = dev_details.cs0_device_details->density; | |
095aea29 A |
775 | size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; |
776 | } | |
777 | ||
d3d82e9f LV |
778 | if (dev_details.cs1_device_details) { |
779 | temp = dev_details.cs1_device_details->density; | |
095aea29 A |
780 | size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; |
781 | } | |
782 | /* convert to bytes */ | |
783 | return size_mbytes << 20; | |
784 | } | |
785 | ||
786 | /* Gets the encoding corresponding to a given DMM section size */ | |
787 | u32 get_dmm_section_size_map(u32 section_size) | |
788 | { | |
789 | /* | |
790 | * Section size mapping: | |
791 | * 0x0: 16-MiB section | |
792 | * 0x1: 32-MiB section | |
793 | * 0x2: 64-MiB section | |
794 | * 0x3: 128-MiB section | |
795 | * 0x4: 256-MiB section | |
796 | * 0x5: 512-MiB section | |
797 | * 0x6: 1-GiB section | |
798 | * 0x7: 2-GiB section | |
799 | */ | |
800 | section_size >>= 24; /* divide by 16 MB */ | |
801 | return log_2_n_round_down(section_size); | |
802 | } | |
803 | ||
804 | static void emif_calculate_regs( | |
805 | const struct emif_device_details *emif_dev_details, | |
806 | u32 freq, struct emif_regs *regs) | |
807 | { | |
808 | u32 temp, sys_freq; | |
809 | const struct lpddr2_addressing *addressing; | |
810 | const struct lpddr2_ac_timings *timings; | |
811 | const struct lpddr2_min_tck *min_tck; | |
812 | const struct lpddr2_device_details *cs0_dev_details = | |
813 | emif_dev_details->cs0_device_details; | |
814 | const struct lpddr2_device_details *cs1_dev_details = | |
815 | emif_dev_details->cs1_device_details; | |
816 | const struct lpddr2_device_timings *cs0_dev_timings = | |
817 | emif_dev_details->cs0_device_timings; | |
818 | ||
819 | emif_assert(emif_dev_details); | |
820 | emif_assert(regs); | |
821 | /* | |
822 | * You can not have a device on CS1 without one on CS0 | |
823 | * So configuring EMIF without a device on CS0 doesn't | |
824 | * make sense | |
825 | */ | |
826 | emif_assert(cs0_dev_details); | |
827 | emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); | |
828 | /* | |
829 | * If there is a device on CS1 it should be same type as CS0 | |
830 | * (or NVM. But NVM is not supported in this driver yet) | |
831 | */ | |
832 | emif_assert((cs1_dev_details == NULL) || | |
833 | (cs1_dev_details->type == LPDDR2_TYPE_NVM) || | |
834 | (cs0_dev_details->type == cs1_dev_details->type)); | |
835 | emif_assert(freq <= MAX_LPDDR2_FREQ); | |
836 | ||
837 | set_ddr_clk_period(freq); | |
838 | ||
839 | /* | |
840 | * The device on CS0 is used for all timing calculations | |
841 | * There is only one set of registers for timings per EMIF. So, if the | |
842 | * second CS(CS1) has a device, it should have the same timings as the | |
843 | * device on CS0 | |
844 | */ | |
845 | timings = get_timings_table(cs0_dev_timings->ac_timings, freq); | |
846 | emif_assert(timings); | |
847 | min_tck = cs0_dev_timings->min_tck; | |
848 | ||
849 | temp = addressing_table_index(cs0_dev_details->type, | |
850 | cs0_dev_details->density, | |
851 | cs0_dev_details->io_width); | |
852 | ||
853 | emif_assert((temp >= 0)); | |
854 | addressing = &(addressing_table[temp]); | |
855 | emif_assert(addressing); | |
856 | ||
857 | sys_freq = get_sys_clk_freq(); | |
858 | ||
859 | regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, | |
860 | cs1_dev_details, | |
861 | addressing, RL_BOOT); | |
862 | ||
863 | regs->sdram_config = get_sdram_config_reg(cs0_dev_details, | |
864 | cs1_dev_details, | |
865 | addressing, RL_FINAL); | |
866 | ||
867 | regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); | |
868 | ||
869 | regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); | |
870 | ||
871 | regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); | |
872 | ||
873 | regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); | |
874 | ||
875 | regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); | |
876 | ||
877 | regs->temp_alert_config = | |
878 | get_temp_alert_config(cs1_dev_details, addressing, 0); | |
879 | ||
880 | regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, | |
881 | LPDDR2_VOLTAGE_STABLE); | |
882 | ||
883 | regs->emif_ddr_phy_ctlr_1_init = | |
884 | get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); | |
885 | ||
886 | regs->emif_ddr_phy_ctlr_1 = | |
887 | get_ddr_phy_ctrl_1(freq, RL_FINAL); | |
888 | ||
889 | regs->freq = freq; | |
890 | ||
891 | print_timing_reg(regs->sdram_config_init); | |
892 | print_timing_reg(regs->sdram_config); | |
893 | print_timing_reg(regs->ref_ctrl); | |
894 | print_timing_reg(regs->sdram_tim1); | |
895 | print_timing_reg(regs->sdram_tim2); | |
896 | print_timing_reg(regs->sdram_tim3); | |
897 | print_timing_reg(regs->read_idle_ctrl); | |
898 | print_timing_reg(regs->temp_alert_config); | |
899 | print_timing_reg(regs->zq_config); | |
900 | print_timing_reg(regs->emif_ddr_phy_ctlr_1); | |
901 | print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); | |
902 | } | |
903 | #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ | |
904 | ||
1e463866 A |
905 | #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION |
906 | const char *get_lpddr2_type(u8 type_id) | |
907 | { | |
908 | switch (type_id) { | |
909 | case LPDDR2_TYPE_S4: | |
910 | return "LPDDR2-S4"; | |
911 | case LPDDR2_TYPE_S2: | |
912 | return "LPDDR2-S2"; | |
913 | default: | |
914 | return NULL; | |
915 | } | |
916 | } | |
917 | ||
918 | const char *get_lpddr2_io_width(u8 width_id) | |
919 | { | |
920 | switch (width_id) { | |
921 | case LPDDR2_IO_WIDTH_8: | |
922 | return "x8"; | |
923 | case LPDDR2_IO_WIDTH_16: | |
924 | return "x16"; | |
925 | case LPDDR2_IO_WIDTH_32: | |
926 | return "x32"; | |
927 | default: | |
928 | return NULL; | |
929 | } | |
930 | } | |
931 | ||
932 | const char *get_lpddr2_manufacturer(u32 manufacturer) | |
933 | { | |
934 | switch (manufacturer) { | |
935 | case LPDDR2_MANUFACTURER_SAMSUNG: | |
936 | return "Samsung"; | |
937 | case LPDDR2_MANUFACTURER_QIMONDA: | |
938 | return "Qimonda"; | |
939 | case LPDDR2_MANUFACTURER_ELPIDA: | |
940 | return "Elpida"; | |
941 | case LPDDR2_MANUFACTURER_ETRON: | |
942 | return "Etron"; | |
943 | case LPDDR2_MANUFACTURER_NANYA: | |
944 | return "Nanya"; | |
945 | case LPDDR2_MANUFACTURER_HYNIX: | |
946 | return "Hynix"; | |
947 | case LPDDR2_MANUFACTURER_MOSEL: | |
948 | return "Mosel"; | |
949 | case LPDDR2_MANUFACTURER_WINBOND: | |
950 | return "Winbond"; | |
951 | case LPDDR2_MANUFACTURER_ESMT: | |
952 | return "ESMT"; | |
953 | case LPDDR2_MANUFACTURER_SPANSION: | |
954 | return "Spansion"; | |
955 | case LPDDR2_MANUFACTURER_SST: | |
956 | return "SST"; | |
957 | case LPDDR2_MANUFACTURER_ZMOS: | |
958 | return "ZMOS"; | |
959 | case LPDDR2_MANUFACTURER_INTEL: | |
960 | return "Intel"; | |
961 | case LPDDR2_MANUFACTURER_NUMONYX: | |
962 | return "Numonyx"; | |
963 | case LPDDR2_MANUFACTURER_MICRON: | |
964 | return "Micron"; | |
965 | default: | |
966 | return NULL; | |
967 | } | |
968 | } | |
969 | ||
970 | static void display_sdram_details(u32 emif_nr, u32 cs, | |
971 | struct lpddr2_device_details *device) | |
972 | { | |
973 | const char *mfg_str; | |
974 | const char *type_str; | |
975 | char density_str[10]; | |
976 | u32 density; | |
977 | ||
978 | debug("EMIF%d CS%d\t", emif_nr, cs); | |
979 | ||
980 | if (!device) { | |
981 | debug("None\n"); | |
982 | return; | |
983 | } | |
984 | ||
985 | mfg_str = get_lpddr2_manufacturer(device->manufacturer); | |
986 | type_str = get_lpddr2_type(device->type); | |
987 | ||
988 | density = lpddr2_density_2_size_in_mbytes[device->density]; | |
989 | if ((density / 1024 * 1024) == density) { | |
990 | density /= 1024; | |
991 | sprintf(density_str, "%d GB", density); | |
992 | } else | |
993 | sprintf(density_str, "%d MB", density); | |
994 | if (mfg_str && type_str) | |
995 | debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); | |
996 | } | |
997 | ||
998 | static u8 is_lpddr2_sdram_present(u32 base, u32 cs, | |
999 | struct lpddr2_device_details *lpddr2_device) | |
1000 | { | |
1001 | u32 mr = 0, temp; | |
1002 | ||
1003 | mr = get_mr(base, cs, LPDDR2_MR0); | |
1004 | if (mr > 0xFF) { | |
1005 | /* Mode register value bigger than 8 bit */ | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; | |
1010 | if (temp) { | |
1011 | /* Not SDRAM */ | |
1012 | return 0; | |
1013 | } | |
1014 | temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; | |
1015 | ||
1016 | if (temp) { | |
1017 | /* DNV supported - But DNV is only supported for NVM */ | |
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | mr = get_mr(base, cs, LPDDR2_MR4); | |
1022 | if (mr > 0xFF) { | |
1023 | /* Mode register value bigger than 8 bit */ | |
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | mr = get_mr(base, cs, LPDDR2_MR5); | |
ad0878a7 | 1028 | if (mr > 0xFF) { |
1e463866 A |
1029 | /* Mode register value bigger than 8 bit */ |
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | if (!get_lpddr2_manufacturer(mr)) { | |
1034 | /* Manufacturer not identified */ | |
1035 | return 0; | |
1036 | } | |
1037 | lpddr2_device->manufacturer = mr; | |
1038 | ||
1039 | mr = get_mr(base, cs, LPDDR2_MR6); | |
1040 | if (mr >= 0xFF) { | |
1041 | /* Mode register value bigger than 8 bit */ | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | mr = get_mr(base, cs, LPDDR2_MR7); | |
1046 | if (mr >= 0xFF) { | |
1047 | /* Mode register value bigger than 8 bit */ | |
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | mr = get_mr(base, cs, LPDDR2_MR8); | |
1052 | if (mr >= 0xFF) { | |
1053 | /* Mode register value bigger than 8 bit */ | |
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; | |
1058 | if (!get_lpddr2_type(temp)) { | |
1059 | /* Not SDRAM */ | |
1060 | return 0; | |
1061 | } | |
1062 | lpddr2_device->type = temp; | |
1063 | ||
1064 | temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; | |
1065 | if (temp > LPDDR2_DENSITY_32Gb) { | |
1066 | /* Density not supported */ | |
1067 | return 0; | |
1068 | } | |
1069 | lpddr2_device->density = temp; | |
1070 | ||
1071 | temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; | |
1072 | if (!get_lpddr2_io_width(temp)) { | |
1073 | /* IO width unsupported value */ | |
1074 | return 0; | |
1075 | } | |
1076 | lpddr2_device->io_width = temp; | |
1077 | ||
1078 | /* | |
1079 | * If all the above tests pass we should | |
1080 | * have a device on this chip-select | |
1081 | */ | |
1082 | return 1; | |
1083 | } | |
1084 | ||
025bc425 | 1085 | struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, |
1e463866 A |
1086 | struct lpddr2_device_details *lpddr2_dev_details) |
1087 | { | |
1088 | u32 phy; | |
bb772a59 S |
1089 | u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; |
1090 | ||
1e463866 A |
1091 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
1092 | ||
1093 | if (!lpddr2_dev_details) | |
1094 | return NULL; | |
1095 | ||
1096 | /* Do the minimum init for mode register accesses */ | |
784229cc | 1097 | if (!(running_from_sdram() || warm_reset())) { |
1e463866 A |
1098 | phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); |
1099 | writel(phy, &emif->emif_ddr_phy_ctrl_1); | |
1100 | } | |
1101 | ||
1102 | if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) | |
1103 | return NULL; | |
1104 | ||
1105 | display_sdram_details(emif_num(base), cs, lpddr2_dev_details); | |
1106 | ||
1107 | return lpddr2_dev_details; | |
1108 | } | |
1e463866 A |
1109 | #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ |
1110 | ||
2ae610f0 A |
1111 | static void do_sdram_init(u32 base) |
1112 | { | |
1113 | const struct emif_regs *regs; | |
1114 | u32 in_sdram, emif_nr; | |
1115 | ||
1116 | debug(">>do_sdram_init() %x\n", base); | |
1117 | ||
1118 | in_sdram = running_from_sdram(); | |
bb772a59 | 1119 | emif_nr = (base == EMIF1_BASE) ? 1 : 2; |
2ae610f0 | 1120 | |
095aea29 | 1121 | #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
2ae610f0 A |
1122 | emif_get_reg_dump(emif_nr, ®s); |
1123 | if (!regs) { | |
1124 | debug("EMIF: reg dump not provided\n"); | |
1125 | return; | |
1126 | } | |
095aea29 A |
1127 | #else |
1128 | /* | |
1129 | * The user has not provided the register values. We need to | |
1130 | * calculate it based on the timings and the DDR frequency | |
1131 | */ | |
1132 | struct emif_device_details dev_details; | |
1133 | struct emif_regs calculated_regs; | |
1134 | ||
1135 | /* | |
1136 | * Get device details: | |
1137 | * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set | |
1138 | * - Obtained from user otherwise | |
1139 | */ | |
1140 | struct lpddr2_device_details cs0_dev_details, cs1_dev_details; | |
025bc425 | 1141 | emif_reset_phy(base); |
4324c118 | 1142 | dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, |
025bc425 | 1143 | &cs0_dev_details); |
4324c118 | 1144 | dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, |
025bc425 A |
1145 | &cs1_dev_details); |
1146 | emif_reset_phy(base); | |
095aea29 A |
1147 | |
1148 | /* Return if no devices on this EMIF */ | |
1149 | if (!dev_details.cs0_device_details && | |
1150 | !dev_details.cs1_device_details) { | |
095aea29 A |
1151 | return; |
1152 | } | |
1153 | ||
095aea29 A |
1154 | /* |
1155 | * Get device timings: | |
1156 | * - Default timings specified by JESD209-2 if | |
1157 | * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set | |
1158 | * - Obtained from user otherwise | |
1159 | */ | |
1160 | emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, | |
1161 | &dev_details.cs1_device_timings); | |
1162 | ||
1163 | /* Calculate the register values */ | |
2e5ba489 | 1164 | emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs); |
095aea29 A |
1165 | regs = &calculated_regs; |
1166 | #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ | |
2ae610f0 A |
1167 | |
1168 | /* | |
1169 | * Initializing the LPDDR2 device can not happen from SDRAM. | |
1170 | * Changing the timing registers in EMIF can happen(going from one | |
1171 | * OPP to another) | |
1172 | */ | |
784229cc | 1173 | if (!(in_sdram || warm_reset())) { |
7c352cd3 TR |
1174 | if (emif_sdram_type(regs->sdram_config) == |
1175 | EMIF_SDRAM_TYPE_LPDDR2) | |
784ab7c5 LV |
1176 | lpddr2_init(base, regs); |
1177 | else | |
1178 | ddr3_init(base, regs); | |
1179 | } | |
7c352cd3 TR |
1180 | if (warm_reset() && (emif_sdram_type(regs->sdram_config) == |
1181 | EMIF_SDRAM_TYPE_DDR3)) { | |
166e5cc6 LV |
1182 | set_lpmode_selfrefresh(base); |
1183 | emif_reset_phy(base); | |
6213db78 | 1184 | omap5_ddr3_leveling(base, regs); |
166e5cc6 | 1185 | } |
2ae610f0 A |
1186 | |
1187 | /* Write to the shadow registers */ | |
1188 | emif_update_timings(base, regs); | |
1189 | ||
1190 | debug("<<do_sdram_init() %x\n", base); | |
1191 | } | |
1192 | ||
bb772a59 | 1193 | void emif_post_init_config(u32 base) |
2ae610f0 A |
1194 | { |
1195 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
bb772a59 S |
1196 | u32 omap_rev = omap_revision(); |
1197 | ||
2ae610f0 | 1198 | /* reset phy on ES2.0 */ |
bb772a59 | 1199 | if (omap_rev == OMAP4430_ES2_0) |
2ae610f0 A |
1200 | emif_reset_phy(base); |
1201 | ||
1202 | /* Put EMIF back in smart idle on ES1.0 */ | |
bb772a59 | 1203 | if (omap_rev == OMAP4430_ES1_0) |
2ae610f0 A |
1204 | writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); |
1205 | } | |
1206 | ||
bb772a59 | 1207 | void dmm_init(u32 base) |
2ae610f0 A |
1208 | { |
1209 | const struct dmm_lisa_map_regs *lisa_map_regs; | |
86021143 | 1210 | u32 i, section, valid; |
2ae610f0 | 1211 | |
095aea29 | 1212 | #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
2ae610f0 | 1213 | emif_get_dmm_regs(&lisa_map_regs); |
095aea29 A |
1214 | #else |
1215 | u32 emif1_size, emif2_size, mapped_size, section_map = 0; | |
1216 | u32 section_cnt, sys_addr; | |
1217 | struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; | |
1218 | ||
1219 | mapped_size = 0; | |
1220 | section_cnt = 3; | |
1221 | sys_addr = CONFIG_SYS_SDRAM_BASE; | |
d3d82e9f LV |
1222 | emif1_size = get_emif_mem_size(EMIF1_BASE); |
1223 | emif2_size = get_emif_mem_size(EMIF2_BASE); | |
095aea29 A |
1224 | debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); |
1225 | ||
1226 | if (!emif1_size && !emif2_size) | |
1227 | return; | |
1228 | ||
1229 | /* symmetric interleaved section */ | |
1230 | if (emif1_size && emif2_size) { | |
1231 | mapped_size = min(emif1_size, emif2_size); | |
1232 | section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; | |
bb772a59 | 1233 | section_map |= 0 << EMIF_SDRC_ADDR_SHIFT; |
095aea29 A |
1234 | /* only MSB */ |
1235 | section_map |= (sys_addr >> 24) << | |
bb772a59 | 1236 | EMIF_SYS_ADDR_SHIFT; |
095aea29 | 1237 | section_map |= get_dmm_section_size_map(mapped_size * 2) |
bb772a59 | 1238 | << EMIF_SYS_SIZE_SHIFT; |
095aea29 A |
1239 | lis_map_regs_calculated.dmm_lisa_map_3 = section_map; |
1240 | emif1_size -= mapped_size; | |
1241 | emif2_size -= mapped_size; | |
1242 | sys_addr += (mapped_size * 2); | |
1243 | section_cnt--; | |
1244 | } | |
1245 | ||
1246 | /* | |
1247 | * Single EMIF section(we can have a maximum of 1 single EMIF | |
1248 | * section- either EMIF1 or EMIF2 or none, but not both) | |
1249 | */ | |
1250 | if (emif1_size) { | |
1251 | section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; | |
1252 | section_map |= get_dmm_section_size_map(emif1_size) | |
bb772a59 | 1253 | << EMIF_SYS_SIZE_SHIFT; |
095aea29 A |
1254 | /* only MSB */ |
1255 | section_map |= (mapped_size >> 24) << | |
bb772a59 | 1256 | EMIF_SDRC_ADDR_SHIFT; |
095aea29 | 1257 | /* only MSB */ |
bb772a59 | 1258 | section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT; |
095aea29 A |
1259 | section_cnt--; |
1260 | } | |
1261 | if (emif2_size) { | |
1262 | section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; | |
1263 | section_map |= get_dmm_section_size_map(emif2_size) << | |
bb772a59 | 1264 | EMIF_SYS_SIZE_SHIFT; |
095aea29 | 1265 | /* only MSB */ |
bb772a59 | 1266 | section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT; |
095aea29 | 1267 | /* only MSB */ |
bb772a59 | 1268 | section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT; |
095aea29 A |
1269 | section_cnt--; |
1270 | } | |
1271 | ||
1272 | if (section_cnt == 2) { | |
1273 | /* Only 1 section - either symmetric or single EMIF */ | |
1274 | lis_map_regs_calculated.dmm_lisa_map_3 = section_map; | |
1275 | lis_map_regs_calculated.dmm_lisa_map_2 = 0; | |
1276 | lis_map_regs_calculated.dmm_lisa_map_1 = 0; | |
1277 | } else { | |
1278 | /* 2 sections - 1 symmetric, 1 single EMIF */ | |
1279 | lis_map_regs_calculated.dmm_lisa_map_2 = section_map; | |
1280 | lis_map_regs_calculated.dmm_lisa_map_1 = 0; | |
1281 | } | |
1282 | ||
1283 | /* TRAP for invalid TILER mappings in section 0 */ | |
1284 | lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; | |
2ae610f0 | 1285 | |
e3f53104 LV |
1286 | if (omap_revision() >= OMAP4460_ES1_0) |
1287 | lis_map_regs_calculated.is_ma_present = 1; | |
1288 | ||
095aea29 A |
1289 | lisa_map_regs = &lis_map_regs_calculated; |
1290 | #endif | |
2ae610f0 A |
1291 | struct dmm_lisa_map_regs *hw_lisa_map_regs = |
1292 | (struct dmm_lisa_map_regs *)base; | |
1293 | ||
1294 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); | |
1295 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); | |
1296 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); | |
1297 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); | |
1298 | ||
1299 | writel(lisa_map_regs->dmm_lisa_map_3, | |
1300 | &hw_lisa_map_regs->dmm_lisa_map_3); | |
1301 | writel(lisa_map_regs->dmm_lisa_map_2, | |
1302 | &hw_lisa_map_regs->dmm_lisa_map_2); | |
1303 | writel(lisa_map_regs->dmm_lisa_map_1, | |
1304 | &hw_lisa_map_regs->dmm_lisa_map_1); | |
1305 | writel(lisa_map_regs->dmm_lisa_map_0, | |
1306 | &hw_lisa_map_regs->dmm_lisa_map_0); | |
924eb369 | 1307 | |
7831419d | 1308 | if (lisa_map_regs->is_ma_present) { |
924eb369 | 1309 | hw_lisa_map_regs = |
bb772a59 | 1310 | (struct dmm_lisa_map_regs *)MA_BASE; |
924eb369 A |
1311 | |
1312 | writel(lisa_map_regs->dmm_lisa_map_3, | |
1313 | &hw_lisa_map_regs->dmm_lisa_map_3); | |
1314 | writel(lisa_map_regs->dmm_lisa_map_2, | |
1315 | &hw_lisa_map_regs->dmm_lisa_map_2); | |
1316 | writel(lisa_map_regs->dmm_lisa_map_1, | |
1317 | &hw_lisa_map_regs->dmm_lisa_map_1); | |
1318 | writel(lisa_map_regs->dmm_lisa_map_0, | |
1319 | &hw_lisa_map_regs->dmm_lisa_map_0); | |
1320 | } | |
86021143 LV |
1321 | |
1322 | /* | |
1323 | * EMIF should be configured only when | |
1324 | * memory is mapped on it. Using emif1_enabled | |
1325 | * and emif2_enabled variables for this. | |
1326 | */ | |
1327 | emif1_enabled = 0; | |
1328 | emif2_enabled = 0; | |
1329 | for (i = 0; i < 4; i++) { | |
1330 | section = __raw_readl(DMM_BASE + i*4); | |
1331 | valid = (section & EMIF_SDRC_MAP_MASK) >> | |
1332 | (EMIF_SDRC_MAP_SHIFT); | |
1333 | if (valid == 3) { | |
1334 | emif1_enabled = 1; | |
1335 | emif2_enabled = 1; | |
1336 | break; | |
dbf02eca FB |
1337 | } |
1338 | ||
1339 | if (valid == 1) | |
86021143 | 1340 | emif1_enabled = 1; |
dbf02eca FB |
1341 | |
1342 | if (valid == 2) | |
86021143 | 1343 | emif2_enabled = 1; |
86021143 | 1344 | } |
2ae610f0 A |
1345 | } |
1346 | ||
54d022e7 S |
1347 | static void do_bug0039_workaround(u32 base) |
1348 | { | |
1349 | u32 val, i, clkctrl; | |
1350 | struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; | |
1351 | const struct read_write_regs *bug_00339_regs; | |
1352 | u32 iterations; | |
1353 | u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; | |
1354 | u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; | |
1355 | ||
1356 | if (is_dra7xx()) | |
1357 | phy_status_base++; | |
1358 | ||
1359 | bug_00339_regs = get_bug_regs(&iterations); | |
1360 | ||
1361 | /* Put EMIF in to idle */ | |
1362 | clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); | |
1363 | __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); | |
1364 | ||
1365 | /* Copy the phy status registers in to phy ctrl shadow registers */ | |
1366 | for (i = 0; i < iterations; i++) { | |
1367 | val = __raw_readl(phy_status_base + | |
1368 | bug_00339_regs[i].read_reg - 1); | |
1369 | ||
1370 | __raw_writel(val, phy_ctrl_base + | |
1371 | ((bug_00339_regs[i].write_reg - 1) << 1)); | |
1372 | ||
1373 | __raw_writel(val, phy_ctrl_base + | |
1374 | (bug_00339_regs[i].write_reg << 1) - 1); | |
1375 | } | |
1376 | ||
1377 | /* Disable leveling */ | |
1378 | writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); | |
1379 | ||
1380 | __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); | |
1381 | } | |
1382 | ||
2ae610f0 A |
1383 | /* |
1384 | * SDRAM initialization: | |
1385 | * SDRAM initialization has two parts: | |
1386 | * 1. Configuring the SDRAM device | |
1387 | * 2. Update the AC timings related parameters in the EMIF module | |
1388 | * (1) should be done only once and should not be done while we are | |
1389 | * running from SDRAM. | |
1390 | * (2) can and should be done more than once if OPP changes. | |
1391 | * Particularly, this may be needed when we boot without SPL and | |
1392 | * and using Configuration Header(CH). ROM code supports only at 50% OPP | |
1393 | * at boot (low power boot). So u-boot has to switch to OPP100 and update | |
1394 | * the frequency. So, | |
1395 | * Doing (1) and (2) makes sense - first time initialization | |
1396 | * Doing (2) and not (1) makes sense - OPP change (when using CH) | |
1397 | * Doing (1) and not (2) doen't make sense | |
1398 | * See do_sdram_init() for the details | |
1399 | */ | |
1400 | void sdram_init(void) | |
1401 | { | |
1402 | u32 in_sdram, size_prog, size_detect; | |
7c352cd3 TR |
1403 | struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; |
1404 | u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); | |
2ae610f0 A |
1405 | |
1406 | debug(">>sdram_init()\n"); | |
1407 | ||
508a58fa | 1408 | if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) |
2ae610f0 A |
1409 | return; |
1410 | ||
1411 | in_sdram = running_from_sdram(); | |
1412 | debug("in_sdram = %d\n", in_sdram); | |
1413 | ||
166e5cc6 LV |
1414 | if (!in_sdram) { |
1415 | if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) | |
01b753ff | 1416 | bypass_dpll((*prcm)->cm_clkmode_dpll_core); |
166e5cc6 | 1417 | else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) |
01b753ff | 1418 | writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); |
753bae8c | 1419 | } |
2ae610f0 | 1420 | |
784229cc | 1421 | if (!in_sdram) |
bb772a59 | 1422 | dmm_init(DMM_BASE); |
784229cc | 1423 | |
86021143 LV |
1424 | if (emif1_enabled) |
1425 | do_sdram_init(EMIF1_BASE); | |
1426 | ||
1427 | if (emif2_enabled) | |
1428 | do_sdram_init(EMIF2_BASE); | |
1429 | ||
784229cc | 1430 | if (!(in_sdram || warm_reset())) { |
86021143 LV |
1431 | if (emif1_enabled) |
1432 | emif_post_init_config(EMIF1_BASE); | |
1433 | if (emif2_enabled) | |
1434 | emif_post_init_config(EMIF2_BASE); | |
2ae610f0 A |
1435 | } |
1436 | ||
1437 | /* for the shadow registers to take effect */ | |
9ca8bfea | 1438 | if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) |
753bae8c | 1439 | freq_update_core(); |
2ae610f0 A |
1440 | |
1441 | /* Do some testing after the init */ | |
1442 | if (!in_sdram) { | |
508a58fa | 1443 | size_prog = omap_sdram_size(); |
41321fd4 S |
1444 | size_prog = log_2_n_round_down(size_prog); |
1445 | size_prog = (1 << size_prog); | |
1446 | ||
2ae610f0 A |
1447 | size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, |
1448 | size_prog); | |
1449 | /* Compare with the size programmed */ | |
1450 | if (size_detect != size_prog) { | |
1451 | printf("SDRAM: identified size not same as expected" | |
1452 | " size identified: %x expected: %x\n", | |
1453 | size_detect, | |
1454 | size_prog); | |
1455 | } else | |
1456 | debug("get_ram_size() successful"); | |
1457 | } | |
1458 | ||
54d022e7 | 1459 | if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && |
f2a1b93b | 1460 | (!in_sdram && !warm_reset()) && (!is_dra7xx())) { |
9fcf3d3a LV |
1461 | if (emif1_enabled) |
1462 | do_bug0039_workaround(EMIF1_BASE); | |
1463 | if (emif2_enabled) | |
1464 | do_bug0039_workaround(EMIF2_BASE); | |
54d022e7 S |
1465 | } |
1466 | ||
2ae610f0 A |
1467 | debug("<<sdram_init()\n"); |
1468 | } |