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5ed3e865 DB |
1 | /* |
2 | * Board specific setup info | |
3 | * | |
4 | * (C) Copyright 2008 | |
5 | * Texas Instruments, <www.ti.com> | |
6 | * | |
7 | * Initial Code by: | |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Syed Mohammed Khasim <khasim@ti.com> | |
10 | * | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
5ed3e865 DB |
12 | */ |
13 | ||
14 | #include <config.h> | |
15 | #include <version.h> | |
16 | #include <asm/arch/mem.h> | |
17 | #include <asm/arch/clocks_omap3.h> | |
74236aca | 18 | #include <linux/linkage.h> |
5ed3e865 DB |
19 | |
20 | _TEXT_BASE: | |
14d0a02a | 21 | .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ |
5ed3e865 | 22 | |
20470511 | 23 | #ifdef CONFIG_SPL_BUILD |
74236aca | 24 | ENTRY(save_boot_params) |
409ef1bc SS |
25 | ldr r4, =omap3_boot_device |
26 | ldr r5, [r0, #0x4] | |
27 | and r5, r5, #0xff | |
28 | str r5, [r4] | |
409ef1bc | 29 | bx lr |
74236aca | 30 | ENDPROC(save_boot_params) |
20470511 | 31 | #endif |
78ce9779 | 32 | |
74236aca | 33 | ENTRY(omap3_gp_romcode_call) |
45bf0585 A |
34 | PUSH {r4-r12, lr} @ Save all registers from ROM code! |
35 | MOV r12, r0 @ Copy the Service ID in R12 | |
36 | MOV r0, r1 @ Copy parameter to R0 | |
37 | mcr p15, 0, r0, c7, c10, 4 @ DSB | |
38 | mcr p15, 0, r0, c7, c10, 5 @ DMB | |
39 | .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled | |
40 | @ because we use -march=armv5 | |
41 | POP {r4-r12, pc} | |
74236aca | 42 | ENDPROC(omap3_gp_romcode_call) |
45bf0585 A |
43 | |
44 | /* | |
45 | * Funtion for making PPA HAL API calls in secure devices | |
46 | * Input: | |
47 | * R0 - Service ID | |
48 | * R1 - paramer list | |
49 | */ | |
74236aca | 50 | ENTRY(do_omap3_emu_romcode_call) |
45bf0585 A |
51 | PUSH {r4-r12, lr} @ Save all registers from ROM code! |
52 | MOV r12, r0 @ Copy the Secure Service ID in R12 | |
53 | MOV r3, r1 @ Copy the pointer to va_list in R3 | |
54 | MOV r1, #0 @ Process ID - 0 | |
55 | MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer | |
56 | @ to va_list in R3 | |
57 | MOV r6, #0xFF @ Indicate new Task call | |
58 | mcr p15, 0, r0, c7, c10, 4 @ DSB | |
59 | mcr p15, 0, r0, c7, c10, 5 @ DMB | |
60 | .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled | |
61 | @ because we use -march=armv5 | |
62 | POP {r4-r12, pc} | |
74236aca | 63 | ENDPROC(do_omap3_emu_romcode_call) |
45bf0585 | 64 | |
5ed3e865 DB |
65 | #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) |
66 | /************************************************************************** | |
67 | * cpy_clk_code: relocates clock code into SRAM where its safer to execute | |
68 | * R1 = SRAM destination address. | |
69 | *************************************************************************/ | |
74236aca | 70 | ENTRY(cpy_clk_code) |
5ed3e865 | 71 | /* Copy DPLL code into SRAM */ |
8d208366 AA |
72 | adr r0, go_to_speed /* copy from start of go_to_speed... */ |
73 | adr r2, lowlevel_init /* ... up to start of low_level_init */ | |
5ed3e865 DB |
74 | next2: |
75 | ldmia r0!, {r3 - r10} /* copy from source address [r0] */ | |
76 | stmia r1!, {r3 - r10} /* copy to target address [r1] */ | |
77 | cmp r0, r2 /* until source end address [r2] */ | |
8d208366 | 78 | blo next2 |
5ed3e865 | 79 | mov pc, lr /* back to caller */ |
74236aca | 80 | ENDPROC(cpy_clk_code) |
5ed3e865 DB |
81 | |
82 | /* *************************************************************************** | |
83 | * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed | |
84 | * -executed from SRAM. | |
85 | * R0 = CM_CLKEN_PLL-bypass value | |
86 | * R1 = CM_CLKSEL1_PLL-m, n, and divider values | |
87 | * R2 = CM_CLKSEL_CORE-divider values | |
88 | * R3 = CM_IDLEST_CKGEN - addr dpll lock wait | |
89 | * | |
90 | * Note: If core unlocks/relocks and SDRAM is running fast already it gets | |
91 | * confused. A reset of the controller gets it back. Taking away its | |
92 | * L3 when its not in self refresh seems bad for it. Normally, this | |
93 | * code runs from flash before SDR is init so that should be ok. | |
94 | ****************************************************************************/ | |
74236aca | 95 | ENTRY(go_to_speed) |
5ed3e865 DB |
96 | stmfd sp!, {r4 - r6} |
97 | ||
98 | /* move into fast relock bypass */ | |
99 | ldr r4, pll_ctl_add | |
100 | str r0, [r4] | |
101 | wait1: | |
102 | ldr r5, [r3] /* get status */ | |
103 | and r5, r5, #0x1 /* isolate core status */ | |
104 | cmp r5, #0x1 /* still locked? */ | |
105 | beq wait1 /* if lock, loop */ | |
106 | ||
107 | /* set new dpll dividers _after_ in bypass */ | |
108 | ldr r5, pll_div_add1 | |
109 | str r1, [r5] /* set m, n, m2 */ | |
110 | ldr r5, pll_div_add2 | |
111 | str r2, [r5] /* set l3/l4/.. dividers*/ | |
112 | ldr r5, pll_div_add3 /* wkup */ | |
113 | ldr r2, pll_div_val3 /* rsm val */ | |
114 | str r2, [r5] | |
115 | ldr r5, pll_div_add4 /* gfx */ | |
116 | ldr r2, pll_div_val4 | |
117 | str r2, [r5] | |
118 | ldr r5, pll_div_add5 /* emu */ | |
119 | ldr r2, pll_div_val5 | |
120 | str r2, [r5] | |
121 | ||
122 | /* now prepare GPMC (flash) for new dpll speed */ | |
123 | /* flash needs to be stable when we jump back to it */ | |
124 | ldr r5, flash_cfg3_addr | |
125 | ldr r2, flash_cfg3_val | |
126 | str r2, [r5] | |
127 | ldr r5, flash_cfg4_addr | |
128 | ldr r2, flash_cfg4_val | |
129 | str r2, [r5] | |
130 | ldr r5, flash_cfg5_addr | |
131 | ldr r2, flash_cfg5_val | |
132 | str r2, [r5] | |
133 | ldr r5, flash_cfg1_addr | |
134 | ldr r2, [r5] | |
135 | orr r2, r2, #0x3 /* up gpmc divider */ | |
136 | str r2, [r5] | |
137 | ||
138 | /* lock DPLL3 and wait a bit */ | |
139 | orr r0, r0, #0x7 /* set up for lock mode */ | |
140 | str r0, [r4] /* lock */ | |
141 | nop /* ARM slow at this point working at sys_clk */ | |
142 | nop | |
143 | nop | |
144 | nop | |
145 | wait2: | |
146 | ldr r5, [r3] /* get status */ | |
147 | and r5, r5, #0x1 /* isolate core status */ | |
148 | cmp r5, #0x1 /* still locked? */ | |
149 | bne wait2 /* if lock, loop */ | |
150 | nop | |
151 | nop | |
152 | nop | |
153 | nop | |
154 | ldmfd sp!, {r4 - r6} | |
155 | mov pc, lr /* back to caller, locked */ | |
74236aca | 156 | ENDPROC(go_to_speed) |
5ed3e865 DB |
157 | |
158 | _go_to_speed: .word go_to_speed | |
159 | ||
160 | /* these constants need to be close for PIC code */ | |
161 | /* The Nor has to be in the Flash Base CS0 for this condition to happen */ | |
162 | flash_cfg1_addr: | |
3b9043a7 | 163 | .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1) |
5ed3e865 | 164 | flash_cfg3_addr: |
3b9043a7 | 165 | .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3) |
5ed3e865 DB |
166 | flash_cfg3_val: |
167 | .word STNOR_GPMC_CONFIG3 | |
168 | flash_cfg4_addr: | |
3b9043a7 | 169 | .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4) |
5ed3e865 DB |
170 | flash_cfg4_val: |
171 | .word STNOR_GPMC_CONFIG4 | |
172 | flash_cfg5_val: | |
173 | .word STNOR_GPMC_CONFIG5 | |
174 | flash_cfg5_addr: | |
3b9043a7 | 175 | .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5) |
5ed3e865 DB |
176 | pll_ctl_add: |
177 | .word CM_CLKEN_PLL | |
178 | pll_div_add1: | |
179 | .word CM_CLKSEL1_PLL | |
180 | pll_div_add2: | |
181 | .word CM_CLKSEL_CORE | |
182 | pll_div_add3: | |
183 | .word CM_CLKSEL_WKUP | |
184 | pll_div_val3: | |
185 | .word (WKUP_RSM << 1) | |
186 | pll_div_add4: | |
187 | .word CM_CLKSEL_GFX | |
188 | pll_div_val4: | |
189 | .word (GFX_DIV << 0) | |
190 | pll_div_add5: | |
191 | .word CM_CLKSEL1_EMU | |
192 | pll_div_val5: | |
193 | .word CLSEL1_EMU_VAL | |
194 | ||
195 | #endif | |
196 | ||
74236aca | 197 | ENTRY(lowlevel_init) |
5ed3e865 | 198 | ldr sp, SRAM_STACK |
dec96689 | 199 | str ip, [sp] /* stash ip register */ |
5ed3e865 | 200 | mov ip, lr /* save link reg across call */ |
e4fce34e A |
201 | #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) |
202 | /* | |
203 | * No need to copy/exec the clock code - DPLL adjust already done | |
204 | * in NAND/oneNAND Boot. | |
205 | */ | |
206 | ldr r1, =SRAM_CLK_CODE | |
207 | bl cpy_clk_code | |
208 | #endif /* NAND Boot */ | |
5ed3e865 | 209 | mov lr, ip /* restore link reg */ |
dec96689 AA |
210 | ldr ip, [sp] /* restore save ip */ |
211 | /* tail-call s_init to setup pll, mux, memory */ | |
212 | b s_init | |
5ed3e865 | 213 | |
74236aca | 214 | ENDPROC(lowlevel_init) |
5ed3e865 DB |
215 | |
216 | /* the literal pools origin */ | |
217 | .ltorg | |
218 | ||
219 | REG_CONTROL_STATUS: | |
220 | .word CONTROL_STATUS | |
221 | SRAM_STACK: | |
222 | .word LOW_LEVEL_SRAM_STACK | |
223 | ||
224 | /* DPLL(1-4) PARAM TABLES */ | |
225 | ||
226 | /* | |
227 | * Each of the tables has M, N, FREQSEL, M2 values defined for nominal | |
228 | * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c). | |
229 | * The values are defined for all possible sysclk and for ES1 and ES2. | |
230 | */ | |
231 | ||
232 | mpu_dpll_param: | |
233 | /* 12MHz */ | |
234 | /* ES1 */ | |
235 | .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1 | |
236 | /* ES2 */ | |
237 | .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2 | |
238 | /* 3410 */ | |
239 | .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12 | |
240 | ||
241 | /* 13MHz */ | |
242 | /* ES1 */ | |
243 | .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1 | |
244 | /* ES2 */ | |
245 | .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2 | |
246 | /* 3410 */ | |
247 | .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13 | |
248 | ||
249 | /* 19.2MHz */ | |
250 | /* ES1 */ | |
251 | .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1 | |
252 | /* ES2 */ | |
253 | .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2 | |
254 | /* 3410 */ | |
255 | .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2 | |
256 | ||
257 | /* 26MHz */ | |
258 | /* ES1 */ | |
259 | .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1 | |
260 | /* ES2 */ | |
261 | .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2 | |
262 | /* 3410 */ | |
263 | .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26 | |
264 | ||
265 | /* 38.4MHz */ | |
266 | /* ES1 */ | |
267 | .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1 | |
268 | /* ES2 */ | |
269 | .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2 | |
270 | /* 3410 */ | |
271 | .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4 | |
272 | ||
273 | ||
274 | .globl get_mpu_dpll_param | |
275 | get_mpu_dpll_param: | |
276 | adr r0, mpu_dpll_param | |
277 | mov pc, lr | |
278 | ||
279 | iva_dpll_param: | |
280 | /* 12MHz */ | |
281 | /* ES1 */ | |
282 | .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1 | |
283 | /* ES2 */ | |
284 | .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2 | |
285 | /* 3410 */ | |
286 | .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12 | |
287 | ||
288 | /* 13MHz */ | |
289 | /* ES1 */ | |
290 | .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1 | |
291 | /* ES2 */ | |
292 | .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2 | |
293 | /* 3410 */ | |
294 | .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13 | |
295 | ||
296 | /* 19.2MHz */ | |
297 | /* ES1 */ | |
298 | .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1 | |
299 | /* ES2 */ | |
300 | .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2 | |
301 | /* 3410 */ | |
302 | .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2 | |
303 | ||
304 | /* 26MHz */ | |
305 | /* ES1 */ | |
306 | .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1 | |
307 | /* ES2 */ | |
308 | .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2 | |
309 | /* 3410 */ | |
310 | .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26 | |
311 | ||
312 | /* 38.4MHz */ | |
313 | /* ES1 */ | |
314 | .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1 | |
315 | /* ES2 */ | |
316 | .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2 | |
317 | /* 3410 */ | |
318 | .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4 | |
319 | ||
320 | ||
321 | .globl get_iva_dpll_param | |
322 | get_iva_dpll_param: | |
323 | adr r0, iva_dpll_param | |
324 | mov pc, lr | |
325 | ||
326 | /* Core DPLL targets for L3 at 166 & L133 */ | |
327 | core_dpll_param: | |
328 | /* 12MHz */ | |
329 | /* ES1 */ | |
330 | .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1 | |
331 | /* ES2 */ | |
332 | .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 | |
333 | /* 3410 */ | |
334 | .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 | |
335 | ||
336 | /* 13MHz */ | |
337 | /* ES1 */ | |
338 | .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1 | |
339 | /* ES2 */ | |
340 | .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 | |
341 | /* 3410 */ | |
342 | .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 | |
343 | ||
344 | /* 19.2MHz */ | |
345 | /* ES1 */ | |
346 | .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1 | |
347 | /* ES2 */ | |
348 | .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 | |
349 | /* 3410 */ | |
350 | .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 | |
351 | ||
352 | /* 26MHz */ | |
353 | /* ES1 */ | |
354 | .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1 | |
355 | /* ES2 */ | |
356 | .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 | |
357 | /* 3410 */ | |
358 | .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 | |
359 | ||
360 | /* 38.4MHz */ | |
361 | /* ES1 */ | |
362 | .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1 | |
363 | /* ES2 */ | |
364 | .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 | |
365 | /* 3410 */ | |
366 | .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 | |
367 | ||
368 | .globl get_core_dpll_param | |
369 | get_core_dpll_param: | |
370 | adr r0, core_dpll_param | |
371 | mov pc, lr | |
372 | ||
373 | /* PER DPLL values are same for both ES1 and ES2 */ | |
374 | per_dpll_param: | |
375 | /* 12MHz */ | |
376 | .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12 | |
377 | ||
378 | /* 13MHz */ | |
379 | .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13 | |
380 | ||
381 | /* 19.2MHz */ | |
382 | .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2 | |
383 | ||
384 | /* 26MHz */ | |
385 | .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26 | |
386 | ||
387 | /* 38.4MHz */ | |
388 | .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4 | |
389 | ||
390 | .globl get_per_dpll_param | |
391 | get_per_dpll_param: | |
392 | adr r0, per_dpll_param | |
393 | mov pc, lr | |
7c281c98 | 394 | |
7b89795f AH |
395 | /* PER2 DPLL values */ |
396 | per2_dpll_param: | |
397 | /* 12MHz */ | |
398 | .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12 | |
399 | ||
400 | /* 13MHz */ | |
401 | .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13 | |
402 | ||
403 | /* 19.2MHz */ | |
404 | .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2 | |
405 | ||
406 | /* 26MHz */ | |
407 | .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26 | |
408 | ||
409 | /* 38.4MHz */ | |
410 | .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4 | |
411 | ||
412 | .globl get_per2_dpll_param | |
413 | get_per2_dpll_param: | |
414 | adr r0, per2_dpll_param | |
415 | mov pc, lr | |
416 | ||
7c281c98 SS |
417 | /* |
418 | * Tables for 36XX/37XX devices | |
419 | * | |
420 | */ | |
421 | mpu_36x_dpll_param: | |
422 | /* 12MHz */ | |
423 | .word 50, 0, 0, 1 | |
424 | /* 13MHz */ | |
425 | .word 600, 12, 0, 1 | |
426 | /* 19.2MHz */ | |
427 | .word 125, 3, 0, 1 | |
428 | /* 26MHz */ | |
429 | .word 300, 12, 0, 1 | |
430 | /* 38.4MHz */ | |
431 | .word 125, 7, 0, 1 | |
432 | ||
433 | iva_36x_dpll_param: | |
434 | /* 12MHz */ | |
435 | .word 130, 2, 0, 1 | |
436 | /* 13MHz */ | |
437 | .word 20, 0, 0, 1 | |
438 | /* 19.2MHz */ | |
439 | .word 325, 11, 0, 1 | |
440 | /* 26MHz */ | |
441 | .word 10, 0, 0, 1 | |
442 | /* 38.4MHz */ | |
443 | .word 325, 23, 0, 1 | |
444 | ||
445 | core_36x_dpll_param: | |
446 | /* 12MHz */ | |
447 | .word 100, 2, 0, 1 | |
448 | /* 13MHz */ | |
449 | .word 400, 12, 0, 1 | |
450 | /* 19.2MHz */ | |
451 | .word 375, 17, 0, 1 | |
452 | /* 26MHz */ | |
453 | .word 200, 12, 0, 1 | |
454 | /* 38.4MHz */ | |
455 | .word 375, 35, 0, 1 | |
456 | ||
457 | per_36x_dpll_param: | |
458 | /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */ | |
459 | .word 12000, 360, 4, 9, 16, 5, 4, 3, 1 | |
460 | .word 13000, 864, 12, 9, 16, 9, 4, 3, 1 | |
461 | .word 19200, 360, 7, 9, 16, 5, 4, 3, 1 | |
462 | .word 26000, 432, 12, 9, 16, 9, 4, 3, 1 | |
463 | .word 38400, 360, 15, 9, 16, 5, 4, 3, 1 | |
464 | ||
a704a6d6 NA |
465 | per2_36x_dpll_param: |
466 | /* 12MHz */ | |
467 | .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12 | |
468 | /* 13MHz */ | |
469 | .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13 | |
470 | /* 19.2MHz */ | |
471 | .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2 | |
472 | /* 26MHz */ | |
473 | .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26 | |
474 | /* 38.4MHz */ | |
475 | .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4 | |
476 | ||
477 | ||
74236aca | 478 | ENTRY(get_36x_mpu_dpll_param) |
7c281c98 SS |
479 | adr r0, mpu_36x_dpll_param |
480 | mov pc, lr | |
74236aca | 481 | ENDPROC(get_36x_mpu_dpll_param) |
7c281c98 | 482 | |
74236aca | 483 | ENTRY(get_36x_iva_dpll_param) |
7c281c98 SS |
484 | adr r0, iva_36x_dpll_param |
485 | mov pc, lr | |
74236aca | 486 | ENDPROC(get_36x_iva_dpll_param) |
7c281c98 | 487 | |
74236aca | 488 | ENTRY(get_36x_core_dpll_param) |
7c281c98 SS |
489 | adr r0, core_36x_dpll_param |
490 | mov pc, lr | |
74236aca | 491 | ENDPROC(get_36x_core_dpll_param) |
7c281c98 | 492 | |
74236aca | 493 | ENTRY(get_36x_per_dpll_param) |
7c281c98 SS |
494 | adr r0, per_36x_dpll_param |
495 | mov pc, lr | |
74236aca | 496 | ENDPROC(get_36x_per_dpll_param) |
a704a6d6 NA |
497 | |
498 | ENTRY(get_36x_per2_dpll_param) | |
499 | adr r0, per2_36x_dpll_param | |
500 | mov pc, lr | |
501 | ENDPROC(get_36x_per2_dpll_param) |