[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / lowlevel_init.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 *
 * Initial Code by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <version.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks_omap3.h>
#include <linux/linkage.h>

#ifdef CONFIG_SPL_BUILD
ENTRY(save_boot_params)
	ldr	r4, =omap3_boot_device
	ldr	r5, [r0, #0x4]
	and	r5, r5, #0xff
	str	r5, [r4]
	bx	lr
ENDPROC(save_boot_params)
#endif

ENTRY(omap3_gp_romcode_call)
	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	MOV r12, r0	@ Copy the Service ID in R12
	MOV r0, r1	@ Copy parameter to R0
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c10, 5	@ DMB
	.word	0xe1600070	@ SMC #0 to enter monitor - hand assembled
				@ because we use -march=armv5
	POP {r4-r12, pc}
ENDPROC(omap3_gp_romcode_call)

/*
 * Funtion for making PPA HAL API calls in secure devices
 * Input:
 *	R0 - Service ID
 *	R1 - paramer list
 */
ENTRY(do_omap3_emu_romcode_call)
	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	MOV r12, r0	@ Copy the Secure Service ID in R12
	MOV r3, r1	@ Copy the pointer to va_list in R3
	MOV r1, #0	@ Process ID - 0
	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL	@ Copy the pointer
							@ to va_list in R3
	MOV r6, #0xFF	@ Indicate new Task call
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c10, 5	@ DMB
	.word	0xe1600071	@ SMC #1 to call PPA service - hand assembled
				@ because we use -march=armv5
	POP {r4-r12, pc}
ENDPROC(do_omap3_emu_romcode_call)

#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
/**************************************************************************
 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
 * R1 = SRAM destination address.
 *************************************************************************/
ENTRY(cpy_clk_code)
	/* Copy DPLL code into SRAM */
	adr	r0, go_to_speed		/* copy from start of go_to_speed... */
	adr	r2, lowlevel_init	/* ... up to start of low_level_init */
next2:
	ldmia	r0!, {r3 - r10}		/* copy from source address [r0] */
	stmia	r1!, {r3 - r10}		/* copy to   target address [r1] */
	cmp	r0, r2			/* until source end address [r2] */
	blo	next2
	mov	pc, lr			/* back to caller */
ENDPROC(cpy_clk_code)

/* ***************************************************************************
 *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
 *               -executed from SRAM.
 *  R0 = CM_CLKEN_PLL-bypass value
 *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
 *  R2 = CM_CLKSEL_CORE-divider values
 *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
 *
 *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
 *        confused.  A reset of the controller gets it back.  Taking away its
 *        L3 when its not in self refresh seems bad for it.  Normally, this
 *	  code runs from flash before SDR is init so that should be ok.
 ****************************************************************************/
ENTRY(go_to_speed)
	stmfd sp!, {r4 - r6}

	/* move into fast relock bypass */
	ldr	r4, pll_ctl_add
	str	r0, [r4]
wait1:
	ldr	r5, [r3]		/* get status */
	and	r5, r5, #0x1		/* isolate core status */
	cmp	r5, #0x1		/* still locked? */
	beq	wait1			/* if lock, loop */

	/* set new dpll dividers _after_ in bypass */
	ldr	r5, pll_div_add1
	str	r1, [r5]		/* set m, n, m2 */
	ldr	r5, pll_div_add2
	str	r2, [r5]		/* set l3/l4/.. dividers*/
	ldr	r5, pll_div_add3	/* wkup */
	ldr	r2, pll_div_val3	/* rsm val */
	str	r2, [r5]
	ldr	r5, pll_div_add4	/* gfx */
	ldr	r2, pll_div_val4
	str	r2, [r5]
	ldr	r5, pll_div_add5	/* emu */
	ldr	r2, pll_div_val5
	str	r2, [r5]

	/* now prepare GPMC (flash) for new dpll speed */
	/* flash needs to be stable when we jump back to it */
	ldr	r5, flash_cfg3_addr
	ldr	r2, flash_cfg3_val
	str	r2, [r5]
	ldr	r5, flash_cfg4_addr
	ldr	r2, flash_cfg4_val
	str	r2, [r5]
	ldr	r5, flash_cfg5_addr
	ldr	r2, flash_cfg5_val
	str	r2, [r5]
	ldr	r5, flash_cfg1_addr
	ldr	r2, [r5]
	orr	r2, r2, #0x3		/* up gpmc divider */
	str	r2, [r5]

	/* lock DPLL3 and wait a bit */
	orr	r0, r0, #0x7	/* set up for lock mode */
	str	r0, [r4]	/* lock */
	nop			/* ARM slow at this point working at sys_clk */
	nop
	nop
	nop
wait2:
	ldr	r5, [r3]	/* get status */
	and	r5, r5, #0x1	/* isolate core status */
	cmp	r5, #0x1	/* still locked? */
	bne	wait2		/* if lock, loop */
	nop
	nop
	nop
	nop
	ldmfd	sp!, {r4 - r6}
	mov	pc, lr		/* back to caller, locked */
ENDPROC(go_to_speed)

_go_to_speed: .word go_to_speed

/* these constants need to be close for PIC code */
/* The Nor has to be in the Flash Base CS0 for this condition to happen */
flash_cfg1_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
flash_cfg3_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
flash_cfg3_val:
	.word STNOR_GPMC_CONFIG3
flash_cfg4_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
flash_cfg4_val:
	.word STNOR_GPMC_CONFIG4
flash_cfg5_val:
	.word STNOR_GPMC_CONFIG5
flash_cfg5_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
pll_ctl_add:
	.word CM_CLKEN_PLL
pll_div_add1:
	.word CM_CLKSEL1_PLL
pll_div_add2:
	.word CM_CLKSEL_CORE
pll_div_add3:
	.word CM_CLKSEL_WKUP
pll_div_val3:
	.word (WKUP_RSM << 1)
pll_div_add4:
	.word CM_CLKSEL_GFX
pll_div_val4:
	.word (GFX_DIV << 0)
pll_div_add5:
	.word CM_CLKSEL1_EMU
pll_div_val5:
	.word CLSEL1_EMU_VAL

#endif

ENTRY(lowlevel_init)
	ldr	sp, SRAM_STACK
	str	ip, [sp]	/* stash ip register */
	mov	ip, lr		/* save link reg across call */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/*
 * No need to copy/exec the clock code - DPLL adjust already done
 * in NAND/oneNAND Boot.
 */
	ldr	r1, =SRAM_CLK_CODE
	bl	cpy_clk_code
#endif /* NAND Boot */
	mov	lr, ip		/* restore link reg */
	ldr	ip, [sp]	/* restore save ip */
	/* tail-call s_init to setup pll, mux, memory */
	b	s_init

ENDPROC(lowlevel_init)

	/* the literal pools origin */
	.ltorg

REG_CONTROL_STATUS:
	.word CONTROL_STATUS
SRAM_STACK:
	.word LOW_LEVEL_SRAM_STACK

/* DPLL(1-4) PARAM TABLES */

/*
 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
 * The values are defined for all possible sysclk and for ES1 and ES2.
 */

mpu_dpll_param:
/* 12MHz */
/* ES1 */
.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
/* ES2 */
.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
/* 3410 */
.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12

/* 13MHz */
/* ES1 */
.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
/* ES2 */
.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
/* 3410 */
.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13

/* 19.2MHz */
/* ES1 */
.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
/* ES2 */
.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
/* 3410 */
.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2

/* 26MHz */
/* ES1 */
.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
/* ES2 */
.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
/* 3410 */
.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26

/* 38.4MHz */
/* ES1 */
.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
/* ES2 */
.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
/* 3410 */
.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4


.globl get_mpu_dpll_param
get_mpu_dpll_param:
	adr	r0, mpu_dpll_param
	mov	pc, lr

iva_dpll_param:
/* 12MHz */
/* ES1 */
.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
/* ES2 */
.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
/* 3410 */
.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12

/* 13MHz */
/* ES1 */
.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
/* ES2 */
.word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
/* 3410 */
.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13

/* 19.2MHz */
/* ES1 */
.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
/* ES2 */
.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
/* 3410 */
.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2

/* 26MHz */
/* ES1 */
.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
/* ES2 */
.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
/* 3410 */
.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26

/* 38.4MHz */
/* ES1 */
.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
/* ES2 */
.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
/* 3410 */
.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4


.globl get_iva_dpll_param
get_iva_dpll_param:
	adr	r0, iva_dpll_param
	mov	pc, lr

/* Core DPLL targets for L3 at 166 & L133 */
core_dpll_param:
/* 12MHz */
/* ES1 */
.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
/* ES2 */
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
/* 3410 */
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12

/* 13MHz */
/* ES1 */
.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
/* ES2 */
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
/* 3410 */
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13

/* 19.2MHz */
/* ES1 */
.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
/* ES2 */
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
/* 3410 */
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2

/* 26MHz */
/* ES1 */
.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
/* ES2 */
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
/* 3410 */
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26

/* 38.4MHz */
/* ES1 */
.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
/* ES2 */
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
/* 3410 */
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4

.globl get_core_dpll_param
get_core_dpll_param:
	adr	r0, core_dpll_param
	mov	pc, lr

/* PER DPLL values are same for both ES1 and ES2 */
per_dpll_param:
/* 12MHz */
.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12

/* 13MHz */
.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13

/* 19.2MHz */
.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2

/* 26MHz */
.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26

/* 38.4MHz */
.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4

.globl get_per_dpll_param
get_per_dpll_param:
	adr	r0, per_dpll_param
	mov	pc, lr

/* PER2 DPLL values */
per2_dpll_param:
/* 12MHz */
.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12

/* 13MHz */
.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13

/* 19.2MHz */
.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2

/* 26MHz */
.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26

/* 38.4MHz */
.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4

.globl get_per2_dpll_param
get_per2_dpll_param:
	adr	r0, per2_dpll_param
	mov	pc, lr

/*
 * Tables for 36XX/37XX devices
 *
 */
mpu_36x_dpll_param:
/* 12MHz */
.word 50, 0, 0, 1
/* 13MHz */
.word 600, 12, 0, 1
/* 19.2MHz */
.word 125, 3, 0, 1
/* 26MHz */
.word 300, 12, 0, 1
/* 38.4MHz */
.word 125, 7, 0, 1

iva_36x_dpll_param:
/* 12MHz */
.word 130, 2, 0, 1
/* 13MHz */
.word 20, 0, 0, 1
/* 19.2MHz */
.word 325, 11, 0, 1
/* 26MHz */
.word 10, 0, 0, 1
/* 38.4MHz */
.word 325, 23, 0, 1

core_36x_dpll_param:
/* 12MHz */
.word 100, 2, 0, 1
/* 13MHz */
.word 400, 12, 0, 1
/* 19.2MHz */
.word 375, 17, 0, 1
/* 26MHz */
.word 200, 12, 0, 1
/* 38.4MHz */
.word 375, 35, 0, 1

per_36x_dpll_param:
/*    SYSCLK    M       N      M2      M3      M4     M5      M6      m2DIV */
.word 12000,    360,    4,     9,      16,     5,     4,      3,      1
.word 13000,    864,   12,     9,      16,     9,     4,      3,      1
.word 19200,    360,    7,     9,      16,     5,     4,      3,      1
.word 26000,    432,   12,     9,      16,     9,     4,      3,      1
.word 38400,    360,   15,     9,      16,     5,     4,      3,      1

per2_36x_dpll_param:
/* 12MHz */
.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
/* 13MHz */
.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
/* 19.2MHz */
.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
/* 26MHz */
.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
/* 38.4MHz */
.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4


ENTRY(get_36x_mpu_dpll_param)
	adr	r0, mpu_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_mpu_dpll_param)

ENTRY(get_36x_iva_dpll_param)
	adr	r0, iva_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_iva_dpll_param)

ENTRY(get_36x_core_dpll_param)
	adr	r0, core_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_core_dpll_param)

ENTRY(get_36x_per_dpll_param)
	adr	r0, per_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_per_dpll_param)

ENTRY(get_36x_per2_dpll_param)
	adr	r0, per2_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_per2_dpll_param)
Commit	Line	Data
5ed3e865 DB	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2008
	5	* Texas Instruments, <www.ti.com>
	6	*
	7	* Initial Code by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Syed Mohammed Khasim <khasim@ti.com>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
5ed3e865 DB	12	*/
	13
	14	#include <config.h>
	15	#include <version.h>
	16	#include <asm/arch/mem.h>
	17	#include <asm/arch/clocks_omap3.h>
74236aca	18	#include <linux/linkage.h>
5ed3e865	19
20470511	20	#ifdef CONFIG_SPL_BUILD
74236aca	21	ENTRY(save_boot_params)
409ef1bc SS	22	ldr r4, =omap3_boot_device
	23	ldr r5, [r0, #0x4]
	24	and r5, r5, #0xff
	25	str r5, [r4]
409ef1bc	26	bx lr
74236aca	27	ENDPROC(save_boot_params)
20470511	28	#endif
78ce9779	29
74236aca	30	ENTRY(omap3_gp_romcode_call)
45bf0585 A	31	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	32	MOV r12, r0 @ Copy the Service ID in R12
	33	MOV r0, r1 @ Copy parameter to R0
	34	mcr p15, 0, r0, c7, c10, 4 @ DSB
	35	mcr p15, 0, r0, c7, c10, 5 @ DMB
	36	.word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
	37	@ because we use -march=armv5
	38	POP {r4-r12, pc}
74236aca	39	ENDPROC(omap3_gp_romcode_call)
45bf0585 A	40
	41	/*
	42	* Funtion for making PPA HAL API calls in secure devices
	43	* Input:
	44	* R0 - Service ID
	45	* R1 - paramer list
	46	*/
74236aca	47	ENTRY(do_omap3_emu_romcode_call)
45bf0585 A	48	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	49	MOV r12, r0 @ Copy the Secure Service ID in R12
	50	MOV r3, r1 @ Copy the pointer to va_list in R3
	51	MOV r1, #0 @ Process ID - 0
	52	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
	53	@ to va_list in R3
	54	MOV r6, #0xFF @ Indicate new Task call
	55	mcr p15, 0, r0, c7, c10, 4 @ DSB
	56	mcr p15, 0, r0, c7, c10, 5 @ DMB
	57	.word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
	58	@ because we use -march=armv5
	59	POP {r4-r12, pc}
74236aca	60	ENDPROC(do_omap3_emu_romcode_call)
45bf0585	61
5ed3e865 DB	62	#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
	63	/**************************************************************************
	64	* cpy_clk_code: relocates clock code into SRAM where its safer to execute
	65	* R1 = SRAM destination address.
	66	*************************************************************************/
74236aca	67	ENTRY(cpy_clk_code)
5ed3e865	68	/* Copy DPLL code into SRAM */
8d208366 AA	69	adr r0, go_to_speed /* copy from start of go_to_speed... */
8d208366 AA	70	adr r2, lowlevel_init /* ... up to start of low_level_init */
5ed3e865 DB	71	next2:
	72	ldmia r0!, {r3 - r10} /* copy from source address [r0] */
	73	stmia r1!, {r3 - r10} /* copy to target address [r1] */
	74	cmp r0, r2 /* until source end address [r2] */
8d208366	75	blo next2
5ed3e865	76	mov pc, lr /* back to caller */
74236aca	77	ENDPROC(cpy_clk_code)
5ed3e865 DB	78
	79	/* ***************************************************************************
	80	* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
	81	* -executed from SRAM.
	82	* R0 = CM_CLKEN_PLL-bypass value
	83	* R1 = CM_CLKSEL1_PLL-m, n, and divider values
	84	* R2 = CM_CLKSEL_CORE-divider values
	85	* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
	86	*
	87	* Note: If core unlocks/relocks and SDRAM is running fast already it gets
	88	* confused. A reset of the controller gets it back. Taking away its
	89	* L3 when its not in self refresh seems bad for it. Normally, this
	90	* code runs from flash before SDR is init so that should be ok.
	91	****************************************************************************/
74236aca	92	ENTRY(go_to_speed)
5ed3e865 DB	93	stmfd sp!, {r4 - r6}
	94
	95	/* move into fast relock bypass */
	96	ldr r4, pll_ctl_add
	97	str r0, [r4]
	98	wait1:
	99	ldr r5, [r3] /* get status */
	100	and r5, r5, #0x1 /* isolate core status */
	101	cmp r5, #0x1 /* still locked? */
	102	beq wait1 /* if lock, loop */
	103
	104	/* set new dpll dividers _after_ in bypass */
	105	ldr r5, pll_div_add1
	106	str r1, [r5] /* set m, n, m2 */
	107	ldr r5, pll_div_add2
	108	str r2, [r5] /* set l3/l4/.. dividers*/
	109	ldr r5, pll_div_add3 /* wkup */
	110	ldr r2, pll_div_val3 /* rsm val */
	111	str r2, [r5]
	112	ldr r5, pll_div_add4 /* gfx */
	113	ldr r2, pll_div_val4
	114	str r2, [r5]
	115	ldr r5, pll_div_add5 /* emu */
	116	ldr r2, pll_div_val5
	117	str r2, [r5]
	118
	119	/* now prepare GPMC (flash) for new dpll speed */
	120	/* flash needs to be stable when we jump back to it */
	121	ldr r5, flash_cfg3_addr
	122	ldr r2, flash_cfg3_val
	123	str r2, [r5]
	124	ldr r5, flash_cfg4_addr
	125	ldr r2, flash_cfg4_val
	126	str r2, [r5]
	127	ldr r5, flash_cfg5_addr
	128	ldr r2, flash_cfg5_val
	129	str r2, [r5]
	130	ldr r5, flash_cfg1_addr
	131	ldr r2, [r5]
	132	orr r2, r2, #0x3 /* up gpmc divider */
	133	str r2, [r5]
	134
	135	/* lock DPLL3 and wait a bit */
	136	orr r0, r0, #0x7 /* set up for lock mode */
	137	str r0, [r4] /* lock */
	138	nop /* ARM slow at this point working at sys_clk */
	139	nop
	140	nop
	141	nop
	142	wait2:
	143	ldr r5, [r3] /* get status */
	144	and r5, r5, #0x1 /* isolate core status */
	145	cmp r5, #0x1 /* still locked? */
	146	bne wait2 /* if lock, loop */
	147	nop
	148	nop
	149	nop
	150	nop
	151	ldmfd sp!, {r4 - r6}
	152	mov pc, lr /* back to caller, locked */
74236aca	153	ENDPROC(go_to_speed)
5ed3e865 DB	154
	155	_go_to_speed: .word go_to_speed
	156
	157	/* these constants need to be close for PIC code */
	158	/* The Nor has to be in the Flash Base CS0 for this condition to happen */
	159	flash_cfg1_addr:
3b9043a7	160	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
5ed3e865	161	flash_cfg3_addr:
3b9043a7	162	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
5ed3e865 DB	163	flash_cfg3_val:
	164	.word STNOR_GPMC_CONFIG3
	165	flash_cfg4_addr:
3b9043a7	166	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
5ed3e865 DB	167	flash_cfg4_val:
	168	.word STNOR_GPMC_CONFIG4
	169	flash_cfg5_val:
	170	.word STNOR_GPMC_CONFIG5
	171	flash_cfg5_addr:
3b9043a7	172	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
5ed3e865 DB	173	pll_ctl_add:
	174	.word CM_CLKEN_PLL
	175	pll_div_add1:
	176	.word CM_CLKSEL1_PLL
	177	pll_div_add2:
	178	.word CM_CLKSEL_CORE
	179	pll_div_add3:
	180	.word CM_CLKSEL_WKUP
	181	pll_div_val3:
	182	.word (WKUP_RSM << 1)
	183	pll_div_add4:
	184	.word CM_CLKSEL_GFX
	185	pll_div_val4:
	186	.word (GFX_DIV << 0)
	187	pll_div_add5:
	188	.word CM_CLKSEL1_EMU
	189	pll_div_val5:
	190	.word CLSEL1_EMU_VAL
	191
	192	#endif
	193
74236aca	194	ENTRY(lowlevel_init)
5ed3e865	195	ldr sp, SRAM_STACK
dec96689	196	str ip, [sp] /* stash ip register */
5ed3e865	197	mov ip, lr /* save link reg across call */
e4fce34e A	198	#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
	199	/*
	200	* No need to copy/exec the clock code - DPLL adjust already done
	201	* in NAND/oneNAND Boot.
	202	*/
	203	ldr r1, =SRAM_CLK_CODE
	204	bl cpy_clk_code
	205	#endif /* NAND Boot */
5ed3e865	206	mov lr, ip /* restore link reg */
dec96689 AA	207	ldr ip, [sp] /* restore save ip */
	208	/* tail-call s_init to setup pll, mux, memory */
	209	b s_init
5ed3e865	210
74236aca	211	ENDPROC(lowlevel_init)
5ed3e865 DB	212
	213	/* the literal pools origin */
	214	.ltorg
	215
	216	REG_CONTROL_STATUS:
	217	.word CONTROL_STATUS
	218	SRAM_STACK:
	219	.word LOW_LEVEL_SRAM_STACK
	220
	221	/* DPLL(1-4) PARAM TABLES */
	222
	223	/*
	224	* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
	225	* OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
	226	* The values are defined for all possible sysclk and for ES1 and ES2.
	227	*/
	228
	229	mpu_dpll_param:
	230	/* 12MHz */
	231	/* ES1 */
	232	.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
	233	/* ES2 */
	234	.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
	235	/* 3410 */
	236	.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
	237
	238	/* 13MHz */
	239	/* ES1 */
	240	.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
	241	/* ES2 */
	242	.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
	243	/* 3410 */
	244	.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
	245
	246	/* 19.2MHz */
	247	/* ES1 */
	248	.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
	249	/* ES2 */
	250	.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
	251	/* 3410 */
	252	.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
	253
	254	/* 26MHz */
	255	/* ES1 */
	256	.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
	257	/* ES2 */
	258	.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
	259	/* 3410 */
	260	.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
	261
	262	/* 38.4MHz */
	263	/* ES1 */
	264	.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
	265	/* ES2 */
	266	.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
	267	/* 3410 */
	268	.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
	269
	270
	271	.globl get_mpu_dpll_param
	272	get_mpu_dpll_param:
	273	adr r0, mpu_dpll_param
	274	mov pc, lr
	275
276	iva_dpll_param:
277	/* 12MHz */
278	/* ES1 */
279	.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
280	/* ES2 */
281	.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
282	/* 3410 */
283	.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
284
285	/* 13MHz */
286	/* ES1 */
287	.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
288	/* ES2 */
289	.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
290	/* 3410 */
291	.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
292
293	/* 19.2MHz */
294	/* ES1 */
295	.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
296	/* ES2 */
297	.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
298	/* 3410 */
299	.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
300
301	/* 26MHz */
302	/* ES1 */
303	.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
304	/* ES2 */
305	.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
306	/* 3410 */
307	.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
308
309	/* 38.4MHz */
310	/* ES1 */
311	.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
312	/* ES2 */
313	.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
314	/* 3410 */
315	.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
316
317
318	.globl get_iva_dpll_param
319	get_iva_dpll_param:
320	adr r0, iva_dpll_param
321	mov pc, lr
322
323	/* Core DPLL targets for L3 at 166 & L133 */
324	core_dpll_param:
325	/* 12MHz */
326	/* ES1 */
327	.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
328	/* ES2 */
329	.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
330	/* 3410 */
331	.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
332
333	/* 13MHz */
334	/* ES1 */
335	.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
336	/* ES2 */
337	.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
338	/* 3410 */
339	.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
340
341	/* 19.2MHz */
342	/* ES1 */
343	.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
344	/* ES2 */
345	.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
346	/* 3410 */
347	.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
348
349	/* 26MHz */
350	/* ES1 */
351	.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
352	/* ES2 */
353	.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
354	/* 3410 */
355	.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
356
357	/* 38.4MHz */
358	/* ES1 */
359	.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
360	/* ES2 */
361	.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
362	/* 3410 */
363	.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
364
365	.globl get_core_dpll_param
366	get_core_dpll_param:
367	adr r0, core_dpll_param
368	mov pc, lr
369
370	/* PER DPLL values are same for both ES1 and ES2 */
371	per_dpll_param:
372	/* 12MHz */
373	.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
374
375	/* 13MHz */
376	.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
377
378	/* 19.2MHz */
379	.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
380
381	/* 26MHz */
382	.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
383
384	/* 38.4MHz */
385	.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
386
387	.globl get_per_dpll_param
388	get_per_dpll_param:
389	adr r0, per_dpll_param
390	mov pc, lr
7c281c98	391
7b89795f AH	392	/* PER2 DPLL values */
	393	per2_dpll_param:
	394	/* 12MHz */
	395	.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
	396
	397	/* 13MHz */
	398	.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
	399
	400	/* 19.2MHz */
	401	.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
	402
	403	/* 26MHz */
	404	.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
	405
	406	/* 38.4MHz */
	407	.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
	408
	409	.globl get_per2_dpll_param
	410	get_per2_dpll_param:
	411	adr r0, per2_dpll_param
	412	mov pc, lr
	413
7c281c98 SS	414	/*
	415	* Tables for 36XX/37XX devices
	416	*
	417	*/
	418	mpu_36x_dpll_param:
	419	/* 12MHz */
	420	.word 50, 0, 0, 1
	421	/* 13MHz */
	422	.word 600, 12, 0, 1
	423	/* 19.2MHz */
	424	.word 125, 3, 0, 1
	425	/* 26MHz */
	426	.word 300, 12, 0, 1
	427	/* 38.4MHz */
	428	.word 125, 7, 0, 1
	429
	430	iva_36x_dpll_param:
	431	/* 12MHz */
	432	.word 130, 2, 0, 1
	433	/* 13MHz */
	434	.word 20, 0, 0, 1
	435	/* 19.2MHz */
	436	.word 325, 11, 0, 1
	437	/* 26MHz */
	438	.word 10, 0, 0, 1
	439	/* 38.4MHz */
	440	.word 325, 23, 0, 1
	441
	442	core_36x_dpll_param:
	443	/* 12MHz */
	444	.word 100, 2, 0, 1
	445	/* 13MHz */
	446	.word 400, 12, 0, 1
	447	/* 19.2MHz */
	448	.word 375, 17, 0, 1
	449	/* 26MHz */
	450	.word 200, 12, 0, 1
	451	/* 38.4MHz */
	452	.word 375, 35, 0, 1
	453
	454	per_36x_dpll_param:
	455	/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
	456	.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
	457	.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
	458	.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
	459	.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
	460	.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
	461
a704a6d6 NA	462	per2_36x_dpll_param:
	463	/* 12MHz */
	464	.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
	465	/* 13MHz */
	466	.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
	467	/* 19.2MHz */
	468	.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
	469	/* 26MHz */
	470	.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
	471	/* 38.4MHz */
	472	.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
	473
	474
74236aca	475	ENTRY(get_36x_mpu_dpll_param)
7c281c98 SS	476	adr r0, mpu_36x_dpll_param
7c281c98 SS	477	mov pc, lr
74236aca	478	ENDPROC(get_36x_mpu_dpll_param)
7c281c98	479
74236aca	480	ENTRY(get_36x_iva_dpll_param)
7c281c98 SS	481	adr r0, iva_36x_dpll_param
7c281c98 SS	482	mov pc, lr
74236aca	483	ENDPROC(get_36x_iva_dpll_param)
7c281c98	484
74236aca	485	ENTRY(get_36x_core_dpll_param)
7c281c98 SS	486	adr r0, core_36x_dpll_param
7c281c98 SS	487	mov pc, lr
74236aca	488	ENDPROC(get_36x_core_dpll_param)
7c281c98	489
74236aca	490	ENTRY(get_36x_per_dpll_param)
7c281c98 SS	491	adr r0, per_36x_dpll_param
7c281c98 SS	492	mov pc, lr
74236aca	493	ENDPROC(get_36x_per_dpll_param)
a704a6d6 NA	494
	495	ENTRY(get_36x_per2_dpll_param)
	496	adr r0, per2_36x_dpll_param
	497	mov pc, lr
	498	ENDPROC(get_36x_per2_dpll_param)