[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap4 / hw_data.c

/*
 *
 * HW data initialization for OMAP4
 *
 * (C) Copyright 2013
 * Texas Instruments, <www.ti.com>
 *
 * Sricharan R <r.sricharan@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>

struct prcm_regs const **prcm =
			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
			(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;

/*
 * The M & N values in the following tables are created using the
 * following tool:
 * tools/omap/clocks_get_m_n.c
 * Please use this tool for creating the table for any new frequency.
 */

/*
 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
 * OMAP4460 OPP_NOM frequency
 */
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
	{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
};

/*
 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
 * OMAP4430 OPP_TURBO frequency
 */
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
};

/*
 * dpll locked at 1200 MHz - MPU clk at 600 MHz
 * OMAP4430 OPP_NOM frequency
 */
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
	{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
	{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
};

/* OMAP4460 OPP_NOM frequency */
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
	{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
	{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
	{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
	{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
	{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
	{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
	{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
};

/* OMAP4430 ES1 OPP_NOM frequency */
static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
	{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
	{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
	{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
	{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
	{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
	{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
	{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
};

/* OMAP4430 ES2.X OPP_NOM frequency */
static const struct dpll_params
		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
	{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
	{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
	{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
	{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
	{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
	{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
	{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
};

static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
	{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 12 MHz   */
	{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 13 MHz   */
	{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 16.8 MHz */
	{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 19.2 MHz */
	{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 26 MHz   */
	{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 27 MHz   */
	{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}	/* 38.4 MHz */
};

static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
	{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
};

/* ABE M & N values with sys_clk as source */
static const struct dpll_params
		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
	{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
};

/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};

static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
	{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
	{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
};

struct dplls omap4430_dplls_es1 = {
	.mpu = mpu_dpll_params_1200mhz,
	.core = core_dpll_params_es1_1524mhz,
	.per = per_dpll_params_1536mhz,
	.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	.abe = abe_dpll_params_sysclk_196608khz,
#else
	.abe = &abe_dpll_params_32k_196608khz,
#endif
	.usb = usb_dpll_params_1920mhz,
	.ddr = NULL
};

struct dplls omap4430_dplls = {
	.mpu = mpu_dpll_params_1200mhz,
	.core = core_dpll_params_1600mhz,
	.per = per_dpll_params_1536mhz,
	.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	.abe = abe_dpll_params_sysclk_196608khz,
#else
	.abe = &abe_dpll_params_32k_196608khz,
#endif
	.usb = usb_dpll_params_1920mhz,
	.ddr = NULL
};

struct dplls omap4460_dplls = {
	.mpu = mpu_dpll_params_1400mhz,
	.core = core_dpll_params_1600mhz,
	.per = per_dpll_params_1536mhz,
	.iva = iva_dpll_params_1862mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	.abe = abe_dpll_params_sysclk_196608khz,
#else
	.abe = &abe_dpll_params_32k_196608khz,
#endif
	.usb = usb_dpll_params_1920mhz,
	.ddr = NULL
};

struct pmic_data twl6030_4430es1 = {
	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
	.step = 12660, /* 12.66 mV represented in uV */
	/* The code starts at 1 not 0 */
	.start_code = 1,
	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
	.pmic_bus_init	= sri2c_init,
	.pmic_write	= omap_vc_bypass_send_value,
};

struct pmic_data twl6030 = {
	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
	.step = 12660, /* 12.66 mV represented in uV */
	/* The code starts at 1 not 0 */
	.start_code = 1,
	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
	.pmic_bus_init	= sri2c_init,
	.pmic_write	= omap_vc_bypass_send_value,
};

struct pmic_data tps62361 = {
	.base_offset = TPS62361_BASE_VOLT_MV,
	.step = 10000, /* 10 mV represented in uV */
	.start_code = 0,
	.gpio = TPS62361_VSEL0_GPIO,
	.gpio_en = 1,
	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
	.pmic_bus_init	= sri2c_init,
	.pmic_write	= omap_vc_bypass_send_value,
};

struct vcores_data omap4430_volts_es1 = {
	.mpu.value = 1325,
	.mpu.addr = SMPS_REG_ADDR_VCORE1,
	.mpu.pmic = &twl6030_4430es1,

	.core.value = 1200,
	.core.addr = SMPS_REG_ADDR_VCORE3,
	.core.pmic = &twl6030_4430es1,

	.mm.value = 1200,
	.mm.addr = SMPS_REG_ADDR_VCORE2,
	.mm.pmic = &twl6030_4430es1,
};

struct vcores_data omap4430_volts = {
	.mpu.value = 1325,
	.mpu.addr = SMPS_REG_ADDR_VCORE1,
	.mpu.pmic = &twl6030,

	.core.value = 1200,
	.core.addr = SMPS_REG_ADDR_VCORE3,
	.core.pmic = &twl6030,

	.mm.value = 1200,
	.mm.addr = SMPS_REG_ADDR_VCORE2,
	.mm.pmic = &twl6030,
};

struct vcores_data omap4460_volts = {
	.mpu.value = 1203,
	.mpu.addr = TPS62361_REG_ADDR_SET1,
	.mpu.pmic = &tps62361,

	.core.value = 1200,
	.core.addr = SMPS_REG_ADDR_VCORE1,
	.core.pmic = &twl6030,

	.mm.value = 1200,
	.mm.addr = SMPS_REG_ADDR_VCORE2,
	.mm.pmic = &twl6030,
};

/*
 * Enable essential clock domains, modules and
 * do some additional special settings needed
 */
void enable_basic_clocks(void)
{
	u32 const clk_domains_essential[] = {
		(*prcm)->cm_l4per_clkstctrl,
		(*prcm)->cm_l3init_clkstctrl,
		(*prcm)->cm_memif_clkstctrl,
		(*prcm)->cm_l4cfg_clkstctrl,
		0
	};

	u32 const clk_modules_hw_auto_essential[] = {
		(*prcm)->cm_l3_gpmc_clkctrl,
		(*prcm)->cm_memif_emif_1_clkctrl,
		(*prcm)->cm_memif_emif_2_clkctrl,
		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
		(*prcm)->cm_wkup_gpio1_clkctrl,
		(*prcm)->cm_l4per_gpio2_clkctrl,
		(*prcm)->cm_l4per_gpio3_clkctrl,
		(*prcm)->cm_l4per_gpio4_clkctrl,
		(*prcm)->cm_l4per_gpio5_clkctrl,
		(*prcm)->cm_l4per_gpio6_clkctrl,
		0
	};

	u32 const clk_modules_explicit_en_essential[] = {
		(*prcm)->cm_wkup_gptimer1_clkctrl,
		(*prcm)->cm_l3init_hsmmc1_clkctrl,
		(*prcm)->cm_l3init_hsmmc2_clkctrl,
		(*prcm)->cm_l4per_gptimer2_clkctrl,
		(*prcm)->cm_wkup_wdtimer2_clkctrl,
		(*prcm)->cm_l4per_uart3_clkctrl,
		0
	};

	/* Enable optional additional functional clock for GPIO4 */
	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
			GPIO4_CLKCTRL_OPTFCLKEN_MASK);

	/* Enable 96 MHz clock for MMC1 & MMC2 */
	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
			HSMMC_CLKCTRL_CLKSEL_MASK);
	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
			HSMMC_CLKCTRL_CLKSEL_MASK);

	/* Select 32KHz clock as the source of GPTIMER1 */
	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
			GPTIMER1_CLKCTRL_CLKSEL_MASK);

	/* Enable optional 48M functional clock for USB  PHY */
	setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);

	do_enable_clocks(clk_domains_essential,
			 clk_modules_hw_auto_essential,
			 clk_modules_explicit_en_essential,
			 1);
}

void enable_basic_uboot_clocks(void)
{
	u32 const clk_domains_essential[] = {
		0
	};

	u32 const clk_modules_hw_auto_essential[] = {
		(*prcm)->cm_l3init_hsusbotg_clkctrl,
		(*prcm)->cm_l3init_usbphy_clkctrl,
		(*prcm)->cm_l3init_usbphy_clkctrl,
		(*prcm)->cm_clksel_usb_60mhz,
		(*prcm)->cm_l3init_hsusbtll_clkctrl,
		0
	};

	u32 const clk_modules_explicit_en_essential[] = {
		(*prcm)->cm_l4per_mcspi1_clkctrl,
		(*prcm)->cm_l4per_i2c1_clkctrl,
		(*prcm)->cm_l4per_i2c2_clkctrl,
		(*prcm)->cm_l4per_i2c3_clkctrl,
		(*prcm)->cm_l4per_i2c4_clkctrl,
		(*prcm)->cm_l3init_hsusbhost_clkctrl,
		0
	};

	do_enable_clocks(clk_domains_essential,
			 clk_modules_hw_auto_essential,
			 clk_modules_explicit_en_essential,
			 1);
}

/*
 * Enable non-essential clock domains, modules and
 * do some additional special settings needed
 */
void enable_non_essential_clocks(void)
{
	u32 const clk_domains_non_essential[] = {
		(*prcm)->cm_mpu_m3_clkstctrl,
		(*prcm)->cm_ivahd_clkstctrl,
		(*prcm)->cm_dsp_clkstctrl,
		(*prcm)->cm_dss_clkstctrl,
		(*prcm)->cm_sgx_clkstctrl,
		(*prcm)->cm1_abe_clkstctrl,
		(*prcm)->cm_c2c_clkstctrl,
		(*prcm)->cm_cam_clkstctrl,
		(*prcm)->cm_dss_clkstctrl,
		(*prcm)->cm_sdma_clkstctrl,
		0
	};

	u32 const clk_modules_hw_auto_non_essential[] = {
		(*prcm)->cm_l3instr_l3_3_clkctrl,
		(*prcm)->cm_l3instr_l3_instr_clkctrl,
		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
		(*prcm)->cm_l3init_hsi_clkctrl,
		0
	};

	u32 const clk_modules_explicit_en_non_essential[] = {
		(*prcm)->cm1_abe_aess_clkctrl,
		(*prcm)->cm1_abe_pdm_clkctrl,
		(*prcm)->cm1_abe_dmic_clkctrl,
		(*prcm)->cm1_abe_mcasp_clkctrl,
		(*prcm)->cm1_abe_mcbsp1_clkctrl,
		(*prcm)->cm1_abe_mcbsp2_clkctrl,
		(*prcm)->cm1_abe_mcbsp3_clkctrl,
		(*prcm)->cm1_abe_slimbus_clkctrl,
		(*prcm)->cm1_abe_timer5_clkctrl,
		(*prcm)->cm1_abe_timer6_clkctrl,
		(*prcm)->cm1_abe_timer7_clkctrl,
		(*prcm)->cm1_abe_timer8_clkctrl,
		(*prcm)->cm1_abe_wdt3_clkctrl,
		(*prcm)->cm_l4per_gptimer9_clkctrl,
		(*prcm)->cm_l4per_gptimer10_clkctrl,
		(*prcm)->cm_l4per_gptimer11_clkctrl,
		(*prcm)->cm_l4per_gptimer3_clkctrl,
		(*prcm)->cm_l4per_gptimer4_clkctrl,
		(*prcm)->cm_l4per_hdq1w_clkctrl,
		(*prcm)->cm_l4per_mcbsp4_clkctrl,
		(*prcm)->cm_l4per_mcspi2_clkctrl,
		(*prcm)->cm_l4per_mcspi3_clkctrl,
		(*prcm)->cm_l4per_mcspi4_clkctrl,
		(*prcm)->cm_l4per_mmcsd3_clkctrl,
		(*prcm)->cm_l4per_mmcsd4_clkctrl,
		(*prcm)->cm_l4per_mmcsd5_clkctrl,
		(*prcm)->cm_l4per_uart1_clkctrl,
		(*prcm)->cm_l4per_uart2_clkctrl,
		(*prcm)->cm_l4per_uart4_clkctrl,
		(*prcm)->cm_wkup_keyboard_clkctrl,
		(*prcm)->cm_wkup_wdtimer2_clkctrl,
		(*prcm)->cm_cam_iss_clkctrl,
		(*prcm)->cm_cam_fdif_clkctrl,
		(*prcm)->cm_dss_dss_clkctrl,
		(*prcm)->cm_sgx_sgx_clkctrl,
		0
	};

	/* Enable optional functional clock for ISS */
	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);

	/* Enable all optional functional clocks of DSS */
	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);

	do_enable_clocks(clk_domains_non_essential,
			 clk_modules_hw_auto_non_essential,
			 clk_modules_explicit_en_non_essential,
			 0);

	/* Put camera module in no sleep mode */
	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
			MODULE_CLKCTRL_MODULEMODE_MASK,
			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
			MODULE_CLKCTRL_MODULEMODE_SHIFT);
}

void hw_data_init(void)
{
	u32 omap_rev = omap_revision();

	(*prcm) = &omap4_prcm;

	switch (omap_rev) {

	case OMAP4430_ES1_0:
	*dplls_data = &omap4430_dplls_es1;
	*omap_vcores = &omap4430_volts_es1;
	break;

	case OMAP4430_ES2_0:
	case OMAP4430_ES2_1:
	case OMAP4430_ES2_2:
	case OMAP4430_ES2_3:
	*dplls_data = &omap4430_dplls;
	*omap_vcores = &omap4430_volts;
	break;

	case OMAP4460_ES1_0:
	case OMAP4460_ES1_1:
	*dplls_data = &omap4460_dplls;
	*omap_vcores = &omap4460_volts;
	break;

	default:
		printf("\n INVALID OMAP REVISION ");
	}

	*ctrl = &omap4_ctrl;
}
Commit	Line	Data
01b753ff S	1	/*
	2	*
	3	* HW data initialization for OMAP4
	4	*
	5	* (C) Copyright 2013
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Sricharan R <r.sricharan@ti.com>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
01b753ff S	11	*/
	12	#include <common.h>
	13	#include <asm/arch/omap.h>
ee9447bf	14	#include <asm/arch/sys_proto.h>
01b753ff	15	#include <asm/omap_common.h>
af1d002f	16	#include <asm/arch/clock.h>
3fcdd4a5	17	#include <asm/omap_gpio.h>
ee9447bf	18	#include <asm/io.h>
01b753ff S	19
	20	struct prcm_regs const **prcm =
	21	(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
ee9447bf S	22	struct dplls const **dplls_data =
ee9447bf S	23	(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
3fcdd4a5 S	24	struct vcores_data const **omap_vcores =
3fcdd4a5 S	25	(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
c43c8339	26	struct omap_sys_ctrl_regs const **ctrl =
f92f2277	27	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
ee9447bf S	28
	29	/*
	30	* The M & N values in the following tables are created using the
	31	* following tool:
	32	* tools/omap/clocks_get_m_n.c
	33	* Please use this tool for creating the table for any new frequency.
	34	*/
	35
47abc3df S	36	/*
	37	* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
	38	* OMAP4460 OPP_NOM frequency
	39	*/
ee9447bf	40	static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
47abc3df S	41	{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	42	{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	43	{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	44	{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	45	{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	46	{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	47	{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	48	};
ee9447bf S	49
47abc3df S	50	/*
	51	* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
	52	* OMAP4430 OPP_TURBO frequency
	53	*/
ee9447bf	54	static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
47abc3df S	55	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	56	{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	57	{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	58	{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	59	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	60	{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	61	{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	62	};
ee9447bf S	63
47abc3df S	64	/*
	65	* dpll locked at 1200 MHz - MPU clk at 600 MHz
	66	* OMAP4430 OPP_NOM frequency
	67	*/
ee9447bf	68	static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
47abc3df S	69	{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	70	{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	71	{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	72	{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	73	{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	74	{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	75	{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	76	};
ee9447bf S	77
47abc3df	78	/* OMAP4460 OPP_NOM frequency */
ee9447bf	79	static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
47abc3df S	80	{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
	81	{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
	82	{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
	83	{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
	84	{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
	85	{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
	86	{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	87	};
ee9447bf S	88
47abc3df	89	/* OMAP4430 ES1 OPP_NOM frequency */
ee9447bf	90	static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
47abc3df S	91	{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
	92	{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
	93	{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
	94	{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
	95	{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
	96	{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
	97	{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	98	};
ee9447bf S	99
47abc3df	100	/* OMAP4430 ES2.X OPP_NOM frequency */
ee9447bf S	101	static const struct dpll_params
ee9447bf S	102	core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
47abc3df S	103	{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
	104	{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
	105	{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
	106	{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
	107	{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
	108	{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
	109	{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	110	};
	111
	112	static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
47abc3df S	113	{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
	114	{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
	115	{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
	116	{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
	117	{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
	118	{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
	119	{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	120	};
	121
	122	static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
47abc3df S	123	{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	124	{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	125	{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	126	{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	127	{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	128	{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	129	{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	130	};
	131
	132	/* ABE M & N values with sys_clk as source */
	133	static const struct dpll_params
	134	abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
47abc3df S	135	{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	136	{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	137	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	138	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	139	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	140	{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	141	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	142	};
	143
	144	/* ABE M & N values with 32K clock as source */
	145	static const struct dpll_params abe_dpll_params_32k_196608khz = {
47abc3df	146	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
ee9447bf S	147	};
	148
	149	static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
47abc3df S	150	{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	151	{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	152	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	153	{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	154	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	155	{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	156	{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	157	};
	158
	159	struct dplls omap4430_dplls_es1 = {
	160	.mpu = mpu_dpll_params_1200mhz,
	161	.core = core_dpll_params_es1_1524mhz,
	162	.per = per_dpll_params_1536mhz,
	163	.iva = iva_dpll_params_1862mhz,
	164	#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	165	.abe = abe_dpll_params_sysclk_196608khz,
	166	#else
	167	.abe = &abe_dpll_params_32k_196608khz,
	168	#endif
ea8eff1f LV	169	.usb = usb_dpll_params_1920mhz,
ea8eff1f LV	170	.ddr = NULL
ee9447bf S	171	};
	172
	173	struct dplls omap4430_dplls = {
47abc3df S	174	.mpu = mpu_dpll_params_1200mhz,
47abc3df S	175	.core = core_dpll_params_1600mhz,
ee9447bf S	176	.per = per_dpll_params_1536mhz,
	177	.iva = iva_dpll_params_1862mhz,
	178	#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	179	.abe = abe_dpll_params_sysclk_196608khz,
	180	#else
	181	.abe = &abe_dpll_params_32k_196608khz,
	182	#endif
ea8eff1f LV	183	.usb = usb_dpll_params_1920mhz,
ea8eff1f LV	184	.ddr = NULL
ee9447bf S	185	};
	186
	187	struct dplls omap4460_dplls = {
	188	.mpu = mpu_dpll_params_1400mhz,
	189	.core = core_dpll_params_1600mhz,
	190	.per = per_dpll_params_1536mhz,
	191	.iva = iva_dpll_params_1862mhz,
	192	#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	193	.abe = abe_dpll_params_sysclk_196608khz,
	194	#else
	195	.abe = &abe_dpll_params_32k_196608khz,
	196	#endif
ea8eff1f LV	197	.usb = usb_dpll_params_1920mhz,
ea8eff1f LV	198	.ddr = NULL
ee9447bf S	199	};
ee9447bf S	200
3fcdd4a5 S	201	struct pmic_data twl6030_4430es1 = {
3fcdd4a5 S	202	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
a1c8fb91	203	.step = 12660, /* 12.66 mV represented in uV */
3fcdd4a5 S	204	/* The code starts at 1 not 0 */
3fcdd4a5 S	205	.start_code = 1,
4ca94d81 LV	206	.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
	207	.pmic_bus_init = sri2c_init,
	208	.pmic_write = omap_vc_bypass_send_value,
3fcdd4a5 S	209	};
	210
	211	struct pmic_data twl6030 = {
	212	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
a1c8fb91	213	.step = 12660, /* 12.66 mV represented in uV */
3fcdd4a5 S	214	/* The code starts at 1 not 0 */
3fcdd4a5 S	215	.start_code = 1,
4ca94d81 LV	216	.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
	217	.pmic_bus_init = sri2c_init,
	218	.pmic_write = omap_vc_bypass_send_value,
3fcdd4a5 S	219	};
	220
	221	struct pmic_data tps62361 = {
	222	.base_offset = TPS62361_BASE_VOLT_MV,
	223	.step = 10000, /* 10 mV represented in uV */
	224	.start_code = 0,
	225	.gpio = TPS62361_VSEL0_GPIO,
4ca94d81 LV	226	.gpio_en = 1,
	227	.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
	228	.pmic_bus_init = sri2c_init,
	229	.pmic_write = omap_vc_bypass_send_value,
3fcdd4a5 S	230	};
	231
	232	struct vcores_data omap4430_volts_es1 = {
	233	.mpu.value = 1325,
	234	.mpu.addr = SMPS_REG_ADDR_VCORE1,
	235	.mpu.pmic = &twl6030_4430es1,
	236
	237	.core.value = 1200,
	238	.core.addr = SMPS_REG_ADDR_VCORE3,
	239	.core.pmic = &twl6030_4430es1,
	240
	241	.mm.value = 1200,
	242	.mm.addr = SMPS_REG_ADDR_VCORE2,
	243	.mm.pmic = &twl6030_4430es1,
	244	};
	245
	246	struct vcores_data omap4430_volts = {
	247	.mpu.value = 1325,
	248	.mpu.addr = SMPS_REG_ADDR_VCORE1,
	249	.mpu.pmic = &twl6030,
	250
	251	.core.value = 1200,
	252	.core.addr = SMPS_REG_ADDR_VCORE3,
	253	.core.pmic = &twl6030,
	254
	255	.mm.value = 1200,
	256	.mm.addr = SMPS_REG_ADDR_VCORE2,
	257	.mm.pmic = &twl6030,
	258	};
	259
	260	struct vcores_data omap4460_volts = {
	261	.mpu.value = 1203,
	262	.mpu.addr = TPS62361_REG_ADDR_SET1,
	263	.mpu.pmic = &tps62361,
	264
	265	.core.value = 1200,
	266	.core.addr = SMPS_REG_ADDR_VCORE1,
a1c8fb91	267	.core.pmic = &twl6030,
3fcdd4a5 S	268
	269	.mm.value = 1200,
	270	.mm.addr = SMPS_REG_ADDR_VCORE2,
a1c8fb91	271	.mm.pmic = &twl6030,
3fcdd4a5 S	272	};
3fcdd4a5 S	273
ee9447bf S	274	/*
	275	* Enable essential clock domains, modules and
	276	* do some additional special settings needed
	277	*/
	278	void enable_basic_clocks(void)
	279	{
	280	u32 const clk_domains_essential[] = {
	281	(*prcm)->cm_l4per_clkstctrl,
	282	(*prcm)->cm_l3init_clkstctrl,
	283	(*prcm)->cm_memif_clkstctrl,
	284	(*prcm)->cm_l4cfg_clkstctrl,
	285	0
	286	};
	287
	288	u32 const clk_modules_hw_auto_essential[] = {
d4e4129c	289	(*prcm)->cm_l3_gpmc_clkctrl,
ee9447bf S	290	(*prcm)->cm_memif_emif_1_clkctrl,
	291	(*prcm)->cm_memif_emif_2_clkctrl,
	292	(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
	293	(*prcm)->cm_wkup_gpio1_clkctrl,
	294	(*prcm)->cm_l4per_gpio2_clkctrl,
	295	(*prcm)->cm_l4per_gpio3_clkctrl,
	296	(*prcm)->cm_l4per_gpio4_clkctrl,
	297	(*prcm)->cm_l4per_gpio5_clkctrl,
	298	(*prcm)->cm_l4per_gpio6_clkctrl,
	299	0
	300	};
	301
	302	u32 const clk_modules_explicit_en_essential[] = {
	303	(*prcm)->cm_wkup_gptimer1_clkctrl,
	304	(*prcm)->cm_l3init_hsmmc1_clkctrl,
	305	(*prcm)->cm_l3init_hsmmc2_clkctrl,
	306	(*prcm)->cm_l4per_gptimer2_clkctrl,
	307	(*prcm)->cm_wkup_wdtimer2_clkctrl,
	308	(*prcm)->cm_l4per_uart3_clkctrl,
	309	0
	310	};
	311
	312	/* Enable optional additional functional clock for GPIO4 */
	313	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
	314	GPIO4_CLKCTRL_OPTFCLKEN_MASK);
	315
	316	/* Enable 96 MHz clock for MMC1 & MMC2 */
	317	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
	318	HSMMC_CLKCTRL_CLKSEL_MASK);
	319	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
	320	HSMMC_CLKCTRL_CLKSEL_MASK);
	321
	322	/* Select 32KHz clock as the source of GPTIMER1 */
	323	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
	324	GPTIMER1_CLKCTRL_CLKSEL_MASK);
	325
	326	/* Enable optional 48M functional clock for USB PHY */
	327	setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
	328	USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
	329
	330	do_enable_clocks(clk_domains_essential,
	331	clk_modules_hw_auto_essential,
	332	clk_modules_explicit_en_essential,
	333	1);
	334	}
	335
	336	void enable_basic_uboot_clocks(void)
	337	{
	338	u32 const clk_domains_essential[] = {
	339	0
	340	};
	341
	342	u32 const clk_modules_hw_auto_essential[] = {
	343	(*prcm)->cm_l3init_hsusbotg_clkctrl,
	344	(*prcm)->cm_l3init_usbphy_clkctrl,
	345	(*prcm)->cm_l3init_usbphy_clkctrl,
	346	(*prcm)->cm_clksel_usb_60mhz,
	347	(*prcm)->cm_l3init_hsusbtll_clkctrl,
	348	0
	349	};
	350
	351	u32 const clk_modules_explicit_en_essential[] = {
	352	(*prcm)->cm_l4per_mcspi1_clkctrl,
	353	(*prcm)->cm_l4per_i2c1_clkctrl,
354	(*prcm)->cm_l4per_i2c2_clkctrl,
355	(*prcm)->cm_l4per_i2c3_clkctrl,
356	(*prcm)->cm_l4per_i2c4_clkctrl,
357	(*prcm)->cm_l3init_hsusbhost_clkctrl,
358	0
359	};
360
361	do_enable_clocks(clk_domains_essential,
362	clk_modules_hw_auto_essential,
363	clk_modules_explicit_en_essential,
364	1);
365	}
366
367	/*
368	* Enable non-essential clock domains, modules and
369	* do some additional special settings needed
370	*/
371	void enable_non_essential_clocks(void)
372	{
373	u32 const clk_domains_non_essential[] = {
374	(*prcm)->cm_mpu_m3_clkstctrl,
375	(*prcm)->cm_ivahd_clkstctrl,
376	(*prcm)->cm_dsp_clkstctrl,
377	(*prcm)->cm_dss_clkstctrl,
378	(*prcm)->cm_sgx_clkstctrl,
379	(*prcm)->cm1_abe_clkstctrl,
380	(*prcm)->cm_c2c_clkstctrl,
381	(*prcm)->cm_cam_clkstctrl,
382	(*prcm)->cm_dss_clkstctrl,
383	(*prcm)->cm_sdma_clkstctrl,
384	0
385	};
386
387	u32 const clk_modules_hw_auto_non_essential[] = {
388	(*prcm)->cm_l3instr_l3_3_clkctrl,
389	(*prcm)->cm_l3instr_l3_instr_clkctrl,
390	(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
391	(*prcm)->cm_l3init_hsi_clkctrl,
392	0
393	};
394
395	u32 const clk_modules_explicit_en_non_essential[] = {
396	(*prcm)->cm1_abe_aess_clkctrl,
397	(*prcm)->cm1_abe_pdm_clkctrl,
398	(*prcm)->cm1_abe_dmic_clkctrl,
399	(*prcm)->cm1_abe_mcasp_clkctrl,
400	(*prcm)->cm1_abe_mcbsp1_clkctrl,
401	(*prcm)->cm1_abe_mcbsp2_clkctrl,
402	(*prcm)->cm1_abe_mcbsp3_clkctrl,
403	(*prcm)->cm1_abe_slimbus_clkctrl,
404	(*prcm)->cm1_abe_timer5_clkctrl,
405	(*prcm)->cm1_abe_timer6_clkctrl,
406	(*prcm)->cm1_abe_timer7_clkctrl,
407	(*prcm)->cm1_abe_timer8_clkctrl,
408	(*prcm)->cm1_abe_wdt3_clkctrl,
409	(*prcm)->cm_l4per_gptimer9_clkctrl,
410	(*prcm)->cm_l4per_gptimer10_clkctrl,
411	(*prcm)->cm_l4per_gptimer11_clkctrl,
412	(*prcm)->cm_l4per_gptimer3_clkctrl,
413	(*prcm)->cm_l4per_gptimer4_clkctrl,
414	(*prcm)->cm_l4per_hdq1w_clkctrl,
415	(*prcm)->cm_l4per_mcbsp4_clkctrl,
416	(*prcm)->cm_l4per_mcspi2_clkctrl,
417	(*prcm)->cm_l4per_mcspi3_clkctrl,
418	(*prcm)->cm_l4per_mcspi4_clkctrl,
419	(*prcm)->cm_l4per_mmcsd3_clkctrl,
420	(*prcm)->cm_l4per_mmcsd4_clkctrl,
421	(*prcm)->cm_l4per_mmcsd5_clkctrl,
422	(*prcm)->cm_l4per_uart1_clkctrl,
423	(*prcm)->cm_l4per_uart2_clkctrl,
424	(*prcm)->cm_l4per_uart4_clkctrl,
425	(*prcm)->cm_wkup_keyboard_clkctrl,
426	(*prcm)->cm_wkup_wdtimer2_clkctrl,
427	(*prcm)->cm_cam_iss_clkctrl,
428	(*prcm)->cm_cam_fdif_clkctrl,
429	(*prcm)->cm_dss_dss_clkctrl,
430	(*prcm)->cm_sgx_sgx_clkctrl,
431	0
432	};
433
434	/* Enable optional functional clock for ISS */
435	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
436
437	/* Enable all optional functional clocks of DSS */
438	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
439
440	do_enable_clocks(clk_domains_non_essential,
441	clk_modules_hw_auto_non_essential,
442	clk_modules_explicit_en_non_essential,
443	0);
444
445	/* Put camera module in no sleep mode */
446	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
447	MODULE_CLKCTRL_MODULEMODE_MASK,
448	CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
449	MODULE_CLKCTRL_MODULEMODE_SHIFT);
450	}
01b753ff S	451
	452	void hw_data_init(void)
	453	{
ee9447bf S	454	u32 omap_rev = omap_revision();
	455
	456	(*prcm) = &omap4_prcm;
	457
	458	switch (omap_rev) {
	459
	460	case OMAP4430_ES1_0:
	461	*dplls_data = &omap4430_dplls_es1;
3fcdd4a5	462	*omap_vcores = &omap4430_volts_es1;
ee9447bf S	463	break;
	464
	465	case OMAP4430_ES2_0:
	466	case OMAP4430_ES2_1:
	467	case OMAP4430_ES2_2:
	468	case OMAP4430_ES2_3:
	469	*dplls_data = &omap4430_dplls;
3fcdd4a5	470	*omap_vcores = &omap4430_volts;
ee9447bf S	471	break;
	472
	473	case OMAP4460_ES1_0:
	474	case OMAP4460_ES1_1:
	475	*dplls_data = &omap4460_dplls;
3fcdd4a5	476	*omap_vcores = &omap4460_volts;
ee9447bf S	477	break;
	478
	479	default:
	480	printf("\n INVALID OMAP REVISION ");
	481	}
	482
c43c8339	483	*ctrl = &omap4_ctrl;
01b753ff	484	}