[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap4 / hwinit.c

/*
 *
 * Common functions for OMAP4 based boards
 *
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *	Aneesh V	<aneesh@ti.com>
 *	Steve Sakoman	<steve@sakoman.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/emif.h>
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>

DECLARE_GLOBAL_DATA_PTR;

u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;

static const struct gpio_bank gpio_bank_44xx[6] = {
	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;

#ifdef CONFIG_SPL_BUILD
/*
 * Some tuning of IOs for optimal power and performance
 */
void do_io_settings(void)
{
	u32 lpddr2io;

	u32 omap4_rev = omap_revision();

	if (omap4_rev == OMAP4430_ES1_0)
		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
	else if (omap4_rev == OMAP4430_ES2_0)
		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
	else
		lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;

	/* EMIF1 */
	writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
	writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
	/* No pull for GR10 as per hw team's recommendation */
	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
		(*ctrl)->control_lpddr2io1_2);
	writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);

	/* EMIF2 */
	writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
	writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
	/* No pull for GR10 as per hw team's recommendation */
	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
		(*ctrl)->control_lpddr2io2_2);
	writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);

	/*
	 * Some of these settings (TRIM values) come from eFuse and are
	 * in turn programmed in the eFuse at manufacturing time after
	 * calibration of the device. Do the software over-ride only if
	 * the device is not correctly trimmed
	 */
	if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {

		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
			(*ctrl)->control_ldosram_iva_voltage_ctrl);

		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
			(*ctrl)->control_ldosram_mpu_voltage_ctrl);

		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
			(*ctrl)->control_ldosram_core_voltage_ctrl);
	}

	/*
	 * Over-ride the register
	 *	i. unconditionally for all 4430
	 *	ii. only if un-trimmed for 4460
	 */
	if (!readl((*ctrl)->control_efuse_1))
		writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);

	if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
		writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
}
#endif /* CONFIG_SPL_BUILD */

/* dummy fuction for omap4 */
void config_data_eye_leveling_samples(u32 emif_base)
{
}

void init_omap_revision(void)
{
	/*
	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
	 * Also, ES1 and ES2 have different ARM revisions
	 * So use ARM revision for identification
	 */
	unsigned int arm_rev = cortex_rev();

	switch (arm_rev) {
	case MIDR_CORTEX_A9_R0P1:
		*omap_si_rev = OMAP4430_ES1_0;
		break;
	case MIDR_CORTEX_A9_R1P2:
		switch (readl(CONTROL_ID_CODE)) {
		case OMAP4_CONTROL_ID_CODE_ES2_0:
			*omap_si_rev = OMAP4430_ES2_0;
			break;
		case OMAP4_CONTROL_ID_CODE_ES2_1:
			*omap_si_rev = OMAP4430_ES2_1;
			break;
		case OMAP4_CONTROL_ID_CODE_ES2_2:
			*omap_si_rev = OMAP4430_ES2_2;
			break;
		default:
			*omap_si_rev = OMAP4430_ES2_0;
			break;
		}
		break;
	case MIDR_CORTEX_A9_R1P3:
		*omap_si_rev = OMAP4430_ES2_3;
		break;
	case MIDR_CORTEX_A9_R2P10:
		switch (readl(CONTROL_ID_CODE)) {
		case OMAP4460_CONTROL_ID_CODE_ES1_1:
			*omap_si_rev = OMAP4460_ES1_1;
			break;
		case OMAP4460_CONTROL_ID_CODE_ES1_0:
		default:
			*omap_si_rev = OMAP4460_ES1_0;
			break;
		}
		break;
	default:
		*omap_si_rev = OMAP4430_SILICON_ID_INVALID;
		break;
	}
}

#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
	set_pl310_ctrl_reg(1);
}

void v7_outer_cache_disable(void)
{
	set_pl310_ctrl_reg(0);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
508a58fa S	1	/*
	2	*
	3	* Common functions for OMAP4 based boards
	4	*
	5	* (C) Copyright 2010
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Aneesh V <aneesh@ti.com>
	10	* Steve Sakoman <steve@sakoman.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
508a58fa S	13	*/
	14	#include <common.h>
	15	#include <asm/armv7.h>
	16	#include <asm/arch/cpu.h>
	17	#include <asm/arch/sys_proto.h>
	18	#include <asm/sizes.h>
bb772a59	19	#include <asm/emif.h>
508a58fa	20	#include <asm/arch/gpio.h>
f92f2277	21	#include <asm/omap_common.h>
508a58fa S	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
f92f2277	25	u32 const omap_si_rev = (u32 )OMAP_SRAM_SCRATCH_OMAP_REV;
508a58fa S	26
	27	static const struct gpio_bank gpio_bank_44xx[6] = {
	28	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
	29	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
	30	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
	31	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
	32	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
	33	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
	34	};
	35
	36	const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
	37
	38	#ifdef CONFIG_SPL_BUILD
	39	/*
	40	* Some tuning of IOs for optimal power and performance
	41	*/
	42	void do_io_settings(void)
	43	{
	44	u32 lpddr2io;
508a58fa S	45
	46	u32 omap4_rev = omap_revision();
	47
	48	if (omap4_rev == OMAP4430_ES1_0)
	49	lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
	50	else if (omap4_rev == OMAP4430_ES2_0)
	51	lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
	52	else
	53	lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
	54
	55	/* EMIF1 */
c43c8339 LV	56	writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
c43c8339 LV	57	writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
508a58fa S	58	/* No pull for GR10 as per hw team's recommendation */
508a58fa S	59	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
c43c8339 LV	60	(*ctrl)->control_lpddr2io1_2);
c43c8339 LV	61	writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
508a58fa S	62
508a58fa S	63	/* EMIF2 */
c43c8339 LV	64	writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
c43c8339 LV	65	writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
508a58fa S	66	/* No pull for GR10 as per hw team's recommendation */
508a58fa S	67	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
c43c8339 LV	68	(*ctrl)->control_lpddr2io2_2);
c43c8339 LV	69	writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
508a58fa S	70
	71	/*
	72	* Some of these settings (TRIM values) come from eFuse and are
	73	* in turn programmed in the eFuse at manufacturing time after
	74	* calibration of the device. Do the software over-ride only if
	75	* the device is not correctly trimmed
	76	*/
c43c8339	77	if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
508a58fa S	78
508a58fa S	79	writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
c43c8339	80	(*ctrl)->control_ldosram_iva_voltage_ctrl);
508a58fa S	81
508a58fa S	82	writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
c43c8339	83	(*ctrl)->control_ldosram_mpu_voltage_ctrl);
508a58fa S	84
508a58fa S	85	writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
c43c8339	86	(*ctrl)->control_ldosram_core_voltage_ctrl);
508a58fa S	87	}
508a58fa S	88
23e9f072 A	89	/*
	90	* Over-ride the register
	91	* i. unconditionally for all 4430
	92	* ii. only if un-trimmed for 4460
	93	*/
c43c8339 LV	94	if (!readl((*ctrl)->control_efuse_1))
c43c8339 LV	95	writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
508a58fa	96
c43c8339 LV	97	if ((omap4_rev < OMAP4460_ES1_0) \|\| !readl((*ctrl)->control_efuse_2))
c43c8339 LV	98	writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
508a58fa	99	}
f281f299	100	#endif /* CONFIG_SPL_BUILD */
508a58fa	101
784ab7c5 LV	102	/* dummy fuction for omap4 */
	103	void config_data_eye_leveling_samples(u32 emif_base)
	104	{
	105	}
	106
508a58fa S	107	void init_omap_revision(void)
	108	{
	109	/*
	110	* For some of the ES2/ES1 boards ID_CODE is not reliable:
	111	* Also, ES1 and ES2 have different ARM revisions
	112	* So use ARM revision for identification
	113	*/
	114	unsigned int arm_rev = cortex_rev();
	115
	116	switch (arm_rev) {
	117	case MIDR_CORTEX_A9_R0P1:
087189fb	118	*omap_si_rev = OMAP4430_ES1_0;
508a58fa S	119	break;
	120	case MIDR_CORTEX_A9_R1P2:
	121	switch (readl(CONTROL_ID_CODE)) {
	122	case OMAP4_CONTROL_ID_CODE_ES2_0:
087189fb	123	*omap_si_rev = OMAP4430_ES2_0;
508a58fa S	124	break;
508a58fa S	125	case OMAP4_CONTROL_ID_CODE_ES2_1:
087189fb	126	*omap_si_rev = OMAP4430_ES2_1;
508a58fa S	127	break;
508a58fa S	128	case OMAP4_CONTROL_ID_CODE_ES2_2:
087189fb	129	*omap_si_rev = OMAP4430_ES2_2;
508a58fa S	130	break;
508a58fa S	131	default:
087189fb	132	*omap_si_rev = OMAP4430_ES2_0;
508a58fa S	133	break;
	134	}
	135	break;
	136	case MIDR_CORTEX_A9_R1P3:
087189fb	137	*omap_si_rev = OMAP4430_ES2_3;
508a58fa S	138	break;
508a58fa S	139	case MIDR_CORTEX_A9_R2P10:
9404758e A	140	switch (readl(CONTROL_ID_CODE)) {
9404758e A	141	case OMAP4460_CONTROL_ID_CODE_ES1_1:
087189fb	142	*omap_si_rev = OMAP4460_ES1_1;
9404758e A	143	break;
	144	case OMAP4460_CONTROL_ID_CODE_ES1_0:
	145	default:
087189fb	146	*omap_si_rev = OMAP4460_ES1_0;
9404758e A	147	break;
9404758e A	148	}
508a58fa S	149	break;
508a58fa S	150	default:
087189fb	151	*omap_si_rev = OMAP4430_SILICON_ID_INVALID;
508a58fa S	152	break;
	153	}
	154	}
	155
	156	#ifndef CONFIG_SYS_L2CACHE_OFF
	157	void v7_outer_cache_enable(void)
	158	{
	159	set_pl310_ctrl_reg(1);
	160	}
	161
	162	void v7_outer_cache_disable(void)
	163	{
	164	set_pl310_ctrl_reg(0);
	165	}
f281f299	166	#endif /* !CONFIG_SYS_L2CACHE_OFF */