[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / hw_data.c

/*
 *
 * HW data initialization for OMAP5
 *
 * (C) Copyright 2013
 * Texas Instruments, <www.ti.com>
 *
 * Sricharan R <r.sricharan@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
#include <asm/emif.h>

struct prcm_regs const **prcm =
			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
			(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
	(struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;

/* OPP HIGH FREQUENCY for ES2.0 */
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
	{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
};

/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
	{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
};

/* OPP NOM FREQUENCY for ES1.0 */
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
};

/* OPP LOW FREQUENCY for ES1.0 */
static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
	{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
};

/* OPP LOW FREQUENCY for ES2.0 */
static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
	{499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
};

static const struct dpll_params
			core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
	{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 16.8 MHz */
	{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 19.2 MHz */
	{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}		/* 38.4 MHz */
};

static const struct dpll_params
			core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
	{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 16.8 MHz */
	{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 19.2 MHz */
	{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}		/* 38.4 MHz */
};

static const struct dpll_params
			core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
	{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 16.8 MHz */
	{277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 19.2 MHz */
	{368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}		/* 38.4 MHz */
};

static const struct dpll_params
			core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
	{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 16.8 MHz */
	{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 19.2 MHz */
	{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}		/* 38.4 MHz */
};

static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
	{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
	{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
	{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */
};

static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
	{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
	{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
	{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */
};

static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
	{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
	{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
	{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
};

/* ABE M & N values with sys_clk as source */
static const struct dpll_params
		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
	{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
};

/* ABE M & N values with 32K clock as source */
static const struct dpll_params abe_dpll_params_32k_196608khz = {
	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};

static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
	{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
	{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
	{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
};

struct dplls omap5_dplls_es1 = {
	.mpu = mpu_dpll_params_800mhz,
	.core = core_dpll_params_2128mhz_ddr532,
	.per = per_dpll_params_768mhz,
	.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	.abe = abe_dpll_params_sysclk_196608khz,
#else
	.abe = &abe_dpll_params_32k_196608khz,
#endif
	.usb = usb_dpll_params_1920mhz
};

struct dplls omap5_dplls_es2 = {
	.mpu = mpu_dpll_params_1100mhz,
	.core = core_dpll_params_2128mhz_ddr532_es2,
	.per = per_dpll_params_768mhz_es2,
	.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	.abe = abe_dpll_params_sysclk_196608khz,
#else
	.abe = &abe_dpll_params_32k_196608khz,
#endif
	.usb = usb_dpll_params_1920mhz
};

struct pmic_data palmas = {
	.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
	.step = 10000, /* 10 mV represented in uV */
	/*
	 * Offset codes 1-6 all give the base voltage in Palmas
	 * Offset code 0 switches OFF the SMPS
	 */
	.start_code = 6,
};

struct vcores_data omap5430_volts = {
	.mpu.value = VDD_MPU,
	.mpu.addr = SMPS_REG_ADDR_12_MPU,
	.mpu.pmic = &palmas,

	.core.value = VDD_CORE,
	.core.addr = SMPS_REG_ADDR_8_CORE,
	.core.pmic = &palmas,

	.mm.value = VDD_MM,
	.mm.addr = SMPS_REG_ADDR_45_IVA,
	.mm.pmic = &palmas,
};

struct vcores_data omap5430_volts_es2 = {
	.mpu.value = VDD_MPU_ES2,
	.mpu.addr = SMPS_REG_ADDR_12_MPU,
	.mpu.pmic = &palmas,

	.core.value = VDD_CORE_ES2,
	.core.addr = SMPS_REG_ADDR_8_CORE,
	.core.pmic = &palmas,

	.mm.value = VDD_MM_ES2,
	.mm.addr = SMPS_REG_ADDR_45_IVA,
	.mm.pmic = &palmas,
};

/*
 * Enable essential clock domains, modules and
 * do some additional special settings needed
 */
void enable_basic_clocks(void)
{
	u32 const clk_domains_essential[] = {
		(*prcm)->cm_l4per_clkstctrl,
		(*prcm)->cm_l3init_clkstctrl,
		(*prcm)->cm_memif_clkstctrl,
		(*prcm)->cm_l4cfg_clkstctrl,
		0
	};

	u32 const clk_modules_hw_auto_essential[] = {
		(*prcm)->cm_l3_gpmc_clkctrl,
		(*prcm)->cm_memif_emif_1_clkctrl,
		(*prcm)->cm_memif_emif_2_clkctrl,
		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
		(*prcm)->cm_wkup_gpio1_clkctrl,
		(*prcm)->cm_l4per_gpio2_clkctrl,
		(*prcm)->cm_l4per_gpio3_clkctrl,
		(*prcm)->cm_l4per_gpio4_clkctrl,
		(*prcm)->cm_l4per_gpio5_clkctrl,
		(*prcm)->cm_l4per_gpio6_clkctrl,
		0
	};

	u32 const clk_modules_explicit_en_essential[] = {
		(*prcm)->cm_wkup_gptimer1_clkctrl,
		(*prcm)->cm_l3init_hsmmc1_clkctrl,
		(*prcm)->cm_l3init_hsmmc2_clkctrl,
		(*prcm)->cm_l4per_gptimer2_clkctrl,
		(*prcm)->cm_wkup_wdtimer2_clkctrl,
		(*prcm)->cm_l4per_uart3_clkctrl,
		(*prcm)->cm_l4per_i2c1_clkctrl,
		0
	};

	/* Enable optional additional functional clock for GPIO4 */
	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
			GPIO4_CLKCTRL_OPTFCLKEN_MASK);

	/* Enable 96 MHz clock for MMC1 & MMC2 */
	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
			HSMMC_CLKCTRL_CLKSEL_MASK);
	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
			HSMMC_CLKCTRL_CLKSEL_MASK);

	/* Set the correct clock dividers for mmc */
	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);

	/* Select 32KHz clock as the source of GPTIMER1 */
	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
			GPTIMER1_CLKCTRL_CLKSEL_MASK);

	do_enable_clocks(clk_domains_essential,
			 clk_modules_hw_auto_essential,
			 clk_modules_explicit_en_essential,
			 1);

	/* Select 384Mhz for GPU as its the POR for ES1.0 */
	setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
			CLKSEL_GPU_HYD_GCLK_MASK);
	setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
			CLKSEL_GPU_CORE_GCLK_MASK);

	/* Enable SCRM OPT clocks for PER and CORE dpll */
	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
			OPTFCLKEN_SCRM_PER_MASK);
	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
			OPTFCLKEN_SCRM_CORE_MASK);
}

void enable_basic_uboot_clocks(void)
{
	u32 const clk_domains_essential[] = {
		0
	};

	u32 const clk_modules_hw_auto_essential[] = {
		0
	};

	u32 const clk_modules_explicit_en_essential[] = {
		(*prcm)->cm_l4per_mcspi1_clkctrl,
		(*prcm)->cm_l4per_i2c2_clkctrl,
		(*prcm)->cm_l4per_i2c3_clkctrl,
		(*prcm)->cm_l4per_i2c4_clkctrl,
		(*prcm)->cm_l3init_hsusbtll_clkctrl,
		(*prcm)->cm_l3init_hsusbhost_clkctrl,
		(*prcm)->cm_l3init_fsusb_clkctrl,
		0
	};

	do_enable_clocks(clk_domains_essential,
			 clk_modules_hw_auto_essential,
			 clk_modules_explicit_en_essential,
			 1);
}

/*
 * Enable non-essential clock domains, modules and
 * do some additional special settings needed
 */
void enable_non_essential_clocks(void)
{
	u32 const clk_domains_non_essential[] = {
		(*prcm)->cm_mpu_m3_clkstctrl,
		(*prcm)->cm_ivahd_clkstctrl,
		(*prcm)->cm_dsp_clkstctrl,
		(*prcm)->cm_dss_clkstctrl,
		(*prcm)->cm_sgx_clkstctrl,
		(*prcm)->cm1_abe_clkstctrl,
		(*prcm)->cm_c2c_clkstctrl,
		(*prcm)->cm_cam_clkstctrl,
		(*prcm)->cm_dss_clkstctrl,
		(*prcm)->cm_sdma_clkstctrl,
		0
	};

	u32 const clk_modules_hw_auto_non_essential[] = {
		(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
		(*prcm)->cm_ivahd_ivahd_clkctrl,
		(*prcm)->cm_ivahd_sl2_clkctrl,
		(*prcm)->cm_dsp_dsp_clkctrl,
		(*prcm)->cm_l3instr_l3_3_clkctrl,
		(*prcm)->cm_l3instr_l3_instr_clkctrl,
		(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
		(*prcm)->cm_l3init_hsi_clkctrl,
		(*prcm)->cm_l4per_hdq1w_clkctrl,
		0
	};

	u32 const clk_modules_explicit_en_non_essential[] = {
		(*prcm)->cm1_abe_aess_clkctrl,
		(*prcm)->cm1_abe_pdm_clkctrl,
		(*prcm)->cm1_abe_dmic_clkctrl,
		(*prcm)->cm1_abe_mcasp_clkctrl,
		(*prcm)->cm1_abe_mcbsp1_clkctrl,
		(*prcm)->cm1_abe_mcbsp2_clkctrl,
		(*prcm)->cm1_abe_mcbsp3_clkctrl,
		(*prcm)->cm1_abe_slimbus_clkctrl,
		(*prcm)->cm1_abe_timer5_clkctrl,
		(*prcm)->cm1_abe_timer6_clkctrl,
		(*prcm)->cm1_abe_timer7_clkctrl,
		(*prcm)->cm1_abe_timer8_clkctrl,
		(*prcm)->cm1_abe_wdt3_clkctrl,
		(*prcm)->cm_l4per_gptimer9_clkctrl,
		(*prcm)->cm_l4per_gptimer10_clkctrl,
		(*prcm)->cm_l4per_gptimer11_clkctrl,
		(*prcm)->cm_l4per_gptimer3_clkctrl,
		(*prcm)->cm_l4per_gptimer4_clkctrl,
		(*prcm)->cm_l4per_mcspi2_clkctrl,
		(*prcm)->cm_l4per_mcspi3_clkctrl,
		(*prcm)->cm_l4per_mcspi4_clkctrl,
		(*prcm)->cm_l4per_mmcsd3_clkctrl,
		(*prcm)->cm_l4per_mmcsd4_clkctrl,
		(*prcm)->cm_l4per_mmcsd5_clkctrl,
		(*prcm)->cm_l4per_uart1_clkctrl,
		(*prcm)->cm_l4per_uart2_clkctrl,
		(*prcm)->cm_l4per_uart4_clkctrl,
		(*prcm)->cm_wkup_keyboard_clkctrl,
		(*prcm)->cm_wkup_wdtimer2_clkctrl,
		(*prcm)->cm_cam_iss_clkctrl,
		(*prcm)->cm_cam_fdif_clkctrl,
		(*prcm)->cm_dss_dss_clkctrl,
		(*prcm)->cm_sgx_sgx_clkctrl,
		0
	};

	/* Enable optional functional clock for ISS */
	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);

	/* Enable all optional functional clocks of DSS */
	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);

	do_enable_clocks(clk_domains_non_essential,
			 clk_modules_hw_auto_non_essential,
			 clk_modules_explicit_en_non_essential,
			 0);

	/* Put camera module in no sleep mode */
	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
			MODULE_CLKCTRL_MODULEMODE_MASK,
			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
			MODULE_CLKCTRL_MODULEMODE_SHIFT);
}

const struct ctrl_ioregs ioregs_omap5430 = {
	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
	.ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
	.ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
	.ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
};

const struct ctrl_ioregs ioregs_omap5432_es1 = {
	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
	.ctrl_lpddr2ch = 0x0,
	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};

const struct ctrl_ioregs ioregs_omap5432_es2 = {
	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
	.ctrl_lpddr2ch = 0x0,
	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};

void hw_data_init(void)
{
	u32 omap_rev = omap_revision();

	switch (omap_rev) {

	case OMAP5430_ES1_0:
	case OMAP5432_ES1_0:
	*prcm = &omap5_es1_prcm;
	*dplls_data = &omap5_dplls_es1;
	*omap_vcores = &omap5430_volts;
	break;

	case OMAP5430_ES2_0:
	case OMAP5432_ES2_0:
	*prcm = &omap5_es2_prcm;
	*dplls_data = &omap5_dplls_es2;
	*omap_vcores = &omap5430_volts_es2;
	break;

	case DRA752_ES1_0:
	*prcm = &dra7xx_prcm;
	break;

	default:
		printf("\n INVALID OMAP REVISION ");
	}

	*ctrl = &omap5_ctrl;
}

void get_ioregs(const struct ctrl_ioregs **regs)
{
	u32 omap_rev = omap_revision();

	switch (omap_rev) {
	case OMAP5430_ES1_0:
	case OMAP5430_ES2_0:
		*regs = &ioregs_omap5430;
	break;
	case OMAP5432_ES1_0:
		*regs = &ioregs_omap5432_es1;
	break;
	case OMAP5432_ES2_0:
		*regs = &ioregs_omap5432_es2;
	break;

	default:
		printf("\n INVALID OMAP REVISION ");
	}
}
Commit	Line	Data
01b753ff S	1	/*
	2	*
	3	* HW data initialization for OMAP5
	4	*
	5	* (C) Copyright 2013
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Sricharan R <r.sricharan@ti.com>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28	#include <common.h>
	29	#include <asm/arch/omap.h>
ee9447bf	30	#include <asm/arch/sys_proto.h>
01b753ff	31	#include <asm/omap_common.h>
ee9447bf	32	#include <asm/arch/clocks.h>
3fcdd4a5	33	#include <asm/omap_gpio.h>
ee9447bf	34	#include <asm/io.h>
ef1697e9	35	#include <asm/emif.h>
01b753ff S	36
	37	struct prcm_regs const **prcm =
	38	(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
ee9447bf S	39	struct dplls const **dplls_data =
ee9447bf S	40	(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
3fcdd4a5 S	41	struct vcores_data const **omap_vcores =
3fcdd4a5 S	42	(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
c43c8339 LV	43	struct omap_sys_ctrl_regs const **ctrl =
c43c8339 LV	44	(struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
ee9447bf	45
47abc3df	46	/* OPP HIGH FREQUENCY for ES2.0 */
ee9447bf	47	static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
47abc3df S	48	{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	49	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	50	{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	51	{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	52	{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	53	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	54	{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	55	};
ee9447bf S	56
47abc3df	57	/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
ee9447bf	58	static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
47abc3df S	59	{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	60	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	61	{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	62	{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	63	{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	64	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	65	{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	66	};
ee9447bf S	67
47abc3df	68	/* OPP NOM FREQUENCY for ES1.0 */
ee9447bf	69	static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
47abc3df S	70	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	71	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	72	{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	73	{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	74	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	75	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	76	{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	77	};
ee9447bf S	78
47abc3df	79	/* OPP LOW FREQUENCY for ES1.0 */
ee9447bf	80	static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
47abc3df S	81	{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	82	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	83	{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	84	{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	85	{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	86	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	87	{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	88	};
ee9447bf S	89
47abc3df S	90	/* OPP LOW FREQUENCY for ES2.0 */
	91	static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
	92	{499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	93	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	94	{297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	95	{493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	96	{499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	97	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	98	{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	99	};
	100
	101	static const struct dpll_params
	102	core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
47abc3df S	103	{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
	104	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	105	{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
	106	{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
	107	{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
	108	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	109	{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
	110	};
	111
	112	static const struct dpll_params
	113	core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
	114	{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
	115	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	116	{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
	117	{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
	118	{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
	119	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	120	{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
ee9447bf S	121	};
	122
	123	static const struct dpll_params
	124	core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
47abc3df S	125	{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
	126	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	127	{443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
	128	{277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
	129	{368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
	130	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	131	{277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
	132	};
	133
	134	static const struct dpll_params
	135	core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
	136	{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
	137	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	138	{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
	139	{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
	140	{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
	141	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	142	{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
ee9447bf S	143	};
	144
	145	static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
47abc3df S	146	{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
	147	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	148	{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
	149	{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
	150	{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
	151	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	152	{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
	153	};
	154
	155	static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
	156	{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
	157	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	158	{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
	159	{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
	160	{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
	161	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	162	{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	163	};
	164
	165	static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
47abc3df S	166	{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	167	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	168	{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	169	{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	170	{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	171	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	172	{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	173	};
	174
	175	/* ABE M & N values with sys_clk as source */
	176	static const struct dpll_params
	177	abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
47abc3df S	178	{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	179	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	180	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	181	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	182	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	183	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	184	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	185	};
	186
	187	/* ABE M & N values with 32K clock as source */
	188	static const struct dpll_params abe_dpll_params_32k_196608khz = {
47abc3df	189	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
ee9447bf S	190	};
	191
	192	static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
47abc3df S	193	{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
	194	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
	195	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
	196	{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
	197	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
	198	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
	199	{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf S	200	};
	201
	202	struct dplls omap5_dplls_es1 = {
	203	.mpu = mpu_dpll_params_800mhz,
	204	.core = core_dpll_params_2128mhz_ddr532,
	205	.per = per_dpll_params_768mhz,
	206	.iva = iva_dpll_params_2330mhz,
	207	#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	208	.abe = abe_dpll_params_sysclk_196608khz,
	209	#else
	210	.abe = &abe_dpll_params_32k_196608khz,
	211	#endif
	212	.usb = usb_dpll_params_1920mhz
	213	};
	214
47abc3df S	215	struct dplls omap5_dplls_es2 = {
	216	.mpu = mpu_dpll_params_1100mhz,
	217	.core = core_dpll_params_2128mhz_ddr532_es2,
	218	.per = per_dpll_params_768mhz_es2,
	219	.iva = iva_dpll_params_2330mhz,
	220	#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
	221	.abe = abe_dpll_params_sysclk_196608khz,
	222	#else
	223	.abe = &abe_dpll_params_32k_196608khz,
	224	#endif
	225	.usb = usb_dpll_params_1920mhz
	226	};
	227
3fcdd4a5 S	228	struct pmic_data palmas = {
	229	.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
	230	.step = 10000, /* 10 mV represented in uV */
	231	/*
	232	* Offset codes 1-6 all give the base voltage in Palmas
	233	* Offset code 0 switches OFF the SMPS
	234	*/
	235	.start_code = 6,
	236	};
	237
	238	struct vcores_data omap5430_volts = {
	239	.mpu.value = VDD_MPU,
	240	.mpu.addr = SMPS_REG_ADDR_12_MPU,
	241	.mpu.pmic = &palmas,
	242
	243	.core.value = VDD_CORE,
	244	.core.addr = SMPS_REG_ADDR_8_CORE,
	245	.core.pmic = &palmas,
	246
	247	.mm.value = VDD_MM,
	248	.mm.addr = SMPS_REG_ADDR_45_IVA,
	249	.mm.pmic = &palmas,
	250	};
	251
47abc3df S	252	struct vcores_data omap5430_volts_es2 = {
47abc3df S	253	.mpu.value = VDD_MPU_ES2,
3fcdd4a5 S	254	.mpu.addr = SMPS_REG_ADDR_12_MPU,
	255	.mpu.pmic = &palmas,
	256
47abc3df	257	.core.value = VDD_CORE_ES2,
3fcdd4a5 S	258	.core.addr = SMPS_REG_ADDR_8_CORE,
	259	.core.pmic = &palmas,
	260
47abc3df	261	.mm.value = VDD_MM_ES2,
3fcdd4a5 S	262	.mm.addr = SMPS_REG_ADDR_45_IVA,
	263	.mm.pmic = &palmas,
	264	};
	265
ee9447bf S	266	/*
	267	* Enable essential clock domains, modules and
	268	* do some additional special settings needed
	269	*/
	270	void enable_basic_clocks(void)
	271	{
	272	u32 const clk_domains_essential[] = {
	273	(*prcm)->cm_l4per_clkstctrl,
	274	(*prcm)->cm_l3init_clkstctrl,
	275	(*prcm)->cm_memif_clkstctrl,
	276	(*prcm)->cm_l4cfg_clkstctrl,
	277	0
	278	};
	279
	280	u32 const clk_modules_hw_auto_essential[] = {
d4e4129c	281	(*prcm)->cm_l3_gpmc_clkctrl,
ee9447bf S	282	(*prcm)->cm_memif_emif_1_clkctrl,
	283	(*prcm)->cm_memif_emif_2_clkctrl,
	284	(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
	285	(*prcm)->cm_wkup_gpio1_clkctrl,
	286	(*prcm)->cm_l4per_gpio2_clkctrl,
	287	(*prcm)->cm_l4per_gpio3_clkctrl,
	288	(*prcm)->cm_l4per_gpio4_clkctrl,
	289	(*prcm)->cm_l4per_gpio5_clkctrl,
	290	(*prcm)->cm_l4per_gpio6_clkctrl,
	291	0
	292	};
	293
	294	u32 const clk_modules_explicit_en_essential[] = {
	295	(*prcm)->cm_wkup_gptimer1_clkctrl,
	296	(*prcm)->cm_l3init_hsmmc1_clkctrl,
	297	(*prcm)->cm_l3init_hsmmc2_clkctrl,
	298	(*prcm)->cm_l4per_gptimer2_clkctrl,
	299	(*prcm)->cm_wkup_wdtimer2_clkctrl,
	300	(*prcm)->cm_l4per_uart3_clkctrl,
	301	(*prcm)->cm_l4per_i2c1_clkctrl,
	302	0
	303	};
	304
	305	/* Enable optional additional functional clock for GPIO4 */
	306	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
	307	GPIO4_CLKCTRL_OPTFCLKEN_MASK);
	308
	309	/* Enable 96 MHz clock for MMC1 & MMC2 */
	310	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
	311	HSMMC_CLKCTRL_CLKSEL_MASK);
	312	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
	313	HSMMC_CLKCTRL_CLKSEL_MASK);
	314
	315	/* Set the correct clock dividers for mmc */
	316	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
	317	HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
	318	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
	319	HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
	320
	321	/* Select 32KHz clock as the source of GPTIMER1 */
	322	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
	323	GPTIMER1_CLKCTRL_CLKSEL_MASK);
	324
	325	do_enable_clocks(clk_domains_essential,
	326	clk_modules_hw_auto_essential,
	327	clk_modules_explicit_en_essential,
	328	1);
	329
	330	/* Select 384Mhz for GPU as its the POR for ES1.0 */
	331	setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
	332	CLKSEL_GPU_HYD_GCLK_MASK);
	333	setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
	334	CLKSEL_GPU_CORE_GCLK_MASK);
	335
	336	/* Enable SCRM OPT clocks for PER and CORE dpll */
	337	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
	338	OPTFCLKEN_SCRM_PER_MASK);
	339	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
	340	OPTFCLKEN_SCRM_CORE_MASK);
	341	}
	342
	343	void enable_basic_uboot_clocks(void)
	344	{
	345	u32 const clk_domains_essential[] = {
346	0
347	};
348
349	u32 const clk_modules_hw_auto_essential[] = {
350	0
351	};
352
353	u32 const clk_modules_explicit_en_essential[] = {
354	(*prcm)->cm_l4per_mcspi1_clkctrl,
355	(*prcm)->cm_l4per_i2c2_clkctrl,
356	(*prcm)->cm_l4per_i2c3_clkctrl,
357	(*prcm)->cm_l4per_i2c4_clkctrl,
358	(*prcm)->cm_l3init_hsusbtll_clkctrl,
359	(*prcm)->cm_l3init_hsusbhost_clkctrl,
360	(*prcm)->cm_l3init_fsusb_clkctrl,
361	0
362	};
363
364	do_enable_clocks(clk_domains_essential,
365	clk_modules_hw_auto_essential,
366	clk_modules_explicit_en_essential,
367	1);
368	}
369
370	/*
371	* Enable non-essential clock domains, modules and
372	* do some additional special settings needed
373	*/
374	void enable_non_essential_clocks(void)
375	{
376	u32 const clk_domains_non_essential[] = {
377	(*prcm)->cm_mpu_m3_clkstctrl,
378	(*prcm)->cm_ivahd_clkstctrl,
379	(*prcm)->cm_dsp_clkstctrl,
380	(*prcm)->cm_dss_clkstctrl,
381	(*prcm)->cm_sgx_clkstctrl,
382	(*prcm)->cm1_abe_clkstctrl,
383	(*prcm)->cm_c2c_clkstctrl,
384	(*prcm)->cm_cam_clkstctrl,
385	(*prcm)->cm_dss_clkstctrl,
386	(*prcm)->cm_sdma_clkstctrl,
387	0
388	};
389
390	u32 const clk_modules_hw_auto_non_essential[] = {
391	(*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
392	(*prcm)->cm_ivahd_ivahd_clkctrl,
393	(*prcm)->cm_ivahd_sl2_clkctrl,
394	(*prcm)->cm_dsp_dsp_clkctrl,
395	(*prcm)->cm_l3instr_l3_3_clkctrl,
396	(*prcm)->cm_l3instr_l3_instr_clkctrl,
397	(*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
398	(*prcm)->cm_l3init_hsi_clkctrl,
399	(*prcm)->cm_l4per_hdq1w_clkctrl,
400	0
401	};
402
403	u32 const clk_modules_explicit_en_non_essential[] = {
404	(*prcm)->cm1_abe_aess_clkctrl,
405	(*prcm)->cm1_abe_pdm_clkctrl,
406	(*prcm)->cm1_abe_dmic_clkctrl,
407	(*prcm)->cm1_abe_mcasp_clkctrl,
408	(*prcm)->cm1_abe_mcbsp1_clkctrl,
409	(*prcm)->cm1_abe_mcbsp2_clkctrl,
410	(*prcm)->cm1_abe_mcbsp3_clkctrl,
411	(*prcm)->cm1_abe_slimbus_clkctrl,
412	(*prcm)->cm1_abe_timer5_clkctrl,
413	(*prcm)->cm1_abe_timer6_clkctrl,
414	(*prcm)->cm1_abe_timer7_clkctrl,
415	(*prcm)->cm1_abe_timer8_clkctrl,
416	(*prcm)->cm1_abe_wdt3_clkctrl,
417	(*prcm)->cm_l4per_gptimer9_clkctrl,
418	(*prcm)->cm_l4per_gptimer10_clkctrl,
419	(*prcm)->cm_l4per_gptimer11_clkctrl,
420	(*prcm)->cm_l4per_gptimer3_clkctrl,
421	(*prcm)->cm_l4per_gptimer4_clkctrl,
422	(*prcm)->cm_l4per_mcspi2_clkctrl,
423	(*prcm)->cm_l4per_mcspi3_clkctrl,
424	(*prcm)->cm_l4per_mcspi4_clkctrl,
425	(*prcm)->cm_l4per_mmcsd3_clkctrl,
426	(*prcm)->cm_l4per_mmcsd4_clkctrl,
427	(*prcm)->cm_l4per_mmcsd5_clkctrl,
428	(*prcm)->cm_l4per_uart1_clkctrl,
429	(*prcm)->cm_l4per_uart2_clkctrl,
430	(*prcm)->cm_l4per_uart4_clkctrl,
431	(*prcm)->cm_wkup_keyboard_clkctrl,
432	(*prcm)->cm_wkup_wdtimer2_clkctrl,
433	(*prcm)->cm_cam_iss_clkctrl,
434	(*prcm)->cm_cam_fdif_clkctrl,
435	(*prcm)->cm_dss_dss_clkctrl,
436	(*prcm)->cm_sgx_sgx_clkctrl,
437	0
438	};
439
440	/* Enable optional functional clock for ISS */
441	setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
442
443	/* Enable all optional functional clocks of DSS */
444	setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
445
446	do_enable_clocks(clk_domains_non_essential,
447	clk_modules_hw_auto_non_essential,
448	clk_modules_explicit_en_non_essential,
449	0);
450
451	/* Put camera module in no sleep mode */
452	clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
453	MODULE_CLKCTRL_MODULEMODE_MASK,
454	CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
455	MODULE_CLKCTRL_MODULEMODE_SHIFT);
456	}
01b753ff	457
ef1697e9 LV	458	const struct ctrl_ioregs ioregs_omap5430 = {
	459	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
	460	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
	461	.ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
	462	.ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
	463	.ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
	464	};
	465
	466	const struct ctrl_ioregs ioregs_omap5432_es1 = {
	467	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
	468	.ctrl_lpddr2ch = 0x0,
	469	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
	470	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
	471	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
	472	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
	473	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
	474	};
	475
9100edec LV	476	const struct ctrl_ioregs ioregs_omap5432_es2 = {
	477	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
	478	.ctrl_lpddr2ch = 0x0,
	479	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
	480	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
	481	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
	482	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
	483	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
	484	};
	485
01b753ff S	486	void hw_data_init(void)
01b753ff S	487	{
ee9447bf S	488	u32 omap_rev = omap_revision();
	489
	490	switch (omap_rev) {
	491
	492	case OMAP5430_ES1_0:
ee9447bf S	493	case OMAP5432_ES1_0:
	494	*prcm = &omap5_es1_prcm;
	495	*dplls_data = &omap5_dplls_es1;
47abc3df	496	*omap_vcores = &omap5430_volts;
ee9447bf S	497	break;
ee9447bf S	498
afc2f9dc S	499	case OMAP5430_ES2_0:
	500	case OMAP5432_ES2_0:
	501	*prcm = &omap5_es2_prcm;
47abc3df S	502	*dplls_data = &omap5_dplls_es2;
47abc3df S	503	*omap_vcores = &omap5430_volts_es2;
afc2f9dc S	504	break;
afc2f9dc S	505
d4e4129c LV	506	case DRA752_ES1_0:
	507	*prcm = &dra7xx_prcm;
	508	break;
	509
ee9447bf S	510	default:
	511	printf("\n INVALID OMAP REVISION ");
	512	}
c43c8339 LV	513
c43c8339 LV	514	*ctrl = &omap5_ctrl;
01b753ff	515	}
ef1697e9 LV	516
	517	void get_ioregs(const struct ctrl_ioregs **regs)
	518	{
	519	u32 omap_rev = omap_revision();
	520
	521	switch (omap_rev) {
	522	case OMAP5430_ES1_0:
9100edec	523	case OMAP5430_ES2_0:
ef1697e9 LV	524	*regs = &ioregs_omap5430;
	525	break;
	526	case OMAP5432_ES1_0:
	527	*regs = &ioregs_omap5432_es1;
	528	break;
9100edec LV	529	case OMAP5432_ES2_0:
	530	*regs = &ioregs_omap5432_es2;
	531	break;
ef1697e9 LV	532
	533	default:
	534	printf("\n INVALID OMAP REVISION ");
	535	}
	536	}