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01b753ff S |
1 | /* |
2 | * | |
3 | * HW regs data for OMAP5 Soc | |
4 | * | |
5 | * (C) Copyright 2013 | |
6 | * Texas Instruments, <www.ti.com> | |
7 | * | |
8 | * Sricharan R <r.sricharan@ti.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <asm/omap_common.h> | |
30 | ||
31 | struct prcm_regs const omap5_es1_prcm = { | |
32 | /* cm1.ckgen */ | |
33 | .cm_clksel_core = 0x4a004100, | |
34 | .cm_clksel_abe = 0x4a004108, | |
35 | .cm_dll_ctrl = 0x4a004110, | |
36 | .cm_clkmode_dpll_core = 0x4a004120, | |
37 | .cm_idlest_dpll_core = 0x4a004124, | |
38 | .cm_autoidle_dpll_core = 0x4a004128, | |
39 | .cm_clksel_dpll_core = 0x4a00412c, | |
40 | .cm_div_m2_dpll_core = 0x4a004130, | |
41 | .cm_div_m3_dpll_core = 0x4a004134, | |
42 | .cm_div_h11_dpll_core = 0x4a004138, | |
43 | .cm_div_h12_dpll_core = 0x4a00413c, | |
44 | .cm_div_h13_dpll_core = 0x4a004140, | |
45 | .cm_div_h14_dpll_core = 0x4a004144, | |
46 | .cm_ssc_deltamstep_dpll_core = 0x4a004148, | |
47 | .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, | |
48 | .cm_emu_override_dpll_core = 0x4a004150, | |
49 | .cm_div_h22_dpllcore = 0x4a004154, | |
50 | .cm_div_h23_dpll_core = 0x4a004158, | |
51 | .cm_clkmode_dpll_mpu = 0x4a004160, | |
52 | .cm_idlest_dpll_mpu = 0x4a004164, | |
53 | .cm_autoidle_dpll_mpu = 0x4a004168, | |
54 | .cm_clksel_dpll_mpu = 0x4a00416c, | |
55 | .cm_div_m2_dpll_mpu = 0x4a004170, | |
56 | .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, | |
57 | .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, | |
58 | .cm_bypclk_dpll_mpu = 0x4a00419c, | |
59 | .cm_clkmode_dpll_iva = 0x4a0041a0, | |
60 | .cm_idlest_dpll_iva = 0x4a0041a4, | |
61 | .cm_autoidle_dpll_iva = 0x4a0041a8, | |
62 | .cm_clksel_dpll_iva = 0x4a0041ac, | |
63 | .cm_div_h11_dpll_iva = 0x4a0041b8, | |
64 | .cm_div_h12_dpll_iva = 0x4a0041bc, | |
65 | .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, | |
66 | .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, | |
67 | .cm_bypclk_dpll_iva = 0x4a0041dc, | |
68 | .cm_clkmode_dpll_abe = 0x4a0041e0, | |
69 | .cm_idlest_dpll_abe = 0x4a0041e4, | |
70 | .cm_autoidle_dpll_abe = 0x4a0041e8, | |
71 | .cm_clksel_dpll_abe = 0x4a0041ec, | |
72 | .cm_div_m2_dpll_abe = 0x4a0041f0, | |
73 | .cm_div_m3_dpll_abe = 0x4a0041f4, | |
74 | .cm_ssc_deltamstep_dpll_abe = 0x4a004208, | |
75 | .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, | |
76 | .cm_clkmode_dpll_ddrphy = 0x4a004220, | |
77 | .cm_idlest_dpll_ddrphy = 0x4a004224, | |
78 | .cm_autoidle_dpll_ddrphy = 0x4a004228, | |
79 | .cm_clksel_dpll_ddrphy = 0x4a00422c, | |
80 | .cm_div_m2_dpll_ddrphy = 0x4a004230, | |
81 | .cm_div_h11_dpll_ddrphy = 0x4a004238, | |
82 | .cm_div_h12_dpll_ddrphy = 0x4a00423c, | |
83 | .cm_div_h13_dpll_ddrphy = 0x4a004240, | |
84 | .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, | |
85 | .cm_shadow_freq_config1 = 0x4a004260, | |
86 | .cm_mpu_mpu_clkctrl = 0x4a004320, | |
87 | ||
88 | /* cm1.dsp */ | |
89 | .cm_dsp_clkstctrl = 0x4a004400, | |
90 | .cm_dsp_dsp_clkctrl = 0x4a004420, | |
91 | ||
92 | /* cm1.abe */ | |
93 | .cm1_abe_clkstctrl = 0x4a004500, | |
94 | .cm1_abe_l4abe_clkctrl = 0x4a004520, | |
95 | .cm1_abe_aess_clkctrl = 0x4a004528, | |
96 | .cm1_abe_pdm_clkctrl = 0x4a004530, | |
97 | .cm1_abe_dmic_clkctrl = 0x4a004538, | |
98 | .cm1_abe_mcasp_clkctrl = 0x4a004540, | |
99 | .cm1_abe_mcbsp1_clkctrl = 0x4a004548, | |
100 | .cm1_abe_mcbsp2_clkctrl = 0x4a004550, | |
101 | .cm1_abe_mcbsp3_clkctrl = 0x4a004558, | |
102 | .cm1_abe_slimbus_clkctrl = 0x4a004560, | |
103 | .cm1_abe_timer5_clkctrl = 0x4a004568, | |
104 | .cm1_abe_timer6_clkctrl = 0x4a004570, | |
105 | .cm1_abe_timer7_clkctrl = 0x4a004578, | |
106 | .cm1_abe_timer8_clkctrl = 0x4a004580, | |
107 | .cm1_abe_wdt3_clkctrl = 0x4a004588, | |
108 | ||
109 | /* cm2.ckgen */ | |
110 | .cm_clksel_mpu_m3_iss_root = 0x4a008100, | |
111 | .cm_clksel_usb_60mhz = 0x4a008104, | |
112 | .cm_scale_fclk = 0x4a008108, | |
113 | .cm_core_dvfs_perf1 = 0x4a008110, | |
114 | .cm_core_dvfs_perf2 = 0x4a008114, | |
115 | .cm_core_dvfs_perf3 = 0x4a008118, | |
116 | .cm_core_dvfs_perf4 = 0x4a00811c, | |
117 | .cm_core_dvfs_current = 0x4a008124, | |
118 | .cm_iva_dvfs_perf_tesla = 0x4a008128, | |
119 | .cm_iva_dvfs_perf_ivahd = 0x4a00812c, | |
120 | .cm_iva_dvfs_perf_abe = 0x4a008130, | |
121 | .cm_iva_dvfs_current = 0x4a008138, | |
122 | .cm_clkmode_dpll_per = 0x4a008140, | |
123 | .cm_idlest_dpll_per = 0x4a008144, | |
124 | .cm_autoidle_dpll_per = 0x4a008148, | |
125 | .cm_clksel_dpll_per = 0x4a00814c, | |
126 | .cm_div_m2_dpll_per = 0x4a008150, | |
127 | .cm_div_m3_dpll_per = 0x4a008154, | |
128 | .cm_div_h11_dpll_per = 0x4a008158, | |
129 | .cm_div_h12_dpll_per = 0x4a00815c, | |
130 | .cm_div_h14_dpll_per = 0x4a008164, | |
131 | .cm_ssc_deltamstep_dpll_per = 0x4a008168, | |
132 | .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, | |
133 | .cm_emu_override_dpll_per = 0x4a008170, | |
134 | .cm_clkmode_dpll_usb = 0x4a008180, | |
135 | .cm_idlest_dpll_usb = 0x4a008184, | |
136 | .cm_autoidle_dpll_usb = 0x4a008188, | |
137 | .cm_clksel_dpll_usb = 0x4a00818c, | |
138 | .cm_div_m2_dpll_usb = 0x4a008190, | |
139 | .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, | |
140 | .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, | |
141 | .cm_clkdcoldo_dpll_usb = 0x4a0081b4, | |
142 | .cm_clkmode_dpll_unipro = 0x4a0081c0, | |
143 | .cm_idlest_dpll_unipro = 0x4a0081c4, | |
144 | .cm_autoidle_dpll_unipro = 0x4a0081c8, | |
145 | .cm_clksel_dpll_unipro = 0x4a0081cc, | |
146 | .cm_div_m2_dpll_unipro = 0x4a0081d0, | |
147 | .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, | |
148 | .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, | |
149 | ||
150 | /* cm2.core */ | |
151 | .cm_coreaon_bandgap_clkctrl = 0x4a008648, | |
d4d986ee | 152 | .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, |
01b753ff S |
153 | .cm_l3_1_clkstctrl = 0x4a008700, |
154 | .cm_l3_1_dynamicdep = 0x4a008708, | |
155 | .cm_l3_1_l3_1_clkctrl = 0x4a008720, | |
156 | .cm_l3_2_clkstctrl = 0x4a008800, | |
157 | .cm_l3_2_dynamicdep = 0x4a008808, | |
158 | .cm_l3_2_l3_2_clkctrl = 0x4a008820, | |
d4e4129c | 159 | .cm_l3_gpmc_clkctrl = 0x4a008828, |
01b753ff S |
160 | .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, |
161 | .cm_mpu_m3_clkstctrl = 0x4a008900, | |
162 | .cm_mpu_m3_staticdep = 0x4a008904, | |
163 | .cm_mpu_m3_dynamicdep = 0x4a008908, | |
164 | .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, | |
165 | .cm_sdma_clkstctrl = 0x4a008a00, | |
166 | .cm_sdma_staticdep = 0x4a008a04, | |
167 | .cm_sdma_dynamicdep = 0x4a008a08, | |
168 | .cm_sdma_sdma_clkctrl = 0x4a008a20, | |
169 | .cm_memif_clkstctrl = 0x4a008b00, | |
170 | .cm_memif_dmm_clkctrl = 0x4a008b20, | |
171 | .cm_memif_emif_fw_clkctrl = 0x4a008b28, | |
172 | .cm_memif_emif_1_clkctrl = 0x4a008b30, | |
173 | .cm_memif_emif_2_clkctrl = 0x4a008b38, | |
174 | .cm_memif_dll_clkctrl = 0x4a008b40, | |
175 | .cm_memif_emif_h1_clkctrl = 0x4a008b50, | |
176 | .cm_memif_emif_h2_clkctrl = 0x4a008b58, | |
177 | .cm_memif_dll_h_clkctrl = 0x4a008b60, | |
178 | .cm_c2c_clkstctrl = 0x4a008c00, | |
179 | .cm_c2c_staticdep = 0x4a008c04, | |
180 | .cm_c2c_dynamicdep = 0x4a008c08, | |
181 | .cm_c2c_sad2d_clkctrl = 0x4a008c20, | |
182 | .cm_c2c_modem_icr_clkctrl = 0x4a008c28, | |
183 | .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, | |
184 | .cm_l4cfg_clkstctrl = 0x4a008d00, | |
185 | .cm_l4cfg_dynamicdep = 0x4a008d08, | |
186 | .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, | |
187 | .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, | |
188 | .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, | |
189 | .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, | |
190 | .cm_l3instr_clkstctrl = 0x4a008e00, | |
191 | .cm_l3instr_l3_3_clkctrl = 0x4a008e20, | |
192 | .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, | |
193 | .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, | |
194 | ||
195 | /* cm2.ivahd */ | |
196 | .cm_ivahd_clkstctrl = 0x4a008f00, | |
197 | .cm_ivahd_ivahd_clkctrl = 0x4a008f20, | |
198 | .cm_ivahd_sl2_clkctrl = 0x4a008f28, | |
199 | ||
200 | /* cm2.cam */ | |
201 | .cm_cam_clkstctrl = 0x4a009000, | |
202 | .cm_cam_iss_clkctrl = 0x4a009020, | |
203 | .cm_cam_fdif_clkctrl = 0x4a009028, | |
204 | ||
205 | /* cm2.dss */ | |
206 | .cm_dss_clkstctrl = 0x4a009100, | |
207 | .cm_dss_dss_clkctrl = 0x4a009120, | |
208 | ||
209 | /* cm2.sgx */ | |
210 | .cm_sgx_clkstctrl = 0x4a009200, | |
211 | .cm_sgx_sgx_clkctrl = 0x4a009220, | |
212 | ||
213 | /* cm2.l3init */ | |
214 | .cm_l3init_clkstctrl = 0x4a009300, | |
215 | .cm_l3init_hsmmc1_clkctrl = 0x4a009328, | |
216 | .cm_l3init_hsmmc2_clkctrl = 0x4a009330, | |
217 | .cm_l3init_hsi_clkctrl = 0x4a009338, | |
218 | .cm_l3init_hsusbhost_clkctrl = 0x4a009358, | |
219 | .cm_l3init_hsusbotg_clkctrl = 0x4a009360, | |
220 | .cm_l3init_hsusbtll_clkctrl = 0x4a009368, | |
221 | .cm_l3init_p1500_clkctrl = 0x4a009378, | |
222 | .cm_l3init_fsusb_clkctrl = 0x4a0093d0, | |
223 | .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, | |
224 | ||
225 | /* cm2.l4per */ | |
226 | .cm_l4per_clkstctrl = 0x4a009400, | |
227 | .cm_l4per_dynamicdep = 0x4a009408, | |
228 | .cm_l4per_adc_clkctrl = 0x4a009420, | |
229 | .cm_l4per_gptimer10_clkctrl = 0x4a009428, | |
230 | .cm_l4per_gptimer11_clkctrl = 0x4a009430, | |
231 | .cm_l4per_gptimer2_clkctrl = 0x4a009438, | |
232 | .cm_l4per_gptimer3_clkctrl = 0x4a009440, | |
233 | .cm_l4per_gptimer4_clkctrl = 0x4a009448, | |
234 | .cm_l4per_gptimer9_clkctrl = 0x4a009450, | |
235 | .cm_l4per_elm_clkctrl = 0x4a009458, | |
236 | .cm_l4per_gpio2_clkctrl = 0x4a009460, | |
237 | .cm_l4per_gpio3_clkctrl = 0x4a009468, | |
238 | .cm_l4per_gpio4_clkctrl = 0x4a009470, | |
239 | .cm_l4per_gpio5_clkctrl = 0x4a009478, | |
240 | .cm_l4per_gpio6_clkctrl = 0x4a009480, | |
241 | .cm_l4per_hdq1w_clkctrl = 0x4a009488, | |
242 | .cm_l4per_hecc1_clkctrl = 0x4a009490, | |
243 | .cm_l4per_hecc2_clkctrl = 0x4a009498, | |
244 | .cm_l4per_i2c1_clkctrl = 0x4a0094a0, | |
245 | .cm_l4per_i2c2_clkctrl = 0x4a0094a8, | |
246 | .cm_l4per_i2c3_clkctrl = 0x4a0094b0, | |
247 | .cm_l4per_i2c4_clkctrl = 0x4a0094b8, | |
248 | .cm_l4per_l4per_clkctrl = 0x4a0094c0, | |
249 | .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, | |
250 | .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, | |
251 | .cm_l4per_mgate_clkctrl = 0x4a0094e8, | |
252 | .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, | |
253 | .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, | |
254 | .cm_l4per_mcspi3_clkctrl = 0x4a009500, | |
255 | .cm_l4per_mcspi4_clkctrl = 0x4a009508, | |
256 | .cm_l4per_gpio7_clkctrl = 0x4a009510, | |
257 | .cm_l4per_gpio8_clkctrl = 0x4a009518, | |
258 | .cm_l4per_mmcsd3_clkctrl = 0x4a009520, | |
259 | .cm_l4per_mmcsd4_clkctrl = 0x4a009528, | |
260 | .cm_l4per_msprohg_clkctrl = 0x4a009530, | |
261 | .cm_l4per_slimbus2_clkctrl = 0x4a009538, | |
262 | .cm_l4per_uart1_clkctrl = 0x4a009540, | |
263 | .cm_l4per_uart2_clkctrl = 0x4a009548, | |
264 | .cm_l4per_uart3_clkctrl = 0x4a009550, | |
265 | .cm_l4per_uart4_clkctrl = 0x4a009558, | |
266 | .cm_l4per_mmcsd5_clkctrl = 0x4a009560, | |
267 | .cm_l4per_i2c5_clkctrl = 0x4a009568, | |
268 | .cm_l4per_uart5_clkctrl = 0x4a009570, | |
269 | .cm_l4per_uart6_clkctrl = 0x4a009578, | |
270 | .cm_l4sec_clkstctrl = 0x4a009580, | |
271 | .cm_l4sec_staticdep = 0x4a009584, | |
272 | .cm_l4sec_dynamicdep = 0x4a009588, | |
273 | .cm_l4sec_aes1_clkctrl = 0x4a0095a0, | |
274 | .cm_l4sec_aes2_clkctrl = 0x4a0095a8, | |
275 | .cm_l4sec_des3des_clkctrl = 0x4a0095b0, | |
276 | .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, | |
277 | .cm_l4sec_rng_clkctrl = 0x4a0095c0, | |
278 | .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, | |
279 | .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, | |
280 | ||
281 | /* l4 wkup regs */ | |
282 | .cm_abe_pll_ref_clksel = 0x4ae0610c, | |
283 | .cm_sys_clksel = 0x4ae06110, | |
284 | .cm_wkup_clkstctrl = 0x4ae07800, | |
285 | .cm_wkup_l4wkup_clkctrl = 0x4ae07820, | |
286 | .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, | |
287 | .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, | |
288 | .cm_wkup_gpio1_clkctrl = 0x4ae07838, | |
289 | .cm_wkup_gptimer1_clkctrl = 0x4ae07840, | |
290 | .cm_wkup_gptimer12_clkctrl = 0x4ae07848, | |
291 | .cm_wkup_synctimer_clkctrl = 0x4ae07850, | |
292 | .cm_wkup_usim_clkctrl = 0x4ae07858, | |
293 | .cm_wkup_sarram_clkctrl = 0x4ae07860, | |
294 | .cm_wkup_keyboard_clkctrl = 0x4ae07878, | |
295 | .cm_wkup_rtc_clkctrl = 0x4ae07880, | |
296 | .cm_wkup_bandgap_clkctrl = 0x4ae07888, | |
297 | .cm_wkupaon_scrm_clkctrl = 0x4ae07890, | |
d4d986ee | 298 | .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, |
d4e4129c LV |
299 | .prm_rstctrl = 0x4ae07b00, |
300 | .prm_rstst = 0x4ae07b04, | |
01b753ff S |
301 | .prm_vc_val_bypass = 0x4ae07ba0, |
302 | .prm_vc_cfg_i2c_mode = 0x4ae07bb4, | |
303 | .prm_vc_cfg_i2c_clk = 0x4ae07bb8, | |
304 | .prm_sldo_core_setup = 0x4ae07bc4, | |
305 | .prm_sldo_core_ctrl = 0x4ae07bc8, | |
306 | .prm_sldo_mpu_setup = 0x4ae07bcc, | |
307 | .prm_sldo_mpu_ctrl = 0x4ae07bd0, | |
308 | .prm_sldo_mm_setup = 0x4ae07bd4, | |
309 | .prm_sldo_mm_ctrl = 0x4ae07bd8, | |
310 | }; | |
c43c8339 LV |
311 | |
312 | struct omap_sys_ctrl_regs const omap5_ctrl = { | |
313 | .control_status = 0x4A002134, | |
314 | .control_paconf_global = 0x4A002DA0, | |
315 | .control_paconf_mode = 0x4A002DA4, | |
316 | .control_smart1io_padconf_0 = 0x4A002DA8, | |
317 | .control_smart1io_padconf_1 = 0x4A002DAC, | |
318 | .control_smart1io_padconf_2 = 0x4A002DB0, | |
319 | .control_smart2io_padconf_0 = 0x4A002DB4, | |
320 | .control_smart2io_padconf_1 = 0x4A002DB8, | |
321 | .control_smart2io_padconf_2 = 0x4A002DBC, | |
322 | .control_smart3io_padconf_0 = 0x4A002DC0, | |
323 | .control_smart3io_padconf_1 = 0x4A002DC4, | |
324 | .control_pbias = 0x4A002E00, | |
325 | .control_i2c_0 = 0x4A002E04, | |
326 | .control_camera_rx = 0x4A002E08, | |
327 | .control_hdmi_tx_phy = 0x4A002E0C, | |
328 | .control_uniportm = 0x4A002E10, | |
329 | .control_dsiphy = 0x4A002E14, | |
330 | .control_mcbsplp = 0x4A002E18, | |
331 | .control_usb2phycore = 0x4A002E1C, | |
332 | .control_hdmi_1 = 0x4A002E20, | |
333 | .control_hsi = 0x4A002E24, | |
334 | .control_ddr3ch1_0 = 0x4A002E30, | |
335 | .control_ddr3ch2_0 = 0x4A002E34, | |
336 | .control_ddrch1_0 = 0x4A002E38, | |
337 | .control_ddrch1_1 = 0x4A002E3C, | |
338 | .control_ddrch2_0 = 0x4A002E40, | |
339 | .control_ddrch2_1 = 0x4A002E44, | |
340 | .control_lpddr2ch1_0 = 0x4A002E48, | |
341 | .control_lpddr2ch1_1 = 0x4A002E4C, | |
342 | .control_ddrio_0 = 0x4A002E50, | |
343 | .control_ddrio_1 = 0x4A002E54, | |
344 | .control_ddrio_2 = 0x4A002E58, | |
345 | .control_hyst_1 = 0x4A002E5C, | |
346 | .control_usbb_hsic_control = 0x4A002E60, | |
347 | .control_c2c = 0x4A002E64, | |
348 | .control_core_control_spare_rw = 0x4A002E68, | |
349 | .control_core_control_spare_r = 0x4A002E6C, | |
350 | .control_core_control_spare_r_c0 = 0x4A002E70, | |
351 | .control_srcomp_north_side = 0x4A002E74, | |
352 | .control_srcomp_south_side = 0x4A002E78, | |
353 | .control_srcomp_east_side = 0x4A002E7C, | |
354 | .control_srcomp_west_side = 0x4A002E80, | |
355 | .control_srcomp_code_latch = 0x4A002E84, | |
356 | .control_port_emif1_sdram_config = 0x4AE0C110, | |
357 | .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, | |
358 | .control_port_emif2_sdram_config = 0x4AE0C118, | |
359 | .control_emif1_sdram_config_ext = 0x4AE0C144, | |
360 | .control_emif2_sdram_config_ext = 0x4AE0C148, | |
361 | .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, | |
362 | .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, | |
363 | .control_padconf_mode = 0x4AE0CDA8, | |
364 | .control_xtal_oscillator = 0x4AE0CDAC, | |
365 | .control_i2c_2 = 0x4AE0CDB0, | |
366 | .control_ckobuffer = 0x4AE0CDB4, | |
367 | .control_wkup_control_spare_rw = 0x4AE0CDB8, | |
368 | .control_wkup_control_spare_r = 0x4AE0CDBC, | |
369 | .control_wkup_control_spare_r_c0 = 0x4AE0CDC0, | |
370 | .control_srcomp_east_side_wkup = 0x4AE0CDC4, | |
371 | .control_efuse_1 = 0x4AE0CDC8, | |
372 | .control_efuse_2 = 0x4AE0CDCC, | |
373 | .control_efuse_3 = 0x4AE0CDD0, | |
374 | .control_efuse_4 = 0x4AE0CDD4, | |
375 | .control_efuse_5 = 0x4AE0CDD8, | |
376 | .control_efuse_6 = 0x4AE0CDDC, | |
377 | .control_efuse_7 = 0x4AE0CDE0, | |
378 | .control_efuse_8 = 0x4AE0CDE4, | |
379 | .control_efuse_9 = 0x4AE0CDE8, | |
380 | .control_efuse_10 = 0x4AE0CDEC, | |
381 | .control_efuse_11 = 0x4AE0CDF0, | |
382 | .control_efuse_12 = 0x4AE0CDF4, | |
383 | .control_efuse_13 = 0x4AE0CDF8, | |
384 | }; | |
afc2f9dc | 385 | |
8b12f177 LV |
386 | struct omap_sys_ctrl_regs const dra7xx_ctrl = { |
387 | .control_status = 0x4A002134, | |
388 | .control_core_mmr_lock1 = 0x4A002540, | |
389 | .control_core_mmr_lock2 = 0x4A002544, | |
390 | .control_core_mmr_lock3 = 0x4A002548, | |
391 | .control_core_mmr_lock4 = 0x4A00254C, | |
392 | .control_core_mmr_lock5 = 0x4A002550, | |
393 | .control_core_control_io1 = 0x4A002554, | |
394 | .control_core_control_io2 = 0x4A002558, | |
395 | .control_paconf_global = 0x4A002DA0, | |
396 | .control_paconf_mode = 0x4A002DA4, | |
397 | .control_smart1io_padconf_0 = 0x4A002DA8, | |
398 | .control_smart1io_padconf_1 = 0x4A002DAC, | |
399 | .control_smart1io_padconf_2 = 0x4A002DB0, | |
400 | .control_smart2io_padconf_0 = 0x4A002DB4, | |
401 | .control_smart2io_padconf_1 = 0x4A002DB8, | |
402 | .control_smart2io_padconf_2 = 0x4A002DBC, | |
403 | .control_smart3io_padconf_0 = 0x4A002DC0, | |
404 | .control_smart3io_padconf_1 = 0x4A002DC4, | |
405 | .control_pbias = 0x4A002E00, | |
406 | .control_i2c_0 = 0x4A002E04, | |
407 | .control_camera_rx = 0x4A002E08, | |
408 | .control_hdmi_tx_phy = 0x4A002E0C, | |
409 | .control_uniportm = 0x4A002E10, | |
410 | .control_dsiphy = 0x4A002E14, | |
411 | .control_mcbsplp = 0x4A002E18, | |
412 | .control_usb2phycore = 0x4A002E1C, | |
413 | .control_hdmi_1 = 0x4A002E20, | |
414 | .control_hsi = 0x4A002E24, | |
415 | .control_ddr3ch1_0 = 0x4A002E30, | |
416 | .control_ddr3ch2_0 = 0x4A002E34, | |
417 | .control_ddrch1_0 = 0x4A002E38, | |
418 | .control_ddrch1_1 = 0x4A002E3C, | |
419 | .control_ddrch2_0 = 0x4A002E40, | |
420 | .control_ddrch2_1 = 0x4A002E44, | |
421 | .control_lpddr2ch1_0 = 0x4A002E48, | |
422 | .control_lpddr2ch1_1 = 0x4A002E4C, | |
423 | .control_ddrio_0 = 0x4A002E50, | |
424 | .control_ddrio_1 = 0x4A002E54, | |
425 | .control_ddrio_2 = 0x4A002E58, | |
426 | .control_hyst_1 = 0x4A002E5C, | |
427 | .control_usbb_hsic_control = 0x4A002E60, | |
428 | .control_c2c = 0x4A002E64, | |
429 | .control_core_control_spare_rw = 0x4A002E68, | |
430 | .control_core_control_spare_r = 0x4A002E6C, | |
431 | .control_core_control_spare_r_c0 = 0x4A002E70, | |
432 | .control_srcomp_north_side = 0x4A002E74, | |
433 | .control_srcomp_south_side = 0x4A002E78, | |
434 | .control_srcomp_east_side = 0x4A002E7C, | |
435 | .control_srcomp_west_side = 0x4A002E80, | |
436 | .control_srcomp_code_latch = 0x4A002E84, | |
437 | .control_padconf_core_base = 0x4A003400, | |
438 | .control_port_emif1_sdram_config = 0x4AE0C110, | |
439 | .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, | |
440 | .control_port_emif2_sdram_config = 0x4AE0C118, | |
441 | .control_emif1_sdram_config_ext = 0x4AE0C144, | |
442 | .control_emif2_sdram_config_ext = 0x4AE0C148, | |
443 | .control_padconf_mode = 0x4AE0C5A0, | |
444 | .control_xtal_oscillator = 0x4AE0C5A4, | |
445 | .control_i2c_2 = 0x4AE0C5A8, | |
446 | .control_ckobuffer = 0x4AE0C5AC, | |
447 | .control_wkup_control_spare_rw = 0x4AE0C5B0, | |
448 | .control_wkup_control_spare_r = 0x4AE0C5B4, | |
449 | .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, | |
450 | .control_srcomp_east_side_wkup = 0x4AE0C5BC, | |
451 | .control_efuse_1 = 0x4AE0C5C0, | |
452 | .control_efuse_2 = 0x4AE0C5C4, | |
453 | .control_efuse_3 = 0x4AE0C5C8, | |
454 | .control_efuse_4 = 0x4AE0C5CC, | |
455 | .control_efuse_13 = 0x4AE0C5F0, | |
456 | }; | |
457 | ||
afc2f9dc S |
458 | struct prcm_regs const omap5_es2_prcm = { |
459 | /* cm1.ckgen */ | |
460 | .cm_clksel_core = 0x4a004100, | |
461 | .cm_clksel_abe = 0x4a004108, | |
462 | .cm_dll_ctrl = 0x4a004110, | |
463 | .cm_clkmode_dpll_core = 0x4a004120, | |
464 | .cm_idlest_dpll_core = 0x4a004124, | |
465 | .cm_autoidle_dpll_core = 0x4a004128, | |
466 | .cm_clksel_dpll_core = 0x4a00412c, | |
467 | .cm_div_m2_dpll_core = 0x4a004130, | |
468 | .cm_div_m3_dpll_core = 0x4a004134, | |
469 | .cm_div_h11_dpll_core = 0x4a004138, | |
470 | .cm_div_h12_dpll_core = 0x4a00413c, | |
471 | .cm_div_h13_dpll_core = 0x4a004140, | |
472 | .cm_div_h14_dpll_core = 0x4a004144, | |
473 | .cm_ssc_deltamstep_dpll_core = 0x4a004148, | |
474 | .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, | |
475 | .cm_div_h21_dpll_core = 0x4a004150, | |
476 | .cm_div_h22_dpllcore = 0x4a004154, | |
477 | .cm_div_h23_dpll_core = 0x4a004158, | |
478 | .cm_div_h24_dpll_core = 0x4a00415c, | |
479 | .cm_clkmode_dpll_mpu = 0x4a004160, | |
480 | .cm_idlest_dpll_mpu = 0x4a004164, | |
481 | .cm_autoidle_dpll_mpu = 0x4a004168, | |
482 | .cm_clksel_dpll_mpu = 0x4a00416c, | |
483 | .cm_div_m2_dpll_mpu = 0x4a004170, | |
484 | .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, | |
485 | .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, | |
486 | .cm_bypclk_dpll_mpu = 0x4a00419c, | |
487 | .cm_clkmode_dpll_iva = 0x4a0041a0, | |
488 | .cm_idlest_dpll_iva = 0x4a0041a4, | |
489 | .cm_autoidle_dpll_iva = 0x4a0041a8, | |
490 | .cm_clksel_dpll_iva = 0x4a0041ac, | |
491 | .cm_div_h11_dpll_iva = 0x4a0041b8, | |
492 | .cm_div_h12_dpll_iva = 0x4a0041bc, | |
493 | .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, | |
494 | .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, | |
495 | .cm_bypclk_dpll_iva = 0x4a0041dc, | |
496 | .cm_clkmode_dpll_abe = 0x4a0041e0, | |
497 | .cm_idlest_dpll_abe = 0x4a0041e4, | |
498 | .cm_autoidle_dpll_abe = 0x4a0041e8, | |
499 | .cm_clksel_dpll_abe = 0x4a0041ec, | |
500 | .cm_div_m2_dpll_abe = 0x4a0041f0, | |
501 | .cm_div_m3_dpll_abe = 0x4a0041f4, | |
502 | .cm_ssc_deltamstep_dpll_abe = 0x4a004208, | |
503 | .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, | |
504 | .cm_clkmode_dpll_ddrphy = 0x4a004220, | |
505 | .cm_idlest_dpll_ddrphy = 0x4a004224, | |
506 | .cm_autoidle_dpll_ddrphy = 0x4a004228, | |
507 | .cm_clksel_dpll_ddrphy = 0x4a00422c, | |
508 | .cm_div_m2_dpll_ddrphy = 0x4a004230, | |
509 | .cm_div_h11_dpll_ddrphy = 0x4a004238, | |
510 | .cm_div_h12_dpll_ddrphy = 0x4a00423c, | |
511 | .cm_div_h13_dpll_ddrphy = 0x4a004240, | |
512 | .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, | |
513 | .cm_shadow_freq_config1 = 0x4a004260, | |
514 | .cm_mpu_mpu_clkctrl = 0x4a004320, | |
515 | ||
516 | /* cm1.dsp */ | |
517 | .cm_dsp_clkstctrl = 0x4a004400, | |
518 | .cm_dsp_dsp_clkctrl = 0x4a004420, | |
519 | ||
520 | /* cm1.abe */ | |
521 | .cm1_abe_clkstctrl = 0x4a004500, | |
522 | .cm1_abe_l4abe_clkctrl = 0x4a004520, | |
523 | .cm1_abe_aess_clkctrl = 0x4a004528, | |
524 | .cm1_abe_pdm_clkctrl = 0x4a004530, | |
525 | .cm1_abe_dmic_clkctrl = 0x4a004538, | |
526 | .cm1_abe_mcasp_clkctrl = 0x4a004540, | |
527 | .cm1_abe_mcbsp1_clkctrl = 0x4a004548, | |
528 | .cm1_abe_mcbsp2_clkctrl = 0x4a004550, | |
529 | .cm1_abe_mcbsp3_clkctrl = 0x4a004558, | |
530 | .cm1_abe_slimbus_clkctrl = 0x4a004560, | |
531 | .cm1_abe_timer5_clkctrl = 0x4a004568, | |
532 | .cm1_abe_timer6_clkctrl = 0x4a004570, | |
533 | .cm1_abe_timer7_clkctrl = 0x4a004578, | |
534 | .cm1_abe_timer8_clkctrl = 0x4a004580, | |
535 | .cm1_abe_wdt3_clkctrl = 0x4a004588, | |
536 | ||
537 | ||
538 | ||
539 | /* cm2.ckgen */ | |
540 | .cm_clksel_mpu_m3_iss_root = 0x4a008100, | |
541 | .cm_clksel_usb_60mhz = 0x4a008104, | |
542 | .cm_scale_fclk = 0x4a008108, | |
543 | .cm_core_dvfs_perf1 = 0x4a008110, | |
544 | .cm_core_dvfs_perf2 = 0x4a008114, | |
545 | .cm_core_dvfs_perf3 = 0x4a008118, | |
546 | .cm_core_dvfs_perf4 = 0x4a00811c, | |
547 | .cm_core_dvfs_current = 0x4a008124, | |
548 | .cm_iva_dvfs_perf_tesla = 0x4a008128, | |
549 | .cm_iva_dvfs_perf_ivahd = 0x4a00812c, | |
550 | .cm_iva_dvfs_perf_abe = 0x4a008130, | |
551 | .cm_iva_dvfs_current = 0x4a008138, | |
552 | .cm_clkmode_dpll_per = 0x4a008140, | |
553 | .cm_idlest_dpll_per = 0x4a008144, | |
554 | .cm_autoidle_dpll_per = 0x4a008148, | |
555 | .cm_clksel_dpll_per = 0x4a00814c, | |
556 | .cm_div_m2_dpll_per = 0x4a008150, | |
557 | .cm_div_m3_dpll_per = 0x4a008154, | |
558 | .cm_div_h11_dpll_per = 0x4a008158, | |
559 | .cm_div_h12_dpll_per = 0x4a00815c, | |
560 | .cm_div_h13_dpll_per = 0x4a008160, | |
561 | .cm_div_h14_dpll_per = 0x4a008164, | |
562 | .cm_ssc_deltamstep_dpll_per = 0x4a008168, | |
563 | .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, | |
564 | .cm_emu_override_dpll_per = 0x4a008170, | |
565 | .cm_clkmode_dpll_usb = 0x4a008180, | |
566 | .cm_idlest_dpll_usb = 0x4a008184, | |
567 | .cm_autoidle_dpll_usb = 0x4a008188, | |
568 | .cm_clksel_dpll_usb = 0x4a00818c, | |
569 | .cm_div_m2_dpll_usb = 0x4a008190, | |
570 | .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, | |
571 | .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, | |
572 | .cm_clkdcoldo_dpll_usb = 0x4a0081b4, | |
573 | .cm_clkmode_dpll_unipro = 0x4a0081c0, | |
574 | .cm_idlest_dpll_unipro = 0x4a0081c4, | |
575 | .cm_autoidle_dpll_unipro = 0x4a0081c8, | |
576 | .cm_clksel_dpll_unipro = 0x4a0081cc, | |
577 | .cm_div_m2_dpll_unipro = 0x4a0081d0, | |
578 | .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, | |
579 | .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, | |
580 | .cm_coreaon_bandgap_clkctrl = 0x4a008648, | |
d4d986ee | 581 | .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, |
afc2f9dc S |
582 | |
583 | /* cm2.core */ | |
584 | .cm_l3_1_clkstctrl = 0x4a008700, | |
585 | .cm_l3_1_dynamicdep = 0x4a008708, | |
586 | .cm_l3_1_l3_1_clkctrl = 0x4a008720, | |
587 | .cm_l3_2_clkstctrl = 0x4a008800, | |
588 | .cm_l3_2_dynamicdep = 0x4a008808, | |
589 | .cm_l3_2_l3_2_clkctrl = 0x4a008820, | |
d4e4129c | 590 | .cm_l3_gpmc_clkctrl = 0x4a008828, |
afc2f9dc S |
591 | .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, |
592 | .cm_mpu_m3_clkstctrl = 0x4a008900, | |
593 | .cm_mpu_m3_staticdep = 0x4a008904, | |
594 | .cm_mpu_m3_dynamicdep = 0x4a008908, | |
595 | .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, | |
596 | .cm_sdma_clkstctrl = 0x4a008a00, | |
597 | .cm_sdma_staticdep = 0x4a008a04, | |
598 | .cm_sdma_dynamicdep = 0x4a008a08, | |
599 | .cm_sdma_sdma_clkctrl = 0x4a008a20, | |
600 | .cm_memif_clkstctrl = 0x4a008b00, | |
601 | .cm_memif_dmm_clkctrl = 0x4a008b20, | |
602 | .cm_memif_emif_fw_clkctrl = 0x4a008b28, | |
603 | .cm_memif_emif_1_clkctrl = 0x4a008b30, | |
604 | .cm_memif_emif_2_clkctrl = 0x4a008b38, | |
605 | .cm_memif_dll_clkctrl = 0x4a008b40, | |
606 | .cm_memif_emif_h1_clkctrl = 0x4a008b50, | |
607 | .cm_memif_emif_h2_clkctrl = 0x4a008b58, | |
608 | .cm_memif_dll_h_clkctrl = 0x4a008b60, | |
609 | .cm_c2c_clkstctrl = 0x4a008c00, | |
610 | .cm_c2c_staticdep = 0x4a008c04, | |
611 | .cm_c2c_dynamicdep = 0x4a008c08, | |
612 | .cm_c2c_sad2d_clkctrl = 0x4a008c20, | |
613 | .cm_c2c_modem_icr_clkctrl = 0x4a008c28, | |
614 | .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, | |
615 | .cm_l4cfg_clkstctrl = 0x4a008d00, | |
616 | .cm_l4cfg_dynamicdep = 0x4a008d08, | |
617 | .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, | |
618 | .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, | |
619 | .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, | |
620 | .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, | |
621 | .cm_l3instr_clkstctrl = 0x4a008e00, | |
622 | .cm_l3instr_l3_3_clkctrl = 0x4a008e20, | |
623 | .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, | |
624 | .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, | |
625 | .cm_l4per_clkstctrl = 0x4a009000, | |
626 | .cm_l4per_dynamicdep = 0x4a009008, | |
627 | .cm_l4per_adc_clkctrl = 0x4a009020, | |
628 | .cm_l4per_gptimer10_clkctrl = 0x4a009028, | |
629 | .cm_l4per_gptimer11_clkctrl = 0x4a009030, | |
630 | .cm_l4per_gptimer2_clkctrl = 0x4a009038, | |
631 | .cm_l4per_gptimer3_clkctrl = 0x4a009040, | |
632 | .cm_l4per_gptimer4_clkctrl = 0x4a009048, | |
633 | .cm_l4per_gptimer9_clkctrl = 0x4a009050, | |
634 | .cm_l4per_elm_clkctrl = 0x4a009058, | |
635 | .cm_l4per_gpio2_clkctrl = 0x4a009060, | |
636 | .cm_l4per_gpio3_clkctrl = 0x4a009068, | |
637 | .cm_l4per_gpio4_clkctrl = 0x4a009070, | |
638 | .cm_l4per_gpio5_clkctrl = 0x4a009078, | |
639 | .cm_l4per_gpio6_clkctrl = 0x4a009080, | |
640 | .cm_l4per_hdq1w_clkctrl = 0x4a009088, | |
641 | .cm_l4per_hecc1_clkctrl = 0x4a009090, | |
642 | .cm_l4per_hecc2_clkctrl = 0x4a009098, | |
643 | .cm_l4per_i2c1_clkctrl = 0x4a0090a0, | |
644 | .cm_l4per_i2c2_clkctrl = 0x4a0090a8, | |
645 | .cm_l4per_i2c3_clkctrl = 0x4a0090b0, | |
646 | .cm_l4per_i2c4_clkctrl = 0x4a0090b8, | |
647 | .cm_l4per_l4per_clkctrl = 0x4a0090c0, | |
648 | .cm_l4per_mcasp2_clkctrl = 0x4a0090d0, | |
649 | .cm_l4per_mcasp3_clkctrl = 0x4a0090d8, | |
650 | .cm_l4per_mgate_clkctrl = 0x4a0090e8, | |
651 | .cm_l4per_mcspi1_clkctrl = 0x4a0090f0, | |
652 | .cm_l4per_mcspi2_clkctrl = 0x4a0090f8, | |
653 | .cm_l4per_mcspi3_clkctrl = 0x4a009100, | |
654 | .cm_l4per_mcspi4_clkctrl = 0x4a009108, | |
655 | .cm_l4per_gpio7_clkctrl = 0x4a009110, | |
656 | .cm_l4per_gpio8_clkctrl = 0x4a009118, | |
657 | .cm_l4per_mmcsd3_clkctrl = 0x4a009120, | |
658 | .cm_l4per_mmcsd4_clkctrl = 0x4a009128, | |
659 | .cm_l4per_msprohg_clkctrl = 0x4a009130, | |
660 | .cm_l4per_slimbus2_clkctrl = 0x4a009138, | |
661 | .cm_l4per_uart1_clkctrl = 0x4a009140, | |
662 | .cm_l4per_uart2_clkctrl = 0x4a009148, | |
663 | .cm_l4per_uart3_clkctrl = 0x4a009150, | |
664 | .cm_l4per_uart4_clkctrl = 0x4a009158, | |
665 | .cm_l4per_mmcsd5_clkctrl = 0x4a009160, | |
666 | .cm_l4per_i2c5_clkctrl = 0x4a009168, | |
667 | .cm_l4per_uart5_clkctrl = 0x4a009170, | |
668 | .cm_l4per_uart6_clkctrl = 0x4a009178, | |
669 | .cm_l4sec_clkstctrl = 0x4a009180, | |
670 | .cm_l4sec_staticdep = 0x4a009184, | |
671 | .cm_l4sec_dynamicdep = 0x4a009188, | |
672 | .cm_l4sec_aes1_clkctrl = 0x4a0091a0, | |
673 | .cm_l4sec_aes2_clkctrl = 0x4a0091a8, | |
674 | .cm_l4sec_des3des_clkctrl = 0x4a0091b0, | |
675 | .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8, | |
676 | .cm_l4sec_rng_clkctrl = 0x4a0091c0, | |
677 | .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8, | |
678 | .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8, | |
679 | ||
680 | /* cm2.ivahd */ | |
681 | .cm_ivahd_clkstctrl = 0x4a009200, | |
682 | .cm_ivahd_ivahd_clkctrl = 0x4a009220, | |
683 | .cm_ivahd_sl2_clkctrl = 0x4a009228, | |
684 | ||
685 | /* cm2.cam */ | |
686 | .cm_cam_clkstctrl = 0x4a009300, | |
687 | .cm_cam_iss_clkctrl = 0x4a009320, | |
688 | .cm_cam_fdif_clkctrl = 0x4a009328, | |
689 | ||
690 | /* cm2.dss */ | |
691 | .cm_dss_clkstctrl = 0x4a009400, | |
692 | .cm_dss_dss_clkctrl = 0x4a009420, | |
693 | ||
694 | /* cm2.sgx */ | |
695 | .cm_sgx_clkstctrl = 0x4a009500, | |
696 | .cm_sgx_sgx_clkctrl = 0x4a009520, | |
697 | ||
698 | /* cm2.l3init */ | |
699 | .cm_l3init_clkstctrl = 0x4a009600, | |
700 | ||
701 | /* cm2.l3init */ | |
702 | .cm_l3init_hsmmc1_clkctrl = 0x4a009628, | |
703 | .cm_l3init_hsmmc2_clkctrl = 0x4a009630, | |
704 | .cm_l3init_hsi_clkctrl = 0x4a009638, | |
705 | .cm_l3init_hsusbhost_clkctrl = 0x4a009658, | |
706 | .cm_l3init_hsusbotg_clkctrl = 0x4a009660, | |
707 | .cm_l3init_hsusbtll_clkctrl = 0x4a009668, | |
708 | .cm_l3init_p1500_clkctrl = 0x4a009678, | |
709 | .cm_l3init_fsusb_clkctrl = 0x4a0096d0, | |
710 | .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, | |
711 | ||
712 | /* l4 wkup regs */ | |
713 | .cm_abe_pll_ref_clksel = 0x4ae0610c, | |
714 | .cm_sys_clksel = 0x4ae06110, | |
715 | .cm_wkup_clkstctrl = 0x4ae07900, | |
716 | .cm_wkup_l4wkup_clkctrl = 0x4ae07920, | |
717 | .cm_wkup_wdtimer1_clkctrl = 0x4ae07928, | |
718 | .cm_wkup_wdtimer2_clkctrl = 0x4ae07930, | |
719 | .cm_wkup_gpio1_clkctrl = 0x4ae07938, | |
720 | .cm_wkup_gptimer1_clkctrl = 0x4ae07940, | |
721 | .cm_wkup_gptimer12_clkctrl = 0x4ae07948, | |
722 | .cm_wkup_synctimer_clkctrl = 0x4ae07950, | |
723 | .cm_wkup_usim_clkctrl = 0x4ae07958, | |
724 | .cm_wkup_sarram_clkctrl = 0x4ae07960, | |
725 | .cm_wkup_keyboard_clkctrl = 0x4ae07978, | |
726 | .cm_wkup_rtc_clkctrl = 0x4ae07980, | |
727 | .cm_wkup_bandgap_clkctrl = 0x4ae07988, | |
728 | .cm_wkupaon_scrm_clkctrl = 0x4ae07990, | |
d4d986ee | 729 | .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, |
d4e4129c LV |
730 | .prm_rstctrl = 0x4ae07c00, |
731 | .prm_rstst = 0x4ae07c04, | |
0b1b60c7 | 732 | .prm_rsttime = 0x4ae07c08, |
afc2f9dc S |
733 | .prm_vc_val_bypass = 0x4ae07ca0, |
734 | .prm_vc_cfg_i2c_mode = 0x4ae07cb4, | |
735 | .prm_vc_cfg_i2c_clk = 0x4ae07cb8, | |
736 | ||
737 | .prm_sldo_core_setup = 0x4ae07cc4, | |
738 | .prm_sldo_core_ctrl = 0x4ae07cc8, | |
739 | .prm_sldo_mpu_setup = 0x4ae07ccc, | |
740 | .prm_sldo_mpu_ctrl = 0x4ae07cd0, | |
741 | .prm_sldo_mm_setup = 0x4ae07cd4, | |
742 | .prm_sldo_mm_ctrl = 0x4ae07cd8, | |
743 | }; | |
d4e4129c LV |
744 | |
745 | struct prcm_regs const dra7xx_prcm = { | |
746 | /* cm1.ckgen */ | |
747 | .cm_clksel_core = 0x4a005100, | |
748 | .cm_clksel_abe = 0x4a005108, | |
749 | .cm_dll_ctrl = 0x4a005110, | |
750 | .cm_clkmode_dpll_core = 0x4a005120, | |
751 | .cm_idlest_dpll_core = 0x4a005124, | |
752 | .cm_autoidle_dpll_core = 0x4a005128, | |
753 | .cm_clksel_dpll_core = 0x4a00512c, | |
754 | .cm_div_m2_dpll_core = 0x4a005130, | |
755 | .cm_div_m3_dpll_core = 0x4a005134, | |
756 | .cm_div_h11_dpll_core = 0x4a005138, | |
757 | .cm_div_h12_dpll_core = 0x4a00513c, | |
758 | .cm_div_h13_dpll_core = 0x4a005140, | |
759 | .cm_div_h14_dpll_core = 0x4a005144, | |
760 | .cm_ssc_deltamstep_dpll_core = 0x4a005148, | |
761 | .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c, | |
762 | .cm_div_h21_dpll_core = 0x4a005150, | |
763 | .cm_div_h22_dpllcore = 0x4a005154, | |
764 | .cm_div_h23_dpll_core = 0x4a005158, | |
765 | .cm_div_h24_dpll_core = 0x4a00515c, | |
766 | .cm_clkmode_dpll_mpu = 0x4a005160, | |
767 | .cm_idlest_dpll_mpu = 0x4a005164, | |
768 | .cm_autoidle_dpll_mpu = 0x4a005168, | |
769 | .cm_clksel_dpll_mpu = 0x4a00516c, | |
770 | .cm_div_m2_dpll_mpu = 0x4a005170, | |
771 | .cm_ssc_deltamstep_dpll_mpu = 0x4a005188, | |
772 | .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c, | |
773 | .cm_bypclk_dpll_mpu = 0x4a00519c, | |
774 | .cm_clkmode_dpll_iva = 0x4a0051a0, | |
775 | .cm_idlest_dpll_iva = 0x4a0051a4, | |
776 | .cm_autoidle_dpll_iva = 0x4a0051a8, | |
777 | .cm_clksel_dpll_iva = 0x4a0051ac, | |
778 | .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8, | |
779 | .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc, | |
780 | .cm_bypclk_dpll_iva = 0x4a0051dc, | |
781 | .cm_clkmode_dpll_abe = 0x4a0051e0, | |
782 | .cm_idlest_dpll_abe = 0x4a0051e4, | |
783 | .cm_autoidle_dpll_abe = 0x4a0051e8, | |
784 | .cm_clksel_dpll_abe = 0x4a0051ec, | |
785 | .cm_div_m2_dpll_abe = 0x4a0051f0, | |
786 | .cm_div_m3_dpll_abe = 0x4a0051f4, | |
787 | .cm_ssc_deltamstep_dpll_abe = 0x4a005208, | |
788 | .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c, | |
789 | .cm_clkmode_dpll_ddrphy = 0x4a005210, | |
790 | .cm_idlest_dpll_ddrphy = 0x4a005214, | |
791 | .cm_autoidle_dpll_ddrphy = 0x4a005218, | |
792 | .cm_clksel_dpll_ddrphy = 0x4a00521c, | |
793 | .cm_div_m2_dpll_ddrphy = 0x4a005220, | |
794 | .cm_div_h11_dpll_ddrphy = 0x4a005228, | |
795 | .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, | |
796 | .cm_clkmode_dpll_dsp = 0x4a005234, | |
797 | .cm_shadow_freq_config1 = 0x4a005260, | |
798 | ||
799 | /* cm1.mpu */ | |
800 | .cm_mpu_mpu_clkctrl = 0x4a005320, | |
801 | ||
802 | /* cm1.dsp */ | |
803 | .cm_dsp_clkstctrl = 0x4a005400, | |
804 | .cm_dsp_dsp_clkctrl = 0x4a005420, | |
805 | ||
806 | /* cm2.ckgen */ | |
807 | .cm_clksel_usb_60mhz = 0x4a008104, | |
808 | .cm_clkmode_dpll_per = 0x4a008140, | |
809 | .cm_idlest_dpll_per = 0x4a008144, | |
810 | .cm_autoidle_dpll_per = 0x4a008148, | |
811 | .cm_clksel_dpll_per = 0x4a00814c, | |
812 | .cm_div_m2_dpll_per = 0x4a008150, | |
813 | .cm_div_m3_dpll_per = 0x4a008154, | |
814 | .cm_div_h11_dpll_per = 0x4a008158, | |
815 | .cm_div_h12_dpll_per = 0x4a00815c, | |
816 | .cm_div_h13_dpll_per = 0x4a008160, | |
817 | .cm_div_h14_dpll_per = 0x4a008164, | |
818 | .cm_ssc_deltamstep_dpll_per = 0x4a008168, | |
819 | .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, | |
820 | .cm_clkmode_dpll_usb = 0x4a008180, | |
821 | .cm_idlest_dpll_usb = 0x4a008184, | |
822 | .cm_autoidle_dpll_usb = 0x4a008188, | |
823 | .cm_clksel_dpll_usb = 0x4a00818c, | |
824 | .cm_div_m2_dpll_usb = 0x4a008190, | |
825 | .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, | |
826 | .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, | |
827 | .cm_clkdcoldo_dpll_usb = 0x4a0081b4, | |
828 | .cm_clkmode_dpll_pcie_ref = 0x4a008200, | |
829 | .cm_clkmode_apll_pcie = 0x4a00821c, | |
830 | .cm_idlest_apll_pcie = 0x4a008220, | |
831 | .cm_div_m2_apll_pcie = 0x4a008224, | |
832 | .cm_clkvcoldo_apll_pcie = 0x4a008228, | |
833 | ||
834 | /* cm2.core */ | |
835 | .cm_l3_1_clkstctrl = 0x4a008700, | |
836 | .cm_l3_1_dynamicdep = 0x4a008708, | |
837 | .cm_l3_1_l3_1_clkctrl = 0x4a008720, | |
838 | .cm_l3_gpmc_clkctrl = 0x4a008728, | |
839 | .cm_mpu_m3_clkstctrl = 0x4a008900, | |
840 | .cm_mpu_m3_staticdep = 0x4a008904, | |
841 | .cm_mpu_m3_dynamicdep = 0x4a008908, | |
842 | .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, | |
843 | .cm_sdma_clkstctrl = 0x4a008a00, | |
844 | .cm_sdma_staticdep = 0x4a008a04, | |
845 | .cm_sdma_dynamicdep = 0x4a008a08, | |
846 | .cm_sdma_sdma_clkctrl = 0x4a008a20, | |
847 | .cm_memif_clkstctrl = 0x4a008b00, | |
848 | .cm_memif_dmm_clkctrl = 0x4a008b20, | |
849 | .cm_memif_emif_fw_clkctrl = 0x4a008b28, | |
850 | .cm_memif_emif_1_clkctrl = 0x4a008b30, | |
851 | .cm_memif_emif_2_clkctrl = 0x4a008b38, | |
852 | .cm_memif_dll_clkctrl = 0x4a008b40, | |
853 | .cm_l4cfg_clkstctrl = 0x4a008d00, | |
854 | .cm_l4cfg_dynamicdep = 0x4a008d08, | |
855 | .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, | |
856 | .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, | |
857 | .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, | |
858 | .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, | |
859 | .cm_l3instr_clkstctrl = 0x4a008e00, | |
860 | .cm_l3instr_l3_3_clkctrl = 0x4a008e20, | |
861 | .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, | |
862 | .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, | |
863 | ||
864 | /* cm2.ivahd */ | |
865 | .cm_ivahd_clkstctrl = 0x4a008f00, | |
866 | .cm_ivahd_ivahd_clkctrl = 0x4a008f20, | |
867 | .cm_ivahd_sl2_clkctrl = 0x4a008f28, | |
868 | ||
869 | /* cm2.cam */ | |
870 | .cm_cam_clkstctrl = 0x4a009000, | |
871 | .cm_cam_vip1_clkctrl = 0x4a009020, | |
872 | .cm_cam_vip2_clkctrl = 0x4a009028, | |
873 | .cm_cam_vip3_clkctrl = 0x4a009030, | |
874 | .cm_cam_lvdsrx_clkctrl = 0x4a009038, | |
875 | .cm_cam_csi1_clkctrl = 0x4a009040, | |
876 | .cm_cam_csi2_clkctrl = 0x4a009048, | |
877 | ||
878 | /* cm2.dss */ | |
879 | .cm_dss_clkstctrl = 0x4a009100, | |
880 | .cm_dss_dss_clkctrl = 0x4a009120, | |
881 | ||
882 | /* cm2.sgx */ | |
883 | .cm_sgx_clkstctrl = 0x4a009200, | |
884 | .cm_sgx_sgx_clkctrl = 0x4a009220, | |
885 | ||
886 | /* cm2.l3init */ | |
887 | .cm_l3init_clkstctrl = 0x4a009300, | |
888 | ||
889 | /* cm2.l3init */ | |
890 | .cm_l3init_hsmmc1_clkctrl = 0x4a009328, | |
891 | .cm_l3init_hsmmc2_clkctrl = 0x4a009330, | |
892 | .cm_l3init_hsusbhost_clkctrl = 0x4a009340, | |
893 | .cm_l3init_hsusbotg_clkctrl = 0x4a009348, | |
894 | .cm_l3init_hsusbtll_clkctrl = 0x4a009350, | |
895 | .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, | |
896 | ||
897 | /* cm2.l4per */ | |
898 | .cm_l4per_clkstctrl = 0x4a009700, | |
899 | .cm_l4per_dynamicdep = 0x4a009708, | |
900 | .cm_l4per_gptimer10_clkctrl = 0x4a009728, | |
901 | .cm_l4per_gptimer11_clkctrl = 0x4a009730, | |
902 | .cm_l4per_gptimer2_clkctrl = 0x4a009738, | |
903 | .cm_l4per_gptimer3_clkctrl = 0x4a009740, | |
904 | .cm_l4per_gptimer4_clkctrl = 0x4a009748, | |
905 | .cm_l4per_gptimer9_clkctrl = 0x4a009750, | |
906 | .cm_l4per_elm_clkctrl = 0x4a009758, | |
907 | .cm_l4per_gpio2_clkctrl = 0x4a009760, | |
908 | .cm_l4per_gpio3_clkctrl = 0x4a009768, | |
909 | .cm_l4per_gpio4_clkctrl = 0x4a009770, | |
910 | .cm_l4per_gpio5_clkctrl = 0x4a009778, | |
911 | .cm_l4per_gpio6_clkctrl = 0x4a009780, | |
912 | .cm_l4per_hdq1w_clkctrl = 0x4a009788, | |
913 | .cm_l4per_i2c1_clkctrl = 0x4a0097a0, | |
914 | .cm_l4per_i2c2_clkctrl = 0x4a0097a8, | |
915 | .cm_l4per_i2c3_clkctrl = 0x4a0097b0, | |
916 | .cm_l4per_i2c4_clkctrl = 0x4a0097b8, | |
917 | .cm_l4per_l4per_clkctrl = 0x4a0097c0, | |
918 | .cm_l4per_mcspi1_clkctrl = 0x4a0097f0, | |
919 | .cm_l4per_mcspi2_clkctrl = 0x4a0097f8, | |
920 | .cm_l4per_mcspi3_clkctrl = 0x4a009800, | |
921 | .cm_l4per_mcspi4_clkctrl = 0x4a009808, | |
922 | .cm_l4per_gpio7_clkctrl = 0x4a009810, | |
923 | .cm_l4per_gpio8_clkctrl = 0x4a009818, | |
924 | .cm_l4per_mmcsd3_clkctrl = 0x4a009820, | |
925 | .cm_l4per_mmcsd4_clkctrl = 0x4a009828, | |
926 | .cm_l4per_uart1_clkctrl = 0x4a009840, | |
927 | .cm_l4per_uart2_clkctrl = 0x4a009848, | |
928 | .cm_l4per_uart3_clkctrl = 0x4a009850, | |
929 | .cm_l4per_uart4_clkctrl = 0x4a009858, | |
930 | .cm_l4per_uart5_clkctrl = 0x4a009870, | |
931 | .cm_l4sec_clkstctrl = 0x4a009880, | |
932 | .cm_l4sec_staticdep = 0x4a009884, | |
933 | .cm_l4sec_dynamicdep = 0x4a009888, | |
934 | .cm_l4sec_aes1_clkctrl = 0x4a0098a0, | |
935 | .cm_l4sec_aes2_clkctrl = 0x4a0098a8, | |
936 | .cm_l4sec_des3des_clkctrl = 0x4a0098b0, | |
937 | .cm_l4sec_rng_clkctrl = 0x4a0098c0, | |
938 | .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8, | |
939 | .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8, | |
940 | ||
941 | /* l4 wkup regs */ | |
942 | .cm_abe_pll_ref_clksel = 0x4ae0610c, | |
943 | .cm_sys_clksel = 0x4ae06110, | |
944 | .cm_wkup_clkstctrl = 0x4ae07800, | |
945 | .cm_wkup_l4wkup_clkctrl = 0x4ae07820, | |
946 | .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, | |
947 | .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, | |
948 | .cm_wkup_gpio1_clkctrl = 0x4ae07838, | |
949 | .cm_wkup_gptimer1_clkctrl = 0x4ae07840, | |
950 | .cm_wkup_gptimer12_clkctrl = 0x4ae07848, | |
951 | .cm_wkup_sarram_clkctrl = 0x4ae07860, | |
952 | .cm_wkup_keyboard_clkctrl = 0x4ae07878, | |
953 | .cm_wkupaon_scrm_clkctrl = 0x4ae07890, | |
954 | .prm_rstctrl = 0x4ae07d00, | |
955 | .prm_rstst = 0x4ae07d04, | |
0b1b60c7 | 956 | .prm_rsttime = 0x4ae07d08, |
d4e4129c LV |
957 | .prm_vc_val_bypass = 0x4ae07da0, |
958 | .prm_vc_cfg_i2c_mode = 0x4ae07db4, | |
959 | .prm_vc_cfg_i2c_clk = 0x4ae07db8, | |
960 | }; |