[people/ms/u-boot.git] / arch / arm / cpu / armv7 / socfpga / spl.c

/*
 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <version.h>
#include <image.h>
#include <asm/arch/reset_manager.h>
#include <spl.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/freeze_controller.h>

DECLARE_GLOBAL_DATA_PTR;

u32 spl_boot_device(void)
{
	return BOOT_DEVICE_RAM;
}

/*
 * Board initialization after bss clearance
 */
void spl_board_init(void)
{
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
	cm_config_t cm_default_cfg = {
		/* main group */
		MAIN_VCO_BASE,
		CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
			CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
		CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
			CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
			CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
			CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
			CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
			CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
			CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
		CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
			CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
		CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
			CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),

		/* peripheral group */
		PERI_VCO_BASE,
		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
			CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
			CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
			CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
			CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
		CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
			CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
			CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
		CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
			CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
		CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
			CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
		CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
			CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
		CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
			CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
			CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
		CLKMGR_PERPLLGRP_SRC_QSPI_SET(
			CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
		CLKMGR_PERPLLGRP_SRC_NAND_SET(
			CONFIG_HPS_PERPLLGRP_SRC_NAND) |
		CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
			CONFIG_HPS_PERPLLGRP_SRC_SDMMC),

		/* sdram pll group */
		SDR_VCO_BASE,
		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
	};

	debug("Freezing all I/O banks\n");
	/* freeze all IO banks */
	sys_mgr_frzctrl_freeze_req();

	debug("Reconfigure Clock Manager\n");
	/* reconfigure the PLLs */
	cm_basic_init(&cm_default_cfg);

	/* configure the IOCSR / IO buffer settings */
	if (scan_mgr_configure_iocsr())
		hang();

	/* configure the pin muxing through system manager */
	sysmgr_pinmux_init();
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */

	/* de-assert reset for peripherals and bridges based on handoff */
	reset_deassert_peripherals_handoff();

	debug("Unfreezing/Thaw all I/O banks\n");
	/* unfreeze / thaw all IO banks */
	sys_mgr_frzctrl_thaw_req();

	/* enable console uart printing */
	preloader_console_init();
}
Commit	Line	Data
77754408 DN	1	/*
	2	* Copyright (C) 2012 Altera Corporation <www.altera.com>
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
77754408 DN	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <asm/u-boot.h>
	10	#include <asm/utils.h>
	11	#include <version.h>
	12	#include <image.h>
77754408 DN	13	#include <asm/arch/reset_manager.h>
77754408 DN	14	#include <spl.h>
5d649d2b	15	#include <asm/arch/system_manager.h>
4c544197	16	#include <asm/arch/freeze_controller.h>
77754408 DN	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
	20	u32 spl_boot_device(void)
	21	{
	22	return BOOT_DEVICE_RAM;
	23	}
	24
	25	/*
	26	* Board initialization after bss clearance
	27	*/
	28	void spl_board_init(void)
	29	{
5d649d2b	30	#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
ddfeb0aa CLS	31	cm_config_t cm_default_cfg = {
	32	/* main group */
	33	MAIN_VCO_BASE,
	34	CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
	35	CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
	36	CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
	37	CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
	38	CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
	39	CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
	40	CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
	41	CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
	42	CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
	43	CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
	44	CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
	45	CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
	46	CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
	47	CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) \|
	48	CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
	49	CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) \|
	50	CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
	51	CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) \|
	52	CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
	53	CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
	54	CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
	55	CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) \|
	56	CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
	57	CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
	58	CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
	59	CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
	60	CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
	61	CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) \|
	62	CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
	63	CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
	64
	65	/* peripheral group */
	66	PERI_VCO_BASE,
	67	CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
	68	CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
	69	CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
	70	CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
	71	CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
	72	CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
	73	CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
	74	CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
	75	CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
	76	CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
	77	CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
	78	CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
	79	CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
	80	CONFIG_HPS_PERPLLGRP_DIV_USBCLK) \|
	81	CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
	82	CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) \|
	83	CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
	84	CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) \|
	85	CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
	86	CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
	87	CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
	88	CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
	89	CLKMGR_PERPLLGRP_SRC_QSPI_SET(
	90	CONFIG_HPS_PERPLLGRP_SRC_QSPI) \|
	91	CLKMGR_PERPLLGRP_SRC_NAND_SET(
	92	CONFIG_HPS_PERPLLGRP_SRC_NAND) \|
	93	CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
	94	CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
95
96	/* sdram pll group */
97	SDR_VCO_BASE,
98	CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
99	CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) \|
100	CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
101	CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
102	CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
103	CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) \|
104	CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
105	CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
106	CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
107	CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) \|
108	CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
109	CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
110	CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
111	CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) \|
112	CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
113	CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
114	};
115
4c544197 CLS	116	debug("Freezing all I/O banks\n");
	117	/* freeze all IO banks */
	118	sys_mgr_frzctrl_freeze_req();
	119
ddfeb0aa CLS	120	debug("Reconfigure Clock Manager\n");
	121	/* reconfigure the PLLs */
	122	cm_basic_init(&cm_default_cfg);
	123
dc4d4aa1 CLS	124	/* configure the IOCSR / IO buffer settings */
	125	if (scan_mgr_configure_iocsr())
	126	hang();
	127
5d649d2b CLS	128	/* configure the pin muxing through system manager */
	129	sysmgr_pinmux_init();
	130	#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
	131
77754408 DN	132	/* de-assert reset for peripherals and bridges based on handoff */
	133	reset_deassert_peripherals_handoff();
	134
4c544197 CLS	135	debug("Unfreezing/Thaw all I/O banks\n");
	136	/* unfreeze / thaw all IO banks */
	137	sys_mgr_frzctrl_thaw_req();
	138
77754408 DN	139	/* enable console uart printing */
	140	preloader_console_init();
	141	}