[people/ms/u-boot.git] / arch / arm / cpu / armv7 / start.S

/*
 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
 *
 * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
 *
 * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
 * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
 * Copyright (c) 2003	Kshitij <kshitij@ti.com>
 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/system.h>
#include <linux/linkage.h>

.globl _start
_start: b	reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq
#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt:	.word _software_interrupt
_prefetch_abort:	.word _prefetch_abort
_data_abort:		.word _data_abort
_not_used:		.word _not_used
_irq:			.word _irq
_fiq:			.word _fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#else
_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#endif	/* CONFIG_SPL_BUILD */

.global _end_vect
_end_vect:

	.balignl 16,0xdeadbeef
/*************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************/

.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _image_copy_end_ofs
_image_copy_end_ofs:
	.word __image_copy_end - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	bl	save_boot_params
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0, cpsr
	bic	r0, r0, #0x1f
	orr	r0, r0, #0xd3
	msr	cpsr,r0

/*
 * Setup vector:
 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
 * Continue to use ROM code vector only in OMAP4 spl)
 */
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
	bic	r0, #CR_V		@ V = 0
	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register

	/* Set vector address in CP15 VBAR register */
	ldr	r0, =_start
	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
#endif

	/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_cp15
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

#ifndef CONFIG_SPL_BUILD
/*
 * void relocate_code(addr_moni)
 *
 * This function relocates the monitor code.
 */
ENTRY(relocate_code)
	mov	r6, r0	/* save addr of destination */

	adr	r0, _start
	subs	r9, r6, r0		/* r9 <- relocation offset */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _image_copy_end_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop

relocate_done:

	bx	lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start
ENDPROC(relocate_code)

#endif

ENTRY(c_runtime_cpu_setup)
/*
 * If I-cache is enabled invalidate it
 */
#ifndef CONFIG_SYS_ICACHE_OFF
	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c5, 4	@ ISB
#endif
/*
 * Move vector table
 */
#if !defined(CONFIG_TEGRA)
	/* Set vector address in CP15 VBAR register */
	ldr     r0, =_start
	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
#endif /* !Tegra */

	bx	lr

ENDPROC(c_runtime_cpu_setup)

/*************************************************************************
 *
 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
 *	__attribute__((weak));
 *
 * Stack pointer is not yet initialized at this moment
 * Don't save anything to stack even if compiled with -O0
 *
 *************************************************************************/
ENTRY(save_boot_params)
	bx	lr			@ back to my caller
ENDPROC(save_boot_params)
	.weak	save_boot_params

/*************************************************************************
 *
 * cpu_init_cp15
 *
 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
 * CONFIG_SYS_ICACHE_OFF is defined.
 *
 *************************************************************************/
ENTRY(cpu_init_cp15)
	/*
	 * Invalidate L1 I/D
	 */
	mov	r0, #0			@ set up for MCR
	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c5, 4	@ ISB

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
#ifdef CONFIG_SYS_ICACHE_OFF
	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
#else
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
#endif
	mcr	p15, 0, r0, c1, c0, 0

#ifdef CONFIG_ARM_ERRATA_716044
	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
	orr	r0, r0, #1 << 11	@ set bit #11
	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
#endif

#ifdef CONFIG_ARM_ERRATA_742230
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 4		@ set bit #4
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

#ifdef CONFIG_ARM_ERRATA_743622
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 6		@ set bit #6
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

#ifdef CONFIG_ARM_ERRATA_751472
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 11	@ set bit #11
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

	mov	pc, lr			@ back to my caller
ENDPROC(cpu_init_cp15)

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************/
ENTRY(cpu_init_crit)
	/*
	 * Jump to board specific initialization...
	 * The Mask ROM will have already initialized
	 * basic memory. Go here to bump up clock rate and handle
	 * wake up conditions.
	 */
	b	lowlevel_init		@ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif

#ifndef CONFIG_SPL_BUILD
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
						@ user stack
	stmia	sp, {r0 - r12}			@ Save user registers (now in
						@ svc mode) r0-r12
	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
						@ stack
	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
						@ and cpsr (into parm regs)
	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp				@ save current stack into r0
						@ (param register)
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
						@ a reserved stack spot would
						@ be good.
	stmdb	r8, {sp, lr}^			@ Calling SP, LR
	str	lr, [r8, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]			@ Save CPSR
	str	r0, [r8, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into
						@ cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
						@ in banked mode)

	str	lr, [r13]			@ save caller lr in position 0
						@ of saved stack
	mrs	lr, spsr			@ get the spsr
	str	lr, [r13, #4]			@ save spsr in position 1 of
						@ saved stack

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13			@ switch modes, make sure
						@ moves will execute
	mov	lr, pc				@ capture return pc
	movs	pc, lr				@ jump to next instruction &
						@ switch modes.
	.endm

	.macro get_bad_stack_swi
	sub	r13, r13, #4			@ space on current stack for
						@ scratch reg.
	str	r0, [r13]			@ save R0's value.
	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
						@ spots for abort stack
	str	lr, [r0]			@ save caller lr in position 0
						@ of saved stack
	mrs	r0, spsr			@ get the spsr
	str	lr, [r0, #4]			@ save spsr in position 1 of
						@ saved stack
	ldr	r0, [r13]			@ restore r0
	add	r13, r13, #4			@ pop stack entry
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack_swi
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effective fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif /* CONFIG_USE_IRQ */
#endif /* CONFIG_SPL_BUILD */
Commit	Line	Data
0b02b184 DB	1	/*
	2	* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
	3	*
	4	* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
	5	*
	6	* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
	7	* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
792a09eb	8	* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
0b02b184 DB	9	* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
	10	* Copyright (c) 2003 Kshitij <kshitij@ti.com>
	11	* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
	12	*
	13	* See file CREDITS for list of people who contributed to this
	14	* project.
	15	*
	16	* This program is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of
	19	* the License, or (at your option) any later version.
	20	*
	21	* This program is distributed in the hope that it will be useful,
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* You should have received a copy of the GNU General Public License
	27	* along with this program; if not, write to the Free Software
	28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	29	* MA 02111-1307 USA
	30	*/
	31
25ddd1fb	32	#include <asm-offsets.h>
0b02b184 DB	33	#include <config.h>
0b02b184 DB	34	#include <version.h>
a8c68639	35	#include <asm/system.h>
74236aca	36	#include <linux/linkage.h>
0b02b184 DB	37
	38	.globl _start
	39	_start: b reset
	40	ldr pc, _undefined_instruction
	41	ldr pc, _software_interrupt
	42	ldr pc, _prefetch_abort
	43	ldr pc, _data_abort
	44	ldr pc, _not_used
	45	ldr pc, _irq
	46	ldr pc, _fiq
033ca724 A	47	#ifdef CONFIG_SPL_BUILD
	48	_undefined_instruction: .word _undefined_instruction
	49	_software_interrupt: .word _software_interrupt
	50	_prefetch_abort: .word _prefetch_abort
	51	_data_abort: .word _data_abort
	52	_not_used: .word _not_used
	53	_irq: .word _irq
	54	_fiq: .word _fiq
	55	_pad: .word 0x12345678 /* now 164=64 /
	56	#else
0b02b184 DB	57	_undefined_instruction: .word undefined_instruction
	58	_software_interrupt: .word software_interrupt
	59	_prefetch_abort: .word prefetch_abort
	60	_data_abort: .word data_abort
	61	_not_used: .word not_used
	62	_irq: .word irq
	63	_fiq: .word fiq
	64	_pad: .word 0x12345678 /* now 164=64 /
033ca724 A	65	#endif /* CONFIG_SPL_BUILD */
033ca724 A	66
0b02b184 DB	67	.global _end_vect
	68	_end_vect:
	69
	70	.balignl 16,0xdeadbeef
	71	/*************************************************************************
	72	*
	73	* Startup Code (reset vector)
	74	*
	75	* do important init only if we don't start from memory!
	76	* setup Memory and board specific bits prior to relocation.
	77	* relocate armboot to ram
	78	* setup stack
	79	*
	80	*************************************************************************/
	81
561142af	82	.globl _TEXT_BASE
0b02b184	83	_TEXT_BASE:
508611bc BT	84	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	85	.word CONFIG_SPL_TEXT_BASE
	86	#else
14d0a02a	87	.word CONFIG_SYS_TEXT_BASE
508611bc	88	#endif
0b02b184	89
0b02b184 DB	90	/*
	91	* These are defined in the board-specific linker script.
	92	*/
c3d3a541 HS	93	.globl _bss_start_ofs
	94	_bss_start_ofs:
	95	.word __bss_start - _start
0b02b184	96
7086e91b	97	.globl _image_copy_end_ofs
033ca724	98	_image_copy_end_ofs:
7086e91b	99	.word __image_copy_end - _start
033ca724	100
c3d3a541 HS	101	.globl _bss_end_ofs
c3d3a541 HS	102	_bss_end_ofs:
3929fb0a	103	.word __bss_end - _start
0b02b184	104
f326cbba PYC	105	.globl _end_ofs
	106	_end_ofs:
	107	.word _end - _start
	108
0b02b184 DB	109	#ifdef CONFIG_USE_IRQ
	110	/* IRQ stack memory (calculated at run-time) */
	111	.globl IRQ_STACK_START
	112	IRQ_STACK_START:
	113	.word 0x0badc0de
	114
	115	/* IRQ stack memory (calculated at run-time) */
	116	.globl FIQ_STACK_START
	117	FIQ_STACK_START:
	118	.word 0x0badc0de
	119	#endif
	120
561142af HS	121	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	122	.globl IRQ_STACK_START_IN
	123	IRQ_STACK_START_IN:
	124	.word 0x0badc0de
	125
561142af HS	126	/*
	127	* the actual reset code
	128	*/
	129
	130	reset:
8cf686e1	131	bl save_boot_params
561142af HS	132	/*
	133	* set the cpu to SVC32 mode
	134	*/
	135	mrs r0, cpsr
	136	bic r0, r0, #0x1f
	137	orr r0, r0, #0xd3
	138	msr cpsr,r0
	139
a8c68639 A	140	/*
	141	* Setup vector:
	142	* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
	143	* Continue to use ROM code vector only in OMAP4 spl)
	144	*/
	145	#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
	146	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
	147	mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
	148	bic r0, #CR_V @ V = 0
	149	mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
	150
	151	/* Set vector address in CP15 VBAR register */
	152	ldr r0, =_start
	153	mcr p15, 0, r0, c12, c0, 0 @Set VBAR
	154	#endif
	155
561142af HS	156	/* the mask ROM code should have PLL and others stable */
561142af HS	157	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
80433c9a	158	bl cpu_init_cp15
561142af HS	159	bl cpu_init_crit
	160	#endif
	161
e05e5de7	162	bl _main
561142af HS	163
	164	/------------------------------------------------------------------------------/
	165
6507f133	166	#ifndef CONFIG_SPL_BUILD
561142af	167	/*
5c6db120	168	* void relocate_code(addr_moni)
561142af	169	*
959eaa74	170	* This function relocates the monitor code.
561142af	171	*/
74236aca	172	ENTRY(relocate_code)
5c6db120	173	mov r6, r0 /* save addr of destination */
561142af	174
561142af	175	adr r0, _start
4b3db1cd	176	subs r9, r6, r0 /* r9 <- relocation offset */
e05e5de7	177	beq relocate_done /* skip relocation */
a1a47d3c	178	mov r1, r6 /* r1 <- scratch for copy_loop */
033ca724	179	ldr r3, _image_copy_end_ofs
a1a47d3c	180	add r2, r0, r3 /* r2 <- source end address */
561142af HS	181
561142af HS	182	copy_loop:
4b3db1cd BT	183	ldmia r0!, {r10-r11} /* copy from source address [r0] */
4b3db1cd BT	184	stmia r1!, {r10-r11} /* copy to target address [r1] */
da90d4ce AA	185	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	186	blo copy_loop
561142af	187
c3d3a541 HS	188	/*
	189	* fix .rel.dyn relocations
	190	*/
	191	ldr r0, _TEXT_BASE /* r0 <- Text base */
c3d3a541 HS	192	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	193	add r10, r10, r0 /* r10 <- sym table in FLASH */
	194	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	195	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	196	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	197	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
561142af	198	fixloop:
8c0c2b90 GR	199	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
8c0c2b90 GR	200	add r0, r0, r9 /* r0 <- location to fix up in RAM */
c3d3a541	201	ldr r1, [r2, #4]
1f52d89f AB	202	and r7, r1, #0xff
1f52d89f AB	203	cmp r7, #23 /* relative fixup? */
c3d3a541	204	beq fixrel
1f52d89f	205	cmp r7, #2 /* absolute fixup? */
c3d3a541 HS	206	beq fixabs
	207	/* ignore unknown type of fixup */
	208	b fixnext
	209	fixabs:
	210	/* absolute fix: set location to (offset) symbol value */
	211	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	212	add r1, r10, r1 /* r1 <- address of symbol in table */
	213	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	214	add r1, r1, r9 /* r1 <- relocated sym addr */
c3d3a541 HS	215	b fixnext
	216	fixrel:
	217	/* relative fix: increase location by offset */
	218	ldr r1, [r0]
	219	add r1, r1, r9
	220	fixnext:
	221	str r1, [r0]
8c0c2b90	222	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
561142af	223	cmp r2, r3
c3d3a541	224	blo fixloop
e05e5de7 AA	225
	226	relocate_done:
	227
	228	bx lr
	229
033ca724 A	230	_rel_dyn_start_ofs:
	231	.word __rel_dyn_start - _start
	232	_rel_dyn_end_ofs:
	233	.word __rel_dyn_end - _start
	234	_dynsym_start_ofs:
	235	.word __dynsym_start - _start
e05e5de7	236	ENDPROC(relocate_code)
033ca724	237
e05e5de7	238	#endif
561142af	239
e05e5de7	240	ENTRY(c_runtime_cpu_setup)
c2dd0d45 A	241	/*
	242	* If I-cache is enabled invalidate it
	243	*/
	244	#ifndef CONFIG_SYS_ICACHE_OFF
	245	mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
	246	mcr p15, 0, r0, c7, c10, 4 @ DSB
	247	mcr p15, 0, r0, c7, c5, 4 @ ISB
	248	#endif
f8b9d1d3 TK	249	/*
	250	* Move vector table
	251	*/
6d6c0bae	252	#if !defined(CONFIG_TEGRA)
f8b9d1d3 TK	253	/* Set vector address in CP15 VBAR register */
f8b9d1d3 TK	254	ldr r0, =_start
f8b9d1d3	255	mcr p15, 0, r0, c12, c0, 0 @Set VBAR
6d6c0bae	256	#endif /* !Tegra */
f8b9d1d3	257
e05e5de7 AA	258	bx lr
	259
	260	ENDPROC(c_runtime_cpu_setup)
c3d3a541	261
6f0dba85 TK	262	/*************************************************************************
	263	*
	264	* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
	265	* __attribute__((weak));
	266	*
	267	* Stack pointer is not yet initialized at this moment
	268	* Don't save anything to stack even if compiled with -O0
	269	*
	270	*************************************************************************/
	271	ENTRY(save_boot_params)
	272	bx lr @ back to my caller
	273	ENDPROC(save_boot_params)
	274	.weak save_boot_params
	275
0b02b184 DB	276	/*************************************************************************
0b02b184 DB	277	*
80433c9a	278	* cpu_init_cp15
0b02b184	279	*
80433c9a SG	280	* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
80433c9a SG	281	* CONFIG_SYS_ICACHE_OFF is defined.
0b02b184 DB	282	*
0b02b184 DB	283	*************************************************************************/
74236aca	284	ENTRY(cpu_init_cp15)
0b02b184 DB	285	/*
	286	* Invalidate L1 I/D
	287	*/
	288	mov r0, #0 @ set up for MCR
	289	mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
	290	mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
c2dd0d45 A	291	mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
	292	mcr p15, 0, r0, c7, c10, 4 @ DSB
	293	mcr p15, 0, r0, c7, c5, 4 @ ISB
0b02b184 DB	294
	295	/*
	296	* disable MMU stuff and caches
	297	*/
	298	mrc p15, 0, r0, c1, c0, 0
	299	bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
	300	bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
	301	orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
c2dd0d45 A	302	orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
	303	#ifdef CONFIG_SYS_ICACHE_OFF
	304	bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
	305	#else
	306	orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
	307	#endif
0b02b184	308	mcr p15, 0, r0, c1, c0, 0
0678587f	309
c5d4752c SW	310	#ifdef CONFIG_ARM_ERRATA_716044
	311	mrc p15, 0, r0, c1, c0, 0 @ read system control register
	312	orr r0, r0, #1 << 11 @ set bit #11
	313	mcr p15, 0, r0, c1, c0, 0 @ write system control register
	314	#endif
	315
0678587f SW	316	#ifdef CONFIG_ARM_ERRATA_742230
	317	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	318	orr r0, r0, #1 << 4 @ set bit #4
	319	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	320	#endif
	321
	322	#ifdef CONFIG_ARM_ERRATA_743622
	323	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	324	orr r0, r0, #1 << 6 @ set bit #6
	325	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	326	#endif
	327
	328	#ifdef CONFIG_ARM_ERRATA_751472
	329	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	330	orr r0, r0, #1 << 11 @ set bit #11
	331	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	332	#endif
	333
80433c9a	334	mov pc, lr @ back to my caller
74236aca	335	ENDPROC(cpu_init_cp15)
0b02b184	336
80433c9a SG	337	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	338	/*************************************************************************
	339	*
	340	* CPU_init_critical registers
	341	*
	342	* setup important registers
	343	* setup memory timing
	344	*
	345	*************************************************************************/
74236aca	346	ENTRY(cpu_init_crit)
0b02b184 DB	347	/*
	348	* Jump to board specific initialization...
	349	* The Mask ROM will have already initialized
	350	* basic memory. Go here to bump up clock rate and handle
	351	* wake up conditions.
	352	*/
63ee53a7	353	b lowlevel_init @ go setup pll,mux,memory
74236aca	354	ENDPROC(cpu_init_crit)
22193540	355	#endif
033ca724 A	356
033ca724 A	357	#ifndef CONFIG_SPL_BUILD
0b02b184 DB	358	/*
	359	*************************************************************************
	360	*
	361	* Interrupt handling
	362	*
	363	*************************************************************************
	364	*/
	365	@
	366	@ IRQ stack frame.
	367	@
	368	#define S_FRAME_SIZE 72
	369
	370	#define S_OLD_R0 68
	371	#define S_PSR 64
	372	#define S_PC 60
	373	#define S_LR 56
	374	#define S_SP 52
	375
	376	#define S_IP 48
	377	#define S_FP 44
	378	#define S_R10 40
	379	#define S_R9 36
	380	#define S_R8 32
	381	#define S_R7 28
	382	#define S_R6 24
	383	#define S_R5 20
	384	#define S_R4 16
	385	#define S_R3 12
	386	#define S_R2 8
	387	#define S_R1 4
	388	#define S_R0 0
	389
	390	#define MODE_SVC 0x13
	391	#define I_BIT 0x80
	392
	393	/*
	394	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	395	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	396	*/
	397
	398	.macro bad_save_user_regs
	399	sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
	400	@ user stack
	401	stmia sp, {r0 - r12} @ Save user registers (now in
	402	@ svc mode) r0-r12
561142af	403	ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
0b02b184 DB	404	@ stack
	405	ldmia r2, {r2 - r3} @ get values for "aborted" pc
	406	@ and cpsr (into parm regs)
	407	add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
	408
	409	add r5, sp, #S_SP
	410	mov r1, lr
	411	stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
	412	mov r0, sp @ save current stack into r0
	413	@ (param register)
	414	.endm
	415
	416	.macro irq_save_user_regs
	417	sub sp, sp, #S_FRAME_SIZE
	418	stmia sp, {r0 - r12} @ Calling r0-r12
	419	add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
	420	@ a reserved stack spot would
	421	@ be good.
	422	stmdb r8, {sp, lr}^ @ Calling SP, LR
	423	str lr, [r8, #0] @ Save calling PC
	424	mrs r6, spsr
	425	str r6, [r8, #4] @ Save CPSR
	426	str r0, [r8, #8] @ Save OLD_R0
	427	mov r0, sp
	428	.endm
	429
	430	.macro irq_restore_user_regs
	431	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	432	mov r0, r0
	433	ldr lr, [sp, #S_PC] @ Get PC
	434	add sp, sp, #S_FRAME_SIZE
	435	subs pc, lr, #4 @ return & move spsr_svc into
	436	@ cpsr
	437	.endm
	438
	439	.macro get_bad_stack
561142af HS	440	ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
561142af HS	441	@ in banked mode)
0b02b184 DB	442
	443	str lr, [r13] @ save caller lr in position 0
	444	@ of saved stack
	445	mrs lr, spsr @ get the spsr
	446	str lr, [r13, #4] @ save spsr in position 1 of
	447	@ saved stack
	448
	449	mov r13, #MODE_SVC @ prepare SVC-Mode
	450	@ msr spsr_c, r13
	451	msr spsr, r13 @ switch modes, make sure
	452	@ moves will execute
	453	mov lr, pc @ capture return pc
	454	movs pc, lr @ jump to next instruction &
	455	@ switch modes.
	456	.endm
	457
	458	.macro get_bad_stack_swi
	459	sub r13, r13, #4 @ space on current stack for
	460	@ scratch reg.
	461	str r0, [r13] @ save R0's value.
561142af	462	ldr r0, IRQ_STACK_START_IN @ get data regions start
0b02b184 DB	463	@ spots for abort stack
	464	str lr, [r0] @ save caller lr in position 0
	465	@ of saved stack
	466	mrs r0, spsr @ get the spsr
	467	str lr, [r0, #4] @ save spsr in position 1 of
	468	@ saved stack
	469	ldr r0, [r13] @ restore r0
	470	add r13, r13, #4 @ pop stack entry
	471	.endm
	472
	473	.macro get_irq_stack @ setup IRQ stack
	474	ldr sp, IRQ_STACK_START
	475	.endm
	476
	477	.macro get_fiq_stack @ setup FIQ stack
	478	ldr sp, FIQ_STACK_START
	479	.endm
	480
	481	/*
	482	* exception handlers
	483	*/
	484	.align 5
	485	undefined_instruction:
	486	get_bad_stack
	487	bad_save_user_regs
	488	bl do_undefined_instruction
	489
	490	.align 5
	491	software_interrupt:
	492	get_bad_stack_swi
	493	bad_save_user_regs
	494	bl do_software_interrupt
	495
	496	.align 5
	497	prefetch_abort:
	498	get_bad_stack
	499	bad_save_user_regs
	500	bl do_prefetch_abort
	501
	502	.align 5
	503	data_abort:
	504	get_bad_stack
	505	bad_save_user_regs
	506	bl do_data_abort
	507
	508	.align 5
	509	not_used:
	510	get_bad_stack
	511	bad_save_user_regs
	512	bl do_not_used
	513
	514	#ifdef CONFIG_USE_IRQ
	515
	516	.align 5
	517	irq:
	518	get_irq_stack
	519	irq_save_user_regs
	520	bl do_irq
	521	irq_restore_user_regs
	522
	523	.align 5
	524	fiq:
	525	get_fiq_stack
	526	/* someone ought to write a more effective fiq_save_user_regs */
527	irq_save_user_regs
528	bl do_fiq
529	irq_restore_user_regs
530
531	#else
532
533	.align 5
534	irq:
535	get_bad_stack
536	bad_save_user_regs
537	bl do_irq
538
539	.align 5
540	fiq:
541	get_bad_stack
542	bad_save_user_regs
543	bl do_fiq
544
033ca724 A	545	#endif /* CONFIG_USE_IRQ */
033ca724 A	546	#endif /* CONFIG_SPL_BUILD */