[people/ms/u-boot.git] / arch / arm / cpu / armv7 / sunxi / board.c

/*
 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some init for sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <netdev.h>
#include <miiphy.h>
#include <serial.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>

#include <linux/compiler.h>

#ifdef CONFIG_SPL_BUILD
/* Pointer to the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;

/* The sunxi internal brom will try to loader external bootloader
 * from mmc0, nand flash, mmc2.
 * Unfortunately we can't check how SPL was loaded so assume
 * it's always the first SD/MMC controller
 */
u32 spl_boot_device(void)
{
	return BOOT_DEVICE_MMC1;
}

/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(void)
{
	return MMCSD_MODE_RAW;
}
#endif

int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif

	return 0;
}

void reset_cpu(ulong addr)
{
#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
	static const struct sunxi_wdog *wdog =
		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);

	while (1) {
		/* sun5i sometimes gets stuck without this */
		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	}
#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */
	static const struct sunxi_wdog *wdog =
		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_CFG_RESET, &wdog->cfg);
	writel(WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
#endif
}

/* do some early init */
void s_init(void)
{
#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \
		defined CONFIG_SUN6I || defined CONFIG_SUN8I)
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
		"mrc p15, 0, r0, c1, c0, 1\n"
		"orr r0, r0, #1 << 6\n"
		"mcr p15, 0, r0, c1, c0, 1\n");
#endif

	clock_init();
	timer_init();
	gpio_init();
	i2c_init_board();

#ifdef CONFIG_SPL_BUILD
	gd = &gdata;
	preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
	/* Needed early by sunxi_board_init if PMU is enabled */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
	sunxi_board_init();
#endif
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif

#ifdef CONFIG_CMD_NET
/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int cpu_eth_init(bd_t *bis)
{
	__maybe_unused int rc;

#ifdef CONFIG_MACPWR
	gpio_direction_output(CONFIG_MACPWR, 1);
	mdelay(200);
#endif

#ifdef CONFIG_SUNXI_EMAC
	rc = sunxi_emac_initialize(bis);
	if (rc < 0) {
		printf("sunxi: failed to initialize emac\n");
		return rc;
	}
#endif

#ifdef CONFIG_SUNXI_GMAC
	rc = sunxi_gmac_initialize(bis);
	if (rc < 0) {
		printf("sunxi: failed to initialize gmac\n");
		return rc;
	}
#endif

	return 0;
}
#endif
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* Some init for sunxi platform.
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
6620377e	14	#include <i2c.h>
5835823d IC	15	#include <netdev.h>
5835823d IC	16	#include <miiphy.h>
cba69eee IC	17	#include <serial.h>
	18	#ifdef CONFIG_SPL_BUILD
	19	#include <spl.h>
	20	#endif
	21	#include <asm/gpio.h>
	22	#include <asm/io.h>
	23	#include <asm/arch/clock.h>
	24	#include <asm/arch/gpio.h>
	25	#include <asm/arch/sys_proto.h>
	26	#include <asm/arch/timer.h>
	27
799aff38 IC	28	#include <linux/compiler.h>
799aff38 IC	29
cba69eee IC	30	#ifdef CONFIG_SPL_BUILD
	31	/* Pointer to the global data structure for SPL */
	32	DECLARE_GLOBAL_DATA_PTR;
	33
	34	/* The sunxi internal brom will try to loader external bootloader
	35	* from mmc0, nand flash, mmc2.
	36	* Unfortunately we can't check how SPL was loaded so assume
	37	* it's always the first SD/MMC controller
	38	*/
	39	u32 spl_boot_device(void)
	40	{
	41	return BOOT_DEVICE_MMC1;
	42	}
	43
	44	/* No confirmation data available in SPL yet. Hardcode bootmode */
	45	u32 spl_boot_mode(void)
	46	{
	47	return MMCSD_MODE_RAW;
	48	}
	49	#endif
	50
	51	int gpio_init(void)
	52	{
ff2b47f6 CYT	53	#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
	54	#if defined(CONFIG_SUN4I) \|\| defined(CONFIG_SUN7I)
	55	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	56	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	57	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
	58	#endif
	59	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
	60	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
	61	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
	62	#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) \|\| defined(CONFIG_SUN7I))
cba69eee IC	63	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
cba69eee IC	64	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
ea520947	65	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
f84269c5 HG	66	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
	67	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
	68	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
ea520947	69	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
77115397 MR	70	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
	71	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
	72	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
	73	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
f84269c5 HG	74	#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
	75	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
	76	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
ea520947	77	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
c757a50b CYT	78	#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
	79	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
	80	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
	81	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
f84269c5 HG	82	#else
	83	#error Unsupported console port number. Please fix pin mux settings in board.c
	84	#endif
cba69eee IC	85
	86	return 0;
	87	}
	88
	89	void reset_cpu(ulong addr)
	90	{
78c396a1	91	#if defined(CONFIG_SUN4I) \|\| defined(CONFIG_SUN5I) \|\| defined(CONFIG_SUN7I)
c7e79dec HG	92	static const struct sunxi_wdog *wdog =
	93	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	94
	95	/* Set the watchdog for its shortest interval (.5s) and wait */
	96	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	97	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
ae5de5a1 HG	98
	99	while (1) {
	100	/* sun5i sometimes gets stuck without this */
	101	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	102	}
78c396a1 CYT	103	#else /* CONFIG_SUN6I \|\| CONFIG_SUN8I \|\| .. */
	104	static const struct sunxi_wdog *wdog =
	105	((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	106
	107	/* Set the watchdog for its shortest interval (.5s) and wait */
	108	writel(WDT_CFG_RESET, &wdog->cfg);
	109	writel(WDT_MODE_EN, &wdog->mode);
	110	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
	111	#endif
cba69eee IC	112	}
	113
	114	/* do some early init */
	115	void s_init(void)
	116	{
8ebe4f42 CYT	117	#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I \|\| \
8ebe4f42 CYT	118	defined CONFIG_SUN6I \|\| defined CONFIG_SUN8I)
cba69eee IC	119	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	120	asm volatile(
	121	"mrc p15, 0, r0, c1, c0, 1\n"
	122	"orr r0, r0, #1 << 6\n"
	123	"mcr p15, 0, r0, c1, c0, 1\n");
	124	#endif
	125
	126	clock_init();
	127	timer_init();
	128	gpio_init();
6620377e	129	i2c_init_board();
cba69eee IC	130
	131	#ifdef CONFIG_SPL_BUILD
	132	gd = &gdata;
	133	preloader_console_init();
	134
6620377e HG	135	#ifdef CONFIG_SPL_I2C_SUPPORT
	136	/* Needed early by sunxi_board_init if PMU is enabled */
	137	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	138	#endif
cba69eee IC	139	sunxi_board_init();
	140	#endif
	141	}
	142
	143	#ifndef CONFIG_SYS_DCACHE_OFF
	144	void enable_caches(void)
	145	{
	146	/* Enable D-cache. I-cache is already enabled in start.S */
	147	dcache_enable();
	148	}
	149	#endif
5835823d IC	150
	151	#ifdef CONFIG_CMD_NET
	152	/*
	153	* Initializes on-chip ethernet controllers.
	154	* to override, implement board_eth_init()
	155	*/
	156	int cpu_eth_init(bd_t *bis)
	157	{
799aff38	158	__maybe_unused int rc;
5835823d	159
fc703001 HG	160	#ifdef CONFIG_MACPWR
	161	gpio_direction_output(CONFIG_MACPWR, 1);
	162	mdelay(200);
	163	#endif
	164
c26fb9db HG	165	#ifdef CONFIG_SUNXI_EMAC
	166	rc = sunxi_emac_initialize(bis);
	167	if (rc < 0) {
	168	printf("sunxi: failed to initialize emac\n");
	169	return rc;
	170	}
	171	#endif
	172
5835823d IC	173	#ifdef CONFIG_SUNXI_GMAC
	174	rc = sunxi_gmac_initialize(bis);
	175	if (rc < 0) {
	176	printf("sunxi: failed to initialize gmac\n");
	177	return rc;
	178	}
	179	#endif
	180
	181	return 0;
	182	}
	183	#endif