[people/ms/u-boot.git] / arch / arm / cpu / armv7 / sunxi / dram_sun8i_h3.c

/*
 * sun8i H3 platform dram controller init
 *
 * (C) Copyright 2007-2015 Allwinner Technology Co.
 *                         Jerry Wang <wangflord@allwinnertech.com>
 * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
 * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>
 * (C) Copyright 2015      Jens Kuske <jenskuske@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <linux/kconfig.h>

struct dram_para {
	u32 read_delays;
	u32 write_delays;
	u16 page_size;
	u8 bus_width;
	u8 dual_rank;
	u8 row_bits;
};

static inline int ns_to_t(int nanoseconds)
{
	const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;

	return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
}

static u32 bin_to_mgray(int val)
{
	static const u8 lookup_table[32] = {
		0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
		0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
		0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
		0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
	};

	return lookup_table[clamp(val, 0, 31)];
}

static int mgray_to_bin(u32 val)
{
	static const u8 lookup_table[32] = {
		0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
		0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
		0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
		0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
	};

	return lookup_table[val & 0x1f];
}

static void mctl_phy_init(u32 val)
{
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

	writel(val | PIR_INIT, &mctl_ctl->pir);
	mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
}

static void mctl_dq_delay(u32 read, u32 write)
{
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
	int i, j;
	u32 val;

	for (i = 0; i < 4; i++) {
		val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
		      DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);

		for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
			writel(val, &mctl_ctl->datx[i].iocr[j]);
	}

	clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);

	for (i = 0; i < 4; i++) {
		val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
		      DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);

		writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
		writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
	}

	setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);

	udelay(1);
}

static void mctl_set_master_priority(void)
{
	struct sunxi_mctl_com_reg * const mctl_com =
			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;

	/* enable bandwidth limit windows and set windows size 1us */
	writel(0x00010190, &mctl_com->bwcr);

	/* set cpu high priority */
	writel(0x00000001, &mctl_com->mapr);

	writel(0x0200000d, &mctl_com->mcr[0][0]);
	writel(0x00800100, &mctl_com->mcr[0][1]);
	writel(0x06000009, &mctl_com->mcr[1][0]);
	writel(0x01000400, &mctl_com->mcr[1][1]);
	writel(0x0200000d, &mctl_com->mcr[2][0]);
	writel(0x00600100, &mctl_com->mcr[2][1]);
	writel(0x0100000d, &mctl_com->mcr[3][0]);
	writel(0x00200080, &mctl_com->mcr[3][1]);
	writel(0x07000009, &mctl_com->mcr[4][0]);
	writel(0x01000640, &mctl_com->mcr[4][1]);
	writel(0x0100000d, &mctl_com->mcr[5][0]);
	writel(0x00200080, &mctl_com->mcr[5][1]);
	writel(0x01000009, &mctl_com->mcr[6][0]);
	writel(0x00400080, &mctl_com->mcr[6][1]);
	writel(0x0100000d, &mctl_com->mcr[7][0]);
	writel(0x00400080, &mctl_com->mcr[7][1]);
	writel(0x0100000d, &mctl_com->mcr[8][0]);
	writel(0x00400080, &mctl_com->mcr[8][1]);
	writel(0x04000009, &mctl_com->mcr[9][0]);
	writel(0x00400100, &mctl_com->mcr[9][1]);
	writel(0x2000030d, &mctl_com->mcr[10][0]);
	writel(0x04001800, &mctl_com->mcr[10][1]);
	writel(0x04000009, &mctl_com->mcr[11][0]);
	writel(0x00400120, &mctl_com->mcr[11][1]);
}

static void mctl_set_timing_params(struct dram_para *para)
{
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

	u8 tccd		= 2;
	u8 tfaw		= ns_to_t(50);
	u8 trrd		= max(ns_to_t(10), 4);
	u8 trcd		= ns_to_t(15);
	u8 trc		= ns_to_t(53);
	u8 txp		= max(ns_to_t(8), 3);
	u8 twtr		= max(ns_to_t(8), 4);
	u8 trtp		= max(ns_to_t(8), 4);
	u8 twr		= max(ns_to_t(15), 3);
	u8 trp		= ns_to_t(15);
	u8 tras		= ns_to_t(38);
	u16 trefi	= ns_to_t(7800) / 32;
	u16 trfc	= ns_to_t(350);

	u8 tmrw		= 0;
	u8 tmrd		= 4;
	u8 tmod		= 12;
	u8 tcke		= 3;
	u8 tcksrx	= 5;
	u8 tcksre	= 5;
	u8 tckesr	= 4;
	u8 trasmax	= 24;

	u8 tcl		= 6; /* CL 12 */
	u8 tcwl		= 4; /* CWL 8 */
	u8 t_rdata_en	= 4;
	u8 wr_latency	= 2;

	u32 tdinit0	= (500 * CONFIG_DRAM_CLK) + 1;		/* 500us */
	u32 tdinit1	= (360 * CONFIG_DRAM_CLK) / 1000 + 1;	/* 360ns */
	u32 tdinit2	= (200 * CONFIG_DRAM_CLK) + 1;		/* 200us */
	u32 tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;		/* 1us */

	u8 twtp		= tcwl + 2 + twr;	/* WL + BL / 2 + tWR */
	u8 twr2rd	= tcwl + 2 + twtr;	/* WL + BL / 2 + tWTR */
	u8 trd2wr	= tcl + 2 + 1 - tcwl;	/* RL + BL / 2 + 2 - WL */

	/* set mode register */
	writel(0x1c70, &mctl_ctl->mr[0]);	/* CL=11, WR=12 */
	writel(0x40, &mctl_ctl->mr[1]);
	writel(0x18, &mctl_ctl->mr[2]);		/* CWL=8 */
	writel(0x0, &mctl_ctl->mr[3]);

	/* set DRAM timing */
	writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
	       DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
	       &mctl_ctl->dramtmg[0]);
	writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
	       &mctl_ctl->dramtmg[1]);
	writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
	       DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
	       &mctl_ctl->dramtmg[2]);
	writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
	       &mctl_ctl->dramtmg[3]);
	writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
	       DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
	writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
	       DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
	       &mctl_ctl->dramtmg[5]);

	/* set two rank timing */
	clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
			(0x66 << 8) | (0x10 << 0));

	/* set PHY interface timing, write latency and read latency configure */
	writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
	       (wr_latency << 0), &mctl_ctl->pitmg[0]);

	/* set PHY timing, PTR0-2 use default */
	writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
	writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);

	/* set refresh timing */
	writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
}

static void mctl_zq_calibration(struct dram_para *para)
{
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

	int i;
	u16 zq_val[6];
	u8 val;

	writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);

	for (i = 0; i < 6; i++) {
		u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;

		writel((zq << 20) | (zq << 16) | (zq << 12) |
				(zq << 8) | (zq << 4) | (zq << 0),
				&mctl_ctl->zqcr);

		writel(PIR_CLRSR, &mctl_ctl->pir);
		mctl_phy_init(PIR_ZCAL);

		zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
		writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);

		writel(PIR_CLRSR, &mctl_ctl->pir);
		mctl_phy_init(PIR_ZCAL);

		val = readl(&mctl_ctl->zqdr[0]) >> 24;
		zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
	}

	writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
	writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
	writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
}

static void mctl_set_cr(struct dram_para *para)
{
	struct sunxi_mctl_com_reg * const mctl_com =
			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;

	writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
	       MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
	       (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
	       MCTL_CR_PAGE_SIZE(para->page_size) |
	       MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
}

static void mctl_sys_init(struct dram_para *para)
{
	struct sunxi_ccm_reg * const ccm =
			(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

	clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
	clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
	clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
	udelay(10);

	clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
	udelay(1000);

	clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
	clrsetbits_le32(&ccm->dram_clk_cfg,
			CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
			CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
			CCM_DRAMCLK_CFG_UPD);
	mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);

	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
	setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);

	setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
	udelay(10);

	writel(0xc00e, &mctl_ctl->clken);
	udelay(500);
}

static int mctl_channel_init(struct dram_para *para)
{
	struct sunxi_mctl_com_reg * const mctl_com =
			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

	unsigned int i;

	mctl_set_cr(para);
	mctl_set_timing_params(para);
	mctl_set_master_priority();

	/* setting VTC, default disable all VT */
	clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
	clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);

	/* increase DFI_PHY_UPD clock */
	writel(PROTECT_MAGIC, &mctl_com->protect);
	udelay(100);
	clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
	writel(0x0, &mctl_com->protect);
	udelay(100);

	/* set dramc odt */
	for (i = 0; i < 4; i++)
		clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
				(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
				(0x3 << 14),
				IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);

	/* AC PDR should always ON */
	setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);

	/* set DQS auto gating PD mode */
	setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);

	/* dx ddr_clk & hdr_clk dynamic mode */
	clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));

	/* dphy & aphy phase select 270 degree */
	clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
			(0x1 << 10) | (0x2 << 8));

	/* set half DQ */
	if (para->bus_width != 32) {
		writel(0x0, &mctl_ctl->datx[2].gcr);
		writel(0x0, &mctl_ctl->datx[3].gcr);
	}

	/* data training configuration */
	clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
			(para->dual_rank ? 0x3 : 0x1) << 24);


	if (para->read_delays || para->write_delays) {
		mctl_dq_delay(para->read_delays, para->write_delays);
		udelay(50);
	}

	mctl_zq_calibration(para);

	mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
		      PIR_DRAMINIT | PIR_QSGATE);

	/* detect ranks and bus width */
	if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
		/* only one rank */
		if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) ||
		    ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
			clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
			para->dual_rank = 0;
		}

		/* only half DQ width */
		if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) ||
		    ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
			writel(0x0, &mctl_ctl->datx[2].gcr);
			writel(0x0, &mctl_ctl->datx[3].gcr);
			para->bus_width = 16;
		}

		mctl_set_cr(para);
		udelay(20);

		/* re-train */
		mctl_phy_init(PIR_QSGATE);
		if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
			return 1;
	}

	/* check the dramc status */
	mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);

	/* liuke added for refresh debug */
	setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
	udelay(10);
	clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
	udelay(10);

	/* set PGCR3, CKE polarity */
	writel(0x00aa0060, &mctl_ctl->pgcr[3]);

	/* power down zq calibration module for power save */
	setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);

	/* enable master access */
	writel(0xffffffff, &mctl_com->maer);

	return 0;
}

static void mctl_auto_detect_dram_size(struct dram_para *para)
{
	/* detect row address bits */
	para->page_size = 512;
	para->row_bits = 16;
	mctl_set_cr(para);

	for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
		if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
			break;

	/* detect page size */
	para->page_size = 8192;
	mctl_set_cr(para);

	for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
		if (mctl_mem_matches(para->page_size))
			break;
}

unsigned long sunxi_dram_init(void)
{
	struct sunxi_mctl_com_reg * const mctl_com =
			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
	struct sunxi_mctl_ctl_reg * const mctl_ctl =
			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;

	struct dram_para para = {
		.read_delays = 0x00007979,	/* dram_tpr12 */
		.write_delays = 0x6aaa0000,	/* dram_tpr11 */
		.dual_rank = 0,
		.bus_width = 32,
		.row_bits = 15,
		.page_size = 4096,
	};

	mctl_sys_init(&para);
	if (mctl_channel_init(&para))
		return 0;

	if (para.dual_rank)
		writel(0x00000303, &mctl_ctl->odtmap);
	else
		writel(0x00000201, &mctl_ctl->odtmap);
	udelay(1);

	/* odt delay */
	writel(0x0c000400, &mctl_ctl->odtcfg);

	/* clear credit value */
	setbits_le32(&mctl_com->cccr, 1 << 31);
	udelay(10);

	mctl_auto_detect_dram_size(&para);
	mctl_set_cr(&para);

	return (1 << (para.row_bits + 3)) * para.page_size *
						(para.dual_rank ? 2 : 1);
}
Commit	Line	Data
0404d53f JK	1	/*
	2	* sun8i H3 platform dram controller init
	3	*
	4	* (C) Copyright 2007-2015 Allwinner Technology Co.
	5	* Jerry Wang <wangflord@allwinnertech.com>
	6	* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
	7	* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
	8	* (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12	#include <common.h>
	13	#include <asm/io.h>
	14	#include <asm/arch/clock.h>
	15	#include <asm/arch/dram.h>
	16	#include <linux/kconfig.h>
	17
	18	struct dram_para {
	19	u32 read_delays;
	20	u32 write_delays;
	21	u16 page_size;
	22	u8 bus_width;
	23	u8 dual_rank;
	24	u8 row_bits;
	25	};
	26
	27	static inline int ns_to_t(int nanoseconds)
	28	{
	29	const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
	30
	31	return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
	32	}
	33
	34	static u32 bin_to_mgray(int val)
	35	{
	36	static const u8 lookup_table[32] = {
	37	0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
	38	0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
	39	0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
	40	0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
	41	};
	42
	43	return lookup_table[clamp(val, 0, 31)];
	44	}
	45
	46	static int mgray_to_bin(u32 val)
	47	{
	48	static const u8 lookup_table[32] = {
	49	0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
	50	0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
	51	0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
	52	0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
	53	};
	54
	55	return lookup_table[val & 0x1f];
	56	}
	57
	58	static void mctl_phy_init(u32 val)
	59	{
	60	struct sunxi_mctl_ctl_reg * const mctl_ctl =
	61	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
	62
	63	writel(val \| PIR_INIT, &mctl_ctl->pir);
	64	mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
65	}
66
67	static void mctl_dq_delay(u32 read, u32 write)
68	{
69	struct sunxi_mctl_ctl_reg * const mctl_ctl =
70	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
71	int i, j;
72	u32 val;
73
74	for (i = 0; i < 4; i++) {
75	val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) \|
bb365462	76	DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
0404d53f JK	77
0404d53f JK	78	for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
bb365462	79	writel(val, &mctl_ctl->datx[i].iocr[j]);
0404d53f JK	80	}
	81
	82	clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
	83
	84	for (i = 0; i < 4; i++) {
	85	val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) \|
	86	DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
	87
bb365462 JK	88	writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
bb365462 JK	89	writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
0404d53f JK	90	}
	91
	92	setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
	93
	94	udelay(1);
	95	}
	96
	97	static void mctl_set_master_priority(void)
	98	{
	99	struct sunxi_mctl_com_reg * const mctl_com =
	100	(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
	101
	102	/* enable bandwidth limit windows and set windows size 1us */
	103	writel(0x00010190, &mctl_com->bwcr);
	104
	105	/* set cpu high priority */
	106	writel(0x00000001, &mctl_com->mapr);
	107
	108	writel(0x0200000d, &mctl_com->mcr[0][0]);
	109	writel(0x00800100, &mctl_com->mcr[0][1]);
	110	writel(0x06000009, &mctl_com->mcr[1][0]);
	111	writel(0x01000400, &mctl_com->mcr[1][1]);
	112	writel(0x0200000d, &mctl_com->mcr[2][0]);
	113	writel(0x00600100, &mctl_com->mcr[2][1]);
	114	writel(0x0100000d, &mctl_com->mcr[3][0]);
	115	writel(0x00200080, &mctl_com->mcr[3][1]);
	116	writel(0x07000009, &mctl_com->mcr[4][0]);
	117	writel(0x01000640, &mctl_com->mcr[4][1]);
	118	writel(0x0100000d, &mctl_com->mcr[5][0]);
	119	writel(0x00200080, &mctl_com->mcr[5][1]);
	120	writel(0x01000009, &mctl_com->mcr[6][0]);
	121	writel(0x00400080, &mctl_com->mcr[6][1]);
	122	writel(0x0100000d, &mctl_com->mcr[7][0]);
	123	writel(0x00400080, &mctl_com->mcr[7][1]);
	124	writel(0x0100000d, &mctl_com->mcr[8][0]);
	125	writel(0x00400080, &mctl_com->mcr[8][1]);
	126	writel(0x04000009, &mctl_com->mcr[9][0]);
	127	writel(0x00400100, &mctl_com->mcr[9][1]);
	128	writel(0x2000030d, &mctl_com->mcr[10][0]);
	129	writel(0x04001800, &mctl_com->mcr[10][1]);
	130	writel(0x04000009, &mctl_com->mcr[11][0]);
	131	writel(0x00400120, &mctl_com->mcr[11][1]);
	132	}
	133
	134	static void mctl_set_timing_params(struct dram_para *para)
	135	{
	136	struct sunxi_mctl_ctl_reg * const mctl_ctl =
	137	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
	138
	139	u8 tccd = 2;
	140	u8 tfaw = ns_to_t(50);
	141	u8 trrd = max(ns_to_t(10), 4);
	142	u8 trcd = ns_to_t(15);
	143	u8 trc = ns_to_t(53);
	144	u8 txp = max(ns_to_t(8), 3);
	145	u8 twtr = max(ns_to_t(8), 4);
	146	u8 trtp = max(ns_to_t(8), 4);
	147	u8 twr = max(ns_to_t(15), 3);
	148	u8 trp = ns_to_t(15);
	149	u8 tras = ns_to_t(38);
	150	u16 trefi = ns_to_t(7800) / 32;
	151	u16 trfc = ns_to_t(350);
	152
	153	u8 tmrw = 0;
154	u8 tmrd = 4;
155	u8 tmod = 12;
156	u8 tcke = 3;
157	u8 tcksrx = 5;
158	u8 tcksre = 5;
159	u8 tckesr = 4;
160	u8 trasmax = 24;
161
162	u8 tcl = 6; /* CL 12 */
163	u8 tcwl = 4; /* CWL 8 */
164	u8 t_rdata_en = 4;
165	u8 wr_latency = 2;
166
167	u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
168	u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
169	u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
170	u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
171
172	u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
173	u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
174	u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
175
176	/* set mode register */
177	writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
178	writel(0x40, &mctl_ctl->mr[1]);
179	writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
180	writel(0x0, &mctl_ctl->mr[3]);
181
182	/* set DRAM timing */
183	writel(DRAMTMG0_TWTP(twtp) \| DRAMTMG0_TFAW(tfaw) \|
184	DRAMTMG0_TRAS_MAX(trasmax) \| DRAMTMG0_TRAS(tras),
185	&mctl_ctl->dramtmg[0]);
186	writel(DRAMTMG1_TXP(txp) \| DRAMTMG1_TRTP(trtp) \| DRAMTMG1_TRC(trc),
187	&mctl_ctl->dramtmg[1]);
188	writel(DRAMTMG2_TCWL(tcwl) \| DRAMTMG2_TCL(tcl) \|
189	DRAMTMG2_TRD2WR(trd2wr) \| DRAMTMG2_TWR2RD(twr2rd),
190	&mctl_ctl->dramtmg[2]);
191	writel(DRAMTMG3_TMRW(tmrw) \| DRAMTMG3_TMRD(tmrd) \| DRAMTMG3_TMOD(tmod),
192	&mctl_ctl->dramtmg[3]);
193	writel(DRAMTMG4_TRCD(trcd) \| DRAMTMG4_TCCD(tccd) \| DRAMTMG4_TRRD(trrd) \|
194	DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
195	writel(DRAMTMG5_TCKSRX(tcksrx) \| DRAMTMG5_TCKSRE(tcksre) \|
196	DRAMTMG5_TCKESR(tckesr) \| DRAMTMG5_TCKE(tcke),
197	&mctl_ctl->dramtmg[5]);
198
199	/* set two rank timing */
200	clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) \| (0xff << 0),
201	(0x66 << 8) \| (0x10 << 0));
202
203	/* set PHY interface timing, write latency and read latency configure */
204	writel((0x2 << 24) \| (t_rdata_en << 16) \| (0x1 << 8) \|
205	(wr_latency << 0), &mctl_ctl->pitmg[0]);
206
207	/* set PHY timing, PTR0-2 use default */
208	writel(PTR3_TDINIT0(tdinit0) \| PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
209	writel(PTR4_TDINIT2(tdinit2) \| PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
210
211	/* set refresh timing */
212	writel(RFSHTMG_TREFI(trefi) \| RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
213	}
214
215	static void mctl_zq_calibration(struct dram_para *para)
216	{
217	struct sunxi_mctl_ctl_reg * const mctl_ctl =
218	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
219
220	int i;
221	u16 zq_val[6];
222	u8 val;
223
224	writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
225
226	for (i = 0; i < 6; i++) {
227	u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
228
229	writel((zq << 20) \| (zq << 16) \| (zq << 12) \|
230	(zq << 8) \| (zq << 4) \| (zq << 0),
231	&mctl_ctl->zqcr);
232
233	writel(PIR_CLRSR, &mctl_ctl->pir);
234	mctl_phy_init(PIR_ZCAL);
235
236	zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
237	writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
238
239	writel(PIR_CLRSR, &mctl_ctl->pir);
240	mctl_phy_init(PIR_ZCAL);
241
242	val = readl(&mctl_ctl->zqdr[0]) >> 24;
243	zq_val[i] \|= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
244	}
245
246	writel((zq_val[1] << 16) \| zq_val[0], &mctl_ctl->zqdr[0]);
247	writel((zq_val[3] << 16) \| zq_val[2], &mctl_ctl->zqdr[1]);
248	writel((zq_val[5] << 16) \| zq_val[4], &mctl_ctl->zqdr[2]);
249	}
250
251	static void mctl_set_cr(struct dram_para *para)
252	{
253	struct sunxi_mctl_com_reg * const mctl_com =
254	(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
255
256	writel(MCTL_CR_BL8 \| MCTL_CR_2T \| MCTL_CR_DDR3 \| MCTL_CR_INTERLEAVED \|
257	MCTL_CR_EIGHT_BANKS \| MCTL_CR_BUS_WIDTH(para->bus_width) \|
258	(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) \|
259	MCTL_CR_PAGE_SIZE(para->page_size) \|
260	MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
261	}
262
263	static void mctl_sys_init(struct dram_para *para)
264	{
265	struct sunxi_ccm_reg * const ccm =
266	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
267	struct sunxi_mctl_ctl_reg * const mctl_ctl =
268	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
269
270	clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
271	clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
272	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
273	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
274	clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
275	udelay(10);
276
277	clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
278	udelay(1000);
279
280	clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
281	clrsetbits_le32(&ccm->dram_clk_cfg,
282	CCM_DRAMCLK_CFG_DIV_MASK \| CCM_DRAMCLK_CFG_SRC_MASK,
283	CCM_DRAMCLK_CFG_DIV(1) \| CCM_DRAMCLK_CFG_SRC_PLL5 \|
284	CCM_DRAMCLK_CFG_UPD);
285	mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
286
287	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
288	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
289	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
290	setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
291
292	setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
293	udelay(10);
294
295	writel(0xc00e, &mctl_ctl->clken);
296	udelay(500);
297	}
298
299	static int mctl_channel_init(struct dram_para *para)
300	{
301	struct sunxi_mctl_com_reg * const mctl_com =
302	(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
303	struct sunxi_mctl_ctl_reg * const mctl_ctl =
304	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
305
306	unsigned int i;
307
308	mctl_set_cr(para);
309	mctl_set_timing_params(para);
310	mctl_set_master_priority();
311
312	/* setting VTC, default disable all VT */
313	clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) \| 0x3f);
314	clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
315
316	/* increase DFI_PHY_UPD clock */
317	writel(PROTECT_MAGIC, &mctl_com->protect);
318	udelay(100);
319	clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
320	writel(0x0, &mctl_com->protect);
321	udelay(100);
322
323	/* set dramc odt */
324	for (i = 0; i < 4; i++)
325	clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) \|
326	(0x1 << 1) \| (0x3 << 2) \| (0x3 << 12) \|
327	(0x3 << 14),
328	IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
329
330	/* AC PDR should always ON */
331	setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
332
333	/* set DQS auto gating PD mode */
334	setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
335
336	/* dx ddr_clk & hdr_clk dynamic mode */
337	clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) \| (0x3 << 12));
338
339	/* dphy & aphy phase select 270 degree */
340	clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) \| (0x3 << 8),
341	(0x1 << 10) \| (0x2 << 8));
342
343	/* set half DQ */
344	if (para->bus_width != 32) {
345	writel(0x0, &mctl_ctl->datx[2].gcr);
346	writel(0x0, &mctl_ctl->datx[3].gcr);
347	}
348
349	/* data training configuration */
350	clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
351	(para->dual_rank ? 0x3 : 0x1) << 24);
352
353
354	if (para->read_delays \|\| para->write_delays) {
355	mctl_dq_delay(para->read_delays, para->write_delays);
356	udelay(50);
357	}
358
359	mctl_zq_calibration(para);
360
361	mctl_phy_init(PIR_PLLINIT \| PIR_DCAL \| PIR_PHYRST \| PIR_DRAMRST \|
362	PIR_DRAMINIT \| PIR_QSGATE);
363
364	/* detect ranks and bus width */
365	if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
366	/* only one rank */
367	if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) \|\|
368	((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
369	clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
370	para->dual_rank = 0;
371	}
372
373	/* only half DQ width */
374	if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) \|\|
375	((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
376	writel(0x0, &mctl_ctl->datx[2].gcr);
377	writel(0x0, &mctl_ctl->datx[3].gcr);
378	para->bus_width = 16;
379	}
380
381	mctl_set_cr(para);
382	udelay(20);
383
384	/* re-train */
385	mctl_phy_init(PIR_QSGATE);
386	if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
387	return 1;
388	}
389
390	/* check the dramc status */
391	mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
392
393	/* liuke added for refresh debug */
394	setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
395	udelay(10);
396	clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
397	udelay(10);
398
399	/* set PGCR3, CKE polarity */
400	writel(0x00aa0060, &mctl_ctl->pgcr[3]);
401
402	/* power down zq calibration module for power save */
403	setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
404
405	/* enable master access */
406	writel(0xffffffff, &mctl_com->maer);
407
408	return 0;
409	}
410
411	static void mctl_auto_detect_dram_size(struct dram_para *para)
412	{
413	/* detect row address bits */
414	para->page_size = 512;
415	para->row_bits = 16;
416	mctl_set_cr(para);
417
418	for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
419	if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
420	break;
421
422	/* detect page size */
423	para->page_size = 8192;
424	mctl_set_cr(para);
425
426	for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
427	if (mctl_mem_matches(para->page_size))
428	break;
429	}
430
431	unsigned long sunxi_dram_init(void)
432	{
433	struct sunxi_mctl_com_reg * const mctl_com =
434	(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
435	struct sunxi_mctl_ctl_reg * const mctl_ctl =
436	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
437
438	struct dram_para para = {
bb365462 JK	439	.read_delays = 0x00007979, /* dram_tpr12 */
bb365462 JK	440	.write_delays = 0x6aaa0000, /* dram_tpr11 */
0404d53f JK	441	.dual_rank = 0,
	442	.bus_width = 32,
	443	.row_bits = 15,
	444	.page_size = 4096,
	445	};
	446
	447	mctl_sys_init(&para);
	448	if (mctl_channel_init(&para))
	449	return 0;
	450
	451	if (para.dual_rank)
	452	writel(0x00000303, &mctl_ctl->odtmap);
	453	else
	454	writel(0x00000201, &mctl_ctl->odtmap);
	455	udelay(1);
	456
	457	/* odt delay */
	458	writel(0x0c000400, &mctl_ctl->odtcfg);
	459
	460	/* clear credit value */
	461	setbits_le32(&mctl_com->cccr, 1 << 31);
	462	udelay(10);
	463
	464	mctl_auto_detect_dram_size(&para);
	465	mctl_set_cr(&para);
	466
	467	return (1 << (para.row_bits + 3)) * para.page_size *
	468	(para.dual_rank ? 2 : 1);
	469	}