[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

config ARCH_LS1012A
	bool
	select FSL_LSCH2
	select SYS_FSL_DDR_BE
	select SYS_FSL_MMDC
	select SYS_FSL_ERRATUM_A010315

config ARCH_LS1043A
	bool
	select FSL_LSCH2
	select SYS_FSL_DDR_BE
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_ERRATUM_A010315
	select SYS_FSL_ERRATUM_A010539

config ARCH_LS1046A
	bool
	select FSL_LSCH2
	select SYS_FSL_DDR_BE
	select SYS_FSL_DDR4
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_ERRATUM_A010539
	select SYS_FSL_SRDS_2

config ARCH_LS2080A
	bool
	select FSL_LSCH3
	select SYS_FSL_DDR4
	select SYS_FSL_DDR_LE
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_HAS_DP_DDR
	select SYS_FSL_SRDS_2

config FSL_LSCH2
	bool
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES

config FSL_LSCH3
	bool
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES

menu "Layerscape architecture"
	depends on FSL_LSCH2 || FSL_LSCH3

config SYS_FSL_MMDC
	bool

config SYS_FSL_ERRATUM_A010315
	bool "Workaround for PCIe erratum A010315"

config SYS_FSL_ERRATUM_A010539
	bool "Workaround for PIN MUX erratum A010539"

config MAX_CPUS
	int "Maximum number of CPUs permitted for Layerscape"
	default 4 if ARCH_LS1043A
	default 4 if ARCH_LS1046A
	default 16 if ARCH_LS2080A
	default 1
	help
	  Set this number to the maximum number of possible CPUs in the SoC.
	  SoCs may have multiple clusters with each cluster may have multiple
	  ports. If some ports are reserved but higher ports are used for
	  cores, count the reserved ports. This will allocate enough memory
	  in spin table to properly handle all cores.

config NUM_DDR_CONTROLLERS
	int "Maximum DDR controllers"
	default 3 if ARCH_LS2080A
	default 1

config SECURE_BOOT
	bool
	help
		Enable Freescale Secure Boot feature

config SYS_FSL_IFC_BANK_COUNT
	int "Maximum banks of Integrated flash controller"
	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
	default 4 if ARCH_LS1043A
	default 4 if ARCH_LS1046A
	default 8 if ARCH_LS2080A

config SYS_FSL_HAS_DP_DDR
	bool

config SYS_FSL_SRDS_1
	bool

config SYS_FSL_SRDS_2
	bool

config SYS_HAS_SERDES
	bool

config SYS_FSL_DDR
	bool "Freescale DDR driver"
	help
	  Select Freescale General DDR driver, shared between most Freescale
	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
	  based Layerscape SoCs (such as ls2080a).

config SYS_FSL_DDR_BE
	bool
	help
	  Access DDR registers in big-endian.

config SYS_FSL_DDR_LE
	bool
	help
	  Access DDR registers in little-endian.

config SYS_FSL_DDR_VER
	int
	default 50 if SYS_FSL_DDR_VER_50

config SYS_FSL_DDR_VER_50
	bool

config SYS_FSL_DDRC_ARM_GEN3
	bool

config SYS_FSL_DDRC_GEN4
	bool

config SYS_FSL_DDR3
	bool "Freescale DDR3 controller"
	depends on !SYS_FSL_DDR4
	select SYS_FSL_DDR
	select SYS_FSL_DDRC_ARM_GEN3
	help
	  Enable Freescale DDR3 controller on ARM-based SoCs.

config SYS_FSL_DDR4
	bool "Freescale DDR4 controller"
	select SYS_FSL_DDR
	select SYS_FSL_DDRC_GEN4
	help
	  Enable Freescale DDR4 controller.

endmenu
Commit	Line	Data
9533acf3	1	config ARCH_LS1012A
4a444176	2	bool
fb2bf8c2	3	select FSL_LSCH2
24aaa094	4	select SYS_FSL_DDR_BE
9533acf3	5	select SYS_FSL_MMDC
0a37cf8f YS	6	select SYS_FSL_ERRATUM_A010315
	7
	8	config ARCH_LS1043A
4a444176	9	bool
fb2bf8c2	10	select FSL_LSCH2
24aaa094 YS	11	select SYS_FSL_DDR_BE
24aaa094 YS	12	select SYS_FSL_DDR_VER_50
0a37cf8f	13	select SYS_FSL_ERRATUM_A010315
0ea3671d	14	select SYS_FSL_ERRATUM_A010539
9533acf3	15
da28e58a	16	config ARCH_LS1046A
4a444176	17	bool
fb2bf8c2	18	select FSL_LSCH2
24aaa094 YS	19	select SYS_FSL_DDR_BE
	20	select SYS_FSL_DDR4
	21	select SYS_FSL_DDR_VER_50
0ea3671d	22	select SYS_FSL_ERRATUM_A010539
f534b8f5	23	select SYS_FSL_SRDS_2
9533acf3	24
4a444176 YS	25	config ARCH_LS2080A
4a444176 YS	26	bool
fb2bf8c2	27	select FSL_LSCH3
24aaa094 YS	28	select SYS_FSL_DDR4
	29	select SYS_FSL_DDR_LE
	30	select SYS_FSL_DDR_VER_50
f534b8f5 YS	31	select SYS_FSL_HAS_DP_DDR
f534b8f5 YS	32	select SYS_FSL_SRDS_2
fb2bf8c2 YS	33
	34	config FSL_LSCH2
	35	bool
f534b8f5 YS	36	select SYS_FSL_SRDS_1
f534b8f5 YS	37	select SYS_HAS_SERDES
fb2bf8c2 YS	38
	39	config FSL_LSCH3
	40	bool
f534b8f5 YS	41	select SYS_FSL_SRDS_1
f534b8f5 YS	42	select SYS_HAS_SERDES
fb2bf8c2 YS	43
	44	menu "Layerscape architecture"
	45	depends on FSL_LSCH2 \|\| FSL_LSCH3
4a444176	46
9533acf3	47	config SYS_FSL_MMDC
4a444176	48	bool
0a37cf8f YS	49
	50	config SYS_FSL_ERRATUM_A010315
	51	bool "Workaround for PCIe erratum A010315"
0ea3671d HZ	52
	53	config SYS_FSL_ERRATUM_A010539
	54	bool "Workaround for PIN MUX erratum A010539"
fb2bf8c2	55
b4b60d06 YS	56	config MAX_CPUS
	57	int "Maximum number of CPUs permitted for Layerscape"
	58	default 4 if ARCH_LS1043A
	59	default 4 if ARCH_LS1046A
	60	default 16 if ARCH_LS2080A
	61	default 1
	62	help
	63	Set this number to the maximum number of possible CPUs in the SoC.
	64	SoCs may have multiple clusters with each cluster may have multiple
	65	ports. If some ports are reserved but higher ports are used for
	66	cores, count the reserved ports. This will allocate enough memory
	67	in spin table to properly handle all cores.
	68
fd638102 YS	69	config NUM_DDR_CONTROLLERS
	70	int "Maximum DDR controllers"
	71	default 3 if ARCH_LS2080A
	72	default 1
	73
01f65d97 YS	74	config SECURE_BOOT
	75	bool
	76	help
	77	Enable Freescale Secure Boot feature
	78
25af7dc1 YS	79	config SYS_FSL_IFC_BANK_COUNT
	80	int "Maximum banks of Integrated flash controller"
	81	depends on ARCH_LS1043A \|\| ARCH_LS1046A \|\| ARCH_LS2080A
	82	default 4 if ARCH_LS1043A
	83	default 4 if ARCH_LS1046A
	84	default 8 if ARCH_LS2080A
	85
fd638102 YS	86	config SYS_FSL_HAS_DP_DDR
	87	bool
	88
f534b8f5 YS	89	config SYS_FSL_SRDS_1
	90	bool
	91
	92	config SYS_FSL_SRDS_2
	93	bool
	94
	95	config SYS_HAS_SERDES
	96	bool
	97
24aaa094 YS	98	config SYS_FSL_DDR
	99	bool "Freescale DDR driver"
	100	help
	101	Select Freescale General DDR driver, shared between most Freescale
	102	PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
	103	based Layerscape SoCs (such as ls2080a).
	104
	105	config SYS_FSL_DDR_BE
	106	bool
	107	help
	108	Access DDR registers in big-endian.
	109
	110	config SYS_FSL_DDR_LE
	111	bool
	112	help
	113	Access DDR registers in little-endian.
	114
	115	config SYS_FSL_DDR_VER
	116	int
	117	default 50 if SYS_FSL_DDR_VER_50
	118
	119	config SYS_FSL_DDR_VER_50
	120	bool
	121
	122	config SYS_FSL_DDRC_ARM_GEN3
	123	bool
	124
	125	config SYS_FSL_DDRC_GEN4
	126	bool
	127
	128	config SYS_FSL_DDR3
	129	bool "Freescale DDR3 controller"
	130	depends on !SYS_FSL_DDR4
	131	select SYS_FSL_DDR
	132	select SYS_FSL_DDRC_ARM_GEN3
	133	help
	134	Enable Freescale DDR3 controller on ARM-based SoCs.
	135
	136	config SYS_FSL_DDR4
	137	bool "Freescale DDR4 controller"
	138	select SYS_FSL_DDR
	139	select SYS_FSL_DDRC_GEN4
	140	help
	141	Enable Freescale DDR4 controller.
	142
fb2bf8c2	143	endmenu