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Commit | Line | Data |
---|---|---|
9533acf3 | 1 | config ARCH_LS1012A |
4a444176 | 2 | bool |
ee2a5102 | 3 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 4 | select FSL_LSCH2 |
24aaa094 | 5 | select SYS_FSL_DDR_BE |
9533acf3 | 6 | select SYS_FSL_MMDC |
0a37cf8f | 7 | select SYS_FSL_ERRATUM_A010315 |
a421192f | 8 | select ARCH_EARLY_INIT_R |
a5d67547 | 9 | select BOARD_EARLY_INIT_F |
0a37cf8f YS |
10 | |
11 | config ARCH_LS1043A | |
4a444176 | 12 | bool |
ee2a5102 | 13 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 14 | select FSL_LSCH2 |
d26e34c4 | 15 | select SYS_FSL_DDR |
24aaa094 YS |
16 | select SYS_FSL_DDR_BE |
17 | select SYS_FSL_DDR_VER_50 | |
ba1b6fb5 YS |
18 | select SYS_FSL_ERRATUM_A008850 |
19 | select SYS_FSL_ERRATUM_A009660 | |
20 | select SYS_FSL_ERRATUM_A009663 | |
21 | select SYS_FSL_ERRATUM_A009929 | |
22 | select SYS_FSL_ERRATUM_A009942 | |
0a37cf8f | 23 | select SYS_FSL_ERRATUM_A010315 |
0ea3671d | 24 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 YS |
25 | select SYS_FSL_HAS_DDR3 |
26 | select SYS_FSL_HAS_DDR4 | |
a421192f | 27 | select ARCH_EARLY_INIT_R |
a5d67547 | 28 | select BOARD_EARLY_INIT_F |
9533acf3 | 29 | |
da28e58a | 30 | config ARCH_LS1046A |
4a444176 | 31 | bool |
ee2a5102 | 32 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 33 | select FSL_LSCH2 |
d26e34c4 | 34 | select SYS_FSL_DDR |
24aaa094 | 35 | select SYS_FSL_DDR_BE |
24aaa094 | 36 | select SYS_FSL_DDR_VER_50 |
ba1b6fb5 YS |
37 | select SYS_FSL_ERRATUM_A008511 |
38 | select SYS_FSL_ERRATUM_A009801 | |
39 | select SYS_FSL_ERRATUM_A009803 | |
40 | select SYS_FSL_ERRATUM_A009942 | |
41 | select SYS_FSL_ERRATUM_A010165 | |
0ea3671d | 42 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 | 43 | select SYS_FSL_HAS_DDR4 |
f534b8f5 | 44 | select SYS_FSL_SRDS_2 |
a421192f | 45 | select ARCH_EARLY_INIT_R |
a5d67547 | 46 | select BOARD_EARLY_INIT_F |
9533acf3 | 47 | |
4a444176 YS |
48 | config ARCH_LS2080A |
49 | bool | |
ee2a5102 | 50 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 51 | select FSL_LSCH3 |
d26e34c4 | 52 | select SYS_FSL_DDR |
24aaa094 YS |
53 | select SYS_FSL_DDR_LE |
54 | select SYS_FSL_DDR_VER_50 | |
f534b8f5 | 55 | select SYS_FSL_HAS_DP_DDR |
2c2e2c9e | 56 | select SYS_FSL_HAS_SEC |
d26e34c4 | 57 | select SYS_FSL_HAS_DDR4 |
2c2e2c9e | 58 | select SYS_FSL_SEC_COMPAT_5 |
90b80386 | 59 | select SYS_FSL_SEC_LE |
f534b8f5 | 60 | select SYS_FSL_SRDS_2 |
ba1b6fb5 YS |
61 | select SYS_FSL_ERRATUM_A008336 |
62 | select SYS_FSL_ERRATUM_A008511 | |
63 | select SYS_FSL_ERRATUM_A008514 | |
64 | select SYS_FSL_ERRATUM_A008585 | |
65 | select SYS_FSL_ERRATUM_A009635 | |
66 | select SYS_FSL_ERRATUM_A009663 | |
67 | select SYS_FSL_ERRATUM_A009801 | |
68 | select SYS_FSL_ERRATUM_A009803 | |
69 | select SYS_FSL_ERRATUM_A009942 | |
70 | select SYS_FSL_ERRATUM_A010165 | |
a421192f | 71 | select ARCH_EARLY_INIT_R |
a5d67547 | 72 | select BOARD_EARLY_INIT_F |
fb2bf8c2 YS |
73 | |
74 | config FSL_LSCH2 | |
75 | bool | |
2c2e2c9e YS |
76 | select SYS_FSL_HAS_SEC |
77 | select SYS_FSL_SEC_COMPAT_5 | |
90b80386 | 78 | select SYS_FSL_SEC_BE |
f534b8f5 YS |
79 | select SYS_FSL_SRDS_1 |
80 | select SYS_HAS_SERDES | |
fb2bf8c2 YS |
81 | |
82 | config FSL_LSCH3 | |
83 | bool | |
f534b8f5 YS |
84 | select SYS_FSL_SRDS_1 |
85 | select SYS_HAS_SERDES | |
fb2bf8c2 YS |
86 | |
87 | menu "Layerscape architecture" | |
88 | depends on FSL_LSCH2 || FSL_LSCH3 | |
4a444176 | 89 | |
19538f30 HZ |
90 | config FSL_PCIE_COMPAT |
91 | string "PCIe compatible of Kernel DT" | |
92 | depends on PCIE_LAYERSCAPE | |
93 | default "fsl,ls1012a-pcie" if ARCH_LS1012A | |
94 | default "fsl,ls1043a-pcie" if ARCH_LS1043A | |
95 | default "fsl,ls1046a-pcie" if ARCH_LS1046A | |
96 | default "fsl,ls2080a-pcie" if ARCH_LS2080A | |
97 | help | |
98 | This compatible is used to find pci controller node in Kernel DT | |
99 | to complete fixup. | |
100 | ||
fa18ed76 WS |
101 | config HAS_FEATURE_GIC64K_ALIGN |
102 | bool | |
103 | default y if ARCH_LS1043A | |
104 | ||
2ca84bf7 WS |
105 | config HAS_FEATURE_ENHANCED_MSI |
106 | bool | |
107 | default y if ARCH_LS1043A | |
fa18ed76 | 108 | |
2d16a1a6 | 109 | menu "Layerscape PPA" |
110 | config FSL_LS_PPA | |
111 | bool "FSL Layerscape PPA firmware support" | |
df88cb3b | 112 | depends on !ARMV8_PSCI |
0541527b | 113 | select ARMV8_SEC_FIRMWARE_SUPPORT |
daa92644 | 114 | select SEC_FIRMWARE_ARMV8_PSCI |
0541527b | 115 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
2d16a1a6 | 116 | help |
117 | The FSL Primary Protected Application (PPA) is a software component | |
118 | which is loaded during boot stage, and then remains resident in RAM | |
119 | and runs in the TrustZone after boot. | |
120 | Say y to enable it. | |
0541527b HZ |
121 | choice |
122 | prompt "FSL Layerscape PPA firmware loading-media select" | |
123 | depends on FSL_LS_PPA | |
124 | default SYS_LS_PPA_FW_IN_XIP | |
125 | ||
126 | config SYS_LS_PPA_FW_IN_XIP | |
127 | bool "XIP" | |
128 | help | |
129 | Say Y here if the PPA firmware locate at XIP flash, such | |
130 | as NOR or QSPI flash. | |
131 | ||
132 | endchoice | |
133 | ||
134 | config SYS_LS_PPA_FW_ADDR | |
135 | hex "Address of PPA firmware loading from" | |
136 | depends on FSL_LS_PPA | |
137 | default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT | |
138 | default 0x60500000 if SYS_LS_PPA_FW_IN_XIP | |
139 | help | |
140 | If the PPA firmware locate at XIP flash, such as NOR or | |
141 | QSPI flash, this address is a directly memory-mapped. | |
142 | If it is in a serial accessed flash, such as NAND and SD | |
143 | card, it is a byte offset. | |
2d16a1a6 | 144 | endmenu |
145 | ||
0a37cf8f YS |
146 | config SYS_FSL_ERRATUM_A010315 |
147 | bool "Workaround for PCIe erratum A010315" | |
0ea3671d HZ |
148 | |
149 | config SYS_FSL_ERRATUM_A010539 | |
150 | bool "Workaround for PIN MUX erratum A010539" | |
fb2bf8c2 | 151 | |
b4b60d06 YS |
152 | config MAX_CPUS |
153 | int "Maximum number of CPUs permitted for Layerscape" | |
154 | default 4 if ARCH_LS1043A | |
155 | default 4 if ARCH_LS1046A | |
156 | default 16 if ARCH_LS2080A | |
157 | default 1 | |
158 | help | |
159 | Set this number to the maximum number of possible CPUs in the SoC. | |
160 | SoCs may have multiple clusters with each cluster may have multiple | |
161 | ports. If some ports are reserved but higher ports are used for | |
162 | cores, count the reserved ports. This will allocate enough memory | |
163 | in spin table to properly handle all cores. | |
164 | ||
01f65d97 | 165 | config SECURE_BOOT |
9cfab06e | 166 | bool "Secure Boot" |
01f65d97 YS |
167 | help |
168 | Enable Freescale Secure Boot feature | |
169 | ||
dd2ad2f1 YY |
170 | config QSPI_AHB_INIT |
171 | bool "Init the QSPI AHB bus" | |
172 | help | |
173 | The default setting for QSPI AHB bus just support 3bytes addressing. | |
174 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB | |
175 | bus for those flashes to support the full QSPI flash size. | |
176 | ||
25af7dc1 YS |
177 | config SYS_FSL_IFC_BANK_COUNT |
178 | int "Maximum banks of Integrated flash controller" | |
179 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A | |
180 | default 4 if ARCH_LS1043A | |
181 | default 4 if ARCH_LS1046A | |
182 | default 8 if ARCH_LS2080A | |
183 | ||
fd638102 YS |
184 | config SYS_FSL_HAS_DP_DDR |
185 | bool | |
186 | ||
f534b8f5 YS |
187 | config SYS_FSL_SRDS_1 |
188 | bool | |
189 | ||
190 | config SYS_FSL_SRDS_2 | |
191 | bool | |
192 | ||
193 | config SYS_HAS_SERDES | |
194 | bool | |
195 | ||
fb2bf8c2 | 196 | endmenu |
ba1b6fb5 | 197 | |
904110c7 HZ |
198 | menu "Layerscape clock tree configuration" |
199 | depends on FSL_LSCH2 || FSL_LSCH3 | |
200 | ||
201 | config SYS_FSL_CLK | |
202 | bool "Enable clock tree initialization" | |
203 | default y | |
204 | ||
205 | config CLUSTER_CLK_FREQ | |
206 | int "Reference clock of core cluster" | |
207 | depends on ARCH_LS1012A | |
208 | default 100000000 | |
209 | help | |
210 | This number is the reference clock frequency of core PLL. | |
211 | For most platforms, the core PLL and Platform PLL have the same | |
212 | reference clock, but for some platforms, LS1012A for instance, | |
213 | they are provided sepatately. | |
214 | ||
215 | config SYS_FSL_PCLK_DIV | |
216 | int "Platform clock divider" | |
217 | default 1 if ARCH_LS1043A | |
218 | default 1 if ARCH_LS1046A | |
219 | default 2 | |
220 | help | |
221 | This is the divider that is used to derive Platform clock from | |
222 | Platform PLL, in another word: | |
223 | Platform_clk = Platform_PLL_freq / this_divider | |
224 | ||
225 | config SYS_FSL_DSPI_CLK_DIV | |
226 | int "DSPI clock divider" | |
227 | default 1 if ARCH_LS1043A | |
228 | default 2 | |
229 | help | |
230 | This is the divider that is used to derive DSPI clock from Platform | |
231 | PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. | |
232 | ||
233 | config SYS_FSL_DUART_CLK_DIV | |
234 | int "DUART clock divider" | |
235 | default 1 if ARCH_LS1043A | |
236 | default 2 | |
237 | help | |
238 | This is the divider that is used to derive DUART clock from Platform | |
239 | clock, in another word DUART_clk = Platform_clk / this_divider. | |
240 | ||
241 | config SYS_FSL_I2C_CLK_DIV | |
242 | int "I2C clock divider" | |
243 | default 1 if ARCH_LS1043A | |
244 | default 2 | |
245 | help | |
246 | This is the divider that is used to derive I2C clock from Platform | |
247 | clock, in another word I2C_clk = Platform_clk / this_divider. | |
248 | ||
249 | config SYS_FSL_IFC_CLK_DIV | |
250 | int "IFC clock divider" | |
251 | default 1 if ARCH_LS1043A | |
252 | default 2 | |
253 | help | |
254 | This is the divider that is used to derive IFC clock from Platform | |
255 | clock, in another word IFC_clk = Platform_clk / this_divider. | |
256 | ||
257 | config SYS_FSL_LPUART_CLK_DIV | |
258 | int "LPUART clock divider" | |
259 | default 1 if ARCH_LS1043A | |
260 | default 2 | |
261 | help | |
262 | This is the divider that is used to derive LPUART clock from Platform | |
263 | clock, in another word LPUART_clk = Platform_clk / this_divider. | |
264 | ||
265 | config SYS_FSL_SDHC_CLK_DIV | |
266 | int "SDHC clock divider" | |
267 | default 1 if ARCH_LS1043A | |
268 | default 1 if ARCH_LS1012A | |
269 | default 2 | |
270 | help | |
271 | This is the divider that is used to derive SDHC clock from Platform | |
272 | clock, in another word SDHC_clk = Platform_clk / this_divider. | |
273 | endmenu | |
274 | ||
ba1b6fb5 YS |
275 | config SYS_FSL_ERRATUM_A008336 |
276 | bool | |
277 | ||
278 | config SYS_FSL_ERRATUM_A008514 | |
279 | bool | |
280 | ||
281 | config SYS_FSL_ERRATUM_A008585 | |
282 | bool | |
283 | ||
284 | config SYS_FSL_ERRATUM_A008850 | |
285 | bool | |
286 | ||
287 | config SYS_FSL_ERRATUM_A009635 | |
288 | bool | |
289 | ||
290 | config SYS_FSL_ERRATUM_A009660 | |
291 | bool | |
292 | ||
293 | config SYS_FSL_ERRATUM_A009929 | |
294 | bool |