[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c

/*
 * Copyright 2014-2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fsl_ifc.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_LS2080A
static void erratum_a008751(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;

	writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
#endif
}

static void erratum_rcw_src(void)
{
#if defined(CONFIG_SPL)
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
	u32 val;

	val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
	val &= ~DCFG_PORSR1_RCW_SRC;
	val |= DCFG_PORSR1_RCW_SRC_NOR;
	out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
#endif
}

#define I2C_DEBUG_REG 0x6
#define I2C_GLITCH_EN 0x8
/*
 * This erratum requires setting glitch_en bit to enable
 * digital glitch filter to improve clock stability.
 */
static void erratum_a009203(void)
{
	u8 __iomem *ptr;
#ifdef CONFIG_SYS_I2C
#ifdef I2C1_BASE_ADDR
	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);

	writeb(I2C_GLITCH_EN, ptr);
#endif
#ifdef I2C2_BASE_ADDR
	ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);

	writeb(I2C_GLITCH_EN, ptr);
#endif
#ifdef I2C3_BASE_ADDR
	ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);

	writeb(I2C_GLITCH_EN, ptr);
#endif
#ifdef I2C4_BASE_ADDR
	ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);

	writeb(I2C_GLITCH_EN, ptr);
#endif
#endif
}

void fsl_lsch3_early_init_f(void)
{
	erratum_a008751();
	erratum_rcw_src();
	init_early_memctl_regs();	/* tighten IFC timing */
	erratum_a009203();
}

#elif defined(CONFIG_LS1043A)
void fsl_lsch2_early_init_f(void)
{
	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;

#ifdef CONFIG_FSL_IFC
	init_early_memctl_regs();	/* tighten IFC timing */
#endif

	/*
	 * Enable snoop requests and DVM message requests for
	 * Slave insterface S4 (A53 core cluster)
	 */
	out_le32(&cci->slave[4].snoop_ctrl,
		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
}
#endif

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
	return 0;
}
#endif
Commit	Line	Data
b991b981	1	/*
9f3183d2	2	* Copyright 2014-2015 Freescale Semiconductor
b991b981 SW	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <fsl_ifc.h>
9f3183d2	9	#include <asm/arch/soc.h>
d746fef4	10	#include <asm/io.h>
b2d5ac59 SW	11	#include <asm/global_data.h>
	12
	13	DECLARE_GLOBAL_DATA_PTR;
d746fef4	14
44937214	15	#ifdef CONFIG_LS2080A
d746fef4 SW	16	static void erratum_a008751(void)
	17	{
	18	#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
	19	u32 __iomem scfg = (u32 __iomem )SCFG_BASE;
	20
	21	writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
	22	#endif
	23	}
b991b981	24
b2d5ac59 SW	25	static void erratum_rcw_src(void)
	26	{
	27	#if defined(CONFIG_SPL)
	28	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	29	u32 __iomem dcfg_dcsr = (u32 __iomem )DCFG_DCSR_BASE;
	30	u32 val;
	31
	32	val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
	33	val &= ~DCFG_PORSR1_RCW_SRC;
	34	val \|= DCFG_PORSR1_RCW_SRC_NOR;
	35	out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
	36	#endif
	37	}
	38
ab10d73d YS	39	#define I2C_DEBUG_REG 0x6
	40	#define I2C_GLITCH_EN 0x8
	41	/*
	42	* This erratum requires setting glitch_en bit to enable
	43	* digital glitch filter to improve clock stability.
	44	*/
	45	static void erratum_a009203(void)
	46	{
	47	u8 __iomem *ptr;
	48	#ifdef CONFIG_SYS_I2C
	49	#ifdef I2C1_BASE_ADDR
	50	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
	51
	52	writeb(I2C_GLITCH_EN, ptr);
	53	#endif
	54	#ifdef I2C2_BASE_ADDR
	55	ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
	56
	57	writeb(I2C_GLITCH_EN, ptr);
	58	#endif
	59	#ifdef I2C3_BASE_ADDR
	60	ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
	61
	62	writeb(I2C_GLITCH_EN, ptr);
	63	#endif
	64	#ifdef I2C4_BASE_ADDR
	65	ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
	66
	67	writeb(I2C_GLITCH_EN, ptr);
	68	#endif
	69	#endif
	70	}
	71
b991b981 SW	72	void fsl_lsch3_early_init_f(void)
b991b981 SW	73	{
d746fef4	74	erratum_a008751();
b2d5ac59	75	erratum_rcw_src();
b991b981	76	init_early_memctl_regs(); /* tighten IFC timing */
ab10d73d	77	erratum_a009203();
b991b981	78	}
8281c58f MH	79
	80	#elif defined(CONFIG_LS1043A)
	81	void fsl_lsch2_early_init_f(void)
	82	{
	83	struct ccsr_cci400 cci = (struct ccsr_cci400 )CONFIG_SYS_CCI400_ADDR;
	84
	85	#ifdef CONFIG_FSL_IFC
	86	init_early_memctl_regs(); /* tighten IFC timing */
	87	#endif
	88
	89	/*
	90	* Enable snoop requests and DVM message requests for
	91	* Slave insterface S4 (A53 core cluster)
	92	*/
	93	out_le32(&cci->slave[4].snoop_ctrl,
	94	CCI400_DVM_MESSAGE_REQ_EN \| CCI400_SNOOP_REQ_EN);
	95	}
9f3183d2	96	#endif
b2d5ac59	97
9f3183d2 MH	98	#ifdef CONFIG_BOARD_LATE_INIT
9f3183d2 MH	99	int board_late_init(void)
b2d5ac59	100	{
9f3183d2	101	return 0;
b2d5ac59 SW	102	}
b2d5ac59 SW	103	#endif