[people/ms/u-boot.git] / arch / arm / cpu / ixp / start.S

/* vi: set ts=8 sw=8 noet: */
/*
 *  u-boot - Startup Code for XScale IXP
 *
 * Copyright (C) 2003	Kyle Harris <kharris@nexus-tech.net>
 *
 * Based on startup code example contained in the
 * Intel IXP4xx Programmer's Guide and past u-boot Start.S
 * samples.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/arch/ixp425.h>

#define MMU_Control_M  0x001    /* Enable MMU */
#define MMU_Control_A  0x002    /* Enable address alignment faults */
#define MMU_Control_C  0x004    /* Enable cache */
#define MMU_Control_W  0x008    /* Enable write-buffer */
#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
#define MMU_Control_L  0x040    /* Compatability: */
#define MMU_Control_B  0x080    /* Enable Big-Endian */
#define MMU_Control_S  0x100    /* Enable system protection */
#define MMU_Control_R  0x200    /* Enable ROM protection */
#define MMU_Control_I  0x1000   /* Enable Instruction cache */
#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)


/*
 * Macro definitions
 */
	/* Delay a bit */
	.macro DELAY_FOR cycles, reg0
	ldr     \reg0, =\cycles
	subs    \reg0, \reg0, #1
	subne   pc,  pc, #0xc
	.endm

	/* wait for coprocessor write complete */
	.macro CPWAIT reg
	mrc  p15,0,\reg,c2,c0,0
	mov  \reg,\reg
	sub  pc,pc,#4
	.endm

.globl _start
_start:
	ldr	pc, _reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_reset:                 .word reset
_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * - relocate armboot to ram
 * - setup stack
 * - jump to second stage
 */

.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _image_copy_end_ofs
_image_copy_end_ofs:
	.word __image_copy_end - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/* disable mmu, set big-endian */
	mov	r0, #0xf8
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	/* invalidate I & D caches & BTB */
	mcr	p15, 0, r0, c7, c7, 0
	CPWAIT	r0

	/* invalidate I & Data TLB */
	mcr	p15, 0, r0, c8, c7, 0
	CPWAIT r0

	/* drain write and fill buffers */
	mcr	p15, 0, r0, c7, c10, 4
	CPWAIT	r0

	/* disable write buffer coalescing */
	mrc	p15, 0, r0, c1, c0, 1
	orr	r0, r0, #1
	mcr	p15, 0, r0, c1, c0, 1
	CPWAIT	r0

	/* set EXP CS0 to the optimum timing */
	ldr	r1, =CONFIG_SYS_EXP_CS0
	ldr     r2, =IXP425_EXP_CS0
	str     r1, [r2]

	/* make sure flash is visible at 0 */
	mov	r1, #CONFIG_SYS_SDR_CONFIG
	ldr     r2, =IXP425_SDR_CONFIG
	str     r1, [r2]

	/* disable refresh cycles */
	mov	r1, #0
	ldr     r3, =IXP425_SDR_REFRESH
	str	r1, [r3]

	/* send nop command */
	mov	r1, #3
	ldr	r4, =IXP425_SDR_IR
	str	r1, [r4]
	DELAY_FOR 0x4000, r0

	/* set SDRAM internal refresh val */
	ldr	r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
	str     r1, [r3]
	DELAY_FOR 0x4000, r0

	/* send precharge-all command to close all open banks */
	mov     r1, #2
	str     r1, [r4]
	DELAY_FOR 0x4000, r0

	/* provide 8 auto-refresh cycles */
	mov     r1, #4
	mov     r5, #8
111:    str	r1, [r4]
	DELAY_FOR 0x100, r0
	subs	r5, r5, #1
	bne	111b

	/* set mode register in sdram */
	mov	r1, #CONFIG_SYS_SDR_MODE_CONFIG
	str	r1, [r4]
	DELAY_FOR 0x4000, r0

	/* send normal operation command */
	mov	r1, #6
	str	r1, [r4]
	DELAY_FOR 0x4000, r0

	/* invalidate I & D caches & BTB */
	mcr	p15, 0, r0, c7, c7, 0
	CPWAIT	r0

	/* invalidate I & Data TLB */
	mcr	p15, 0, r0, c8, c7, 0
	CPWAIT r0

	/* drain write and fill buffers */
	mcr	p15, 0, r0, c7, c10, 4
	CPWAIT	r0

	/* remove flash mirror at 0x00000000 */
	ldr	r2, =IXP425_EXP_CFG0
	ldr     r1, [r2]
	bic     r1, r1, #0x80000000
	str     r1, [r2]

	/* invalidate I & Data TLB */
	mcr	p15, 0, r0, c8, c7, 0
	CPWAIT r0

	/* enable I cache */
	mrc     p15, 0, r0, c1, c0, 0
	orr     r0, r0, #MMU_Control_I
	mcr     p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	mrs	r0,cpsr			/* set the cpu to SVC32 mode	    */
	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
	orr	r0,r0,#0x13
	msr	cpsr,r0

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code(addr_moni)
 *
 * This function relocates the monitor code.
 */
	.globl	relocate_code
relocate_code:
	mov	r6, r0	/* save addr of destination */

	adr	r0, _start
	subs	r9, r6, r0		/* r9 <- relocation offset */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _image_copy_end_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	bx	lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	bx	lr

/****************************************************************************/
/*									    */
/* Interrupt handling							    */
/*									    */
/****************************************************************************/

/* IRQ stack frame							    */

#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13

	/* use bad_save_user_regs for abort/prefetch/undef/swi ...	    */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
	add	r8, sp, #S_PC

	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}			/* save sp_SVC, lr_SVC, pc, cpsr, old_r */
	mov	r0, sp
	.endm


	/* use irq_save_user_regs / irq_restore_user_regs for		     */
	/* IRQ/FIQ handling						     */

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			/* Calling r0-r12	     */
	add	r8, sp, #S_PC
	stmdb	r8, {sp, lr}^			/* Calling SP, LR	     */
	str	lr, [r8, #0]			/* Save calling PC	     */
	mrs	r6, spsr
	str	r6, [r8, #4]			/* Save CPSR		     */
	str	r0, [r8, #8]			/* Save OLD_R0		     */
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str	lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm


/****************************************************************************/
/*									    */
/* exception handlers							    */
/*									    */
/****************************************************************************/

	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	irq_save_user_regs		/* someone ought to write a more    */
	bl	do_fiq			/* effiction fiq_save_user_regs	    */
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif

/****************************************************************************/
/*                                                                          */
/* Reset function: Use Watchdog to reset                                    */
/*                                                                          */
/****************************************************************************/

	.align	5
.globl reset_cpu

reset_cpu:
	ldr	r1, =0x482e
	ldr     r2, =IXP425_OSWK
	str     r1, [r2]
	ldr	r1, =0x0fff
	ldr     r2, =IXP425_OSWT
	str     r1, [r2]
	ldr	r1, =0x5
	ldr     r2, =IXP425_OSWE
	str     r1, [r2]
	b	reset_endless

reset_endless:
	b	reset_endless
Commit	Line	Data
2d5b561e WD	1	/* vi: set ts=8 sw=8 noet: */
	2	/*
	3	* u-boot - Startup Code for XScale IXP
	4	*
	5	* Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
	6	*
	7	* Based on startup code example contained in the
	8	* Intel IXP4xx Programmer's Guide and past u-boot Start.S
	9	* samples.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
25ddd1fb	30	#include <asm-offsets.h>
2d5b561e WD	31	#include <config.h>
	32	#include <version.h>
	33	#include <asm/arch/ixp425.h>
	34
42d1f039 WD	35	#define MMU_Control_M 0x001 /* Enable MMU */
	36	#define MMU_Control_A 0x002 /* Enable address alignment faults */
	37	#define MMU_Control_C 0x004 /* Enable cache */
	38	#define MMU_Control_W 0x008 /* Enable write-buffer */
	39	#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
	40	#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
	41	#define MMU_Control_L 0x040 /* Compatability: */
	42	#define MMU_Control_B 0x080 /* Enable Big-Endian */
	43	#define MMU_Control_S 0x100 /* Enable system protection */
	44	#define MMU_Control_R 0x200 /* Enable ROM protection */
	45	#define MMU_Control_I 0x1000 /* Enable Instruction cache */
	46	#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
2d5b561e WD	47	#define MMU_Control_Init (MMU_Control_P\|MMU_Control_D\|MMU_Control_L)
	48
	49
	50	/*
	51	* Macro definitions
	52	*/
42d1f039 WD	53	/* Delay a bit */
	54	.macro DELAY_FOR cycles, reg0
	55	ldr \reg0, =\cycles
	56	subs \reg0, \reg0, #1
	57	subne pc, pc, #0xc
	58	.endm
	59
	60	/* wait for coprocessor write complete */
	61	.macro CPWAIT reg
	62	mrc p15,0,\reg,c2,c0,0
	63	mov \reg,\reg
	64	sub pc,pc,#4
	65	.endm
2d5b561e WD	66
2d5b561e WD	67	.globl _start
ce04bb41 MS	68	_start:
ce04bb41 MS	69	ldr pc, _reset
2d5b561e WD	70	ldr pc, _undefined_instruction
	71	ldr pc, _software_interrupt
	72	ldr pc, _prefetch_abort
	73	ldr pc, _data_abort
	74	ldr pc, _not_used
	75	ldr pc, _irq
	76	ldr pc, _fiq
	77
ce04bb41	78	_reset: .word reset
2d5b561e WD	79	_undefined_instruction: .word undefined_instruction
	80	_software_interrupt: .word software_interrupt
	81	_prefetch_abort: .word prefetch_abort
	82	_data_abort: .word data_abort
	83	_not_used: .word not_used
	84	_irq: .word irq
	85	_fiq: .word fiq
	86
	87	.balignl 16,0xdeadbeef
	88
	89
	90	/*
	91	* Startup Code (reset vector)
	92	*
	93	* do important init only if we don't start from memory!
	94	* - relocate armboot to ram
	95	* - setup stack
	96	* - jump to second stage
	97	*/
	98
2af0a099	99	.globl _TEXT_BASE
2d5b561e	100	_TEXT_BASE:
508611bc BT	101	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	102	.word CONFIG_SPL_TEXT_BASE
	103	#else
14d0a02a	104	.word CONFIG_SYS_TEXT_BASE
508611bc	105	#endif
2d5b561e	106
2d5b561e	107	/*
f6e20fc6	108	* These are defined in the board-specific linker script.
3336ca60 AA	109	* Subtracting _start from them lets the linker put their
	110	* relative position in the executable instead of leaving
	111	* them null.
2d5b561e	112	*/
3336ca60 AA	113	.globl _bss_start_ofs
	114	_bss_start_ofs:
	115	.word __bss_start - _start
2d5b561e	116
7086e91b BT	117	.globl _image_copy_end_ofs
	118	_image_copy_end_ofs:
	119	.word __image_copy_end - _start
	120
3336ca60 AA	121	.globl _bss_end_ofs
3336ca60 AA	122	_bss_end_ofs:
3929fb0a	123	.word __bss_end - _start
2d5b561e	124
f326cbba PYC	125	.globl _end_ofs
	126	_end_ofs:
	127	.word _end - _start
	128
2d5b561e WD	129	#ifdef CONFIG_USE_IRQ
	130	/* IRQ stack memory (calculated at run-time) */
	131	.globl IRQ_STACK_START
	132	IRQ_STACK_START:
	133	.word 0x0badc0de
	134
	135	/* IRQ stack memory (calculated at run-time) */
	136	.globl FIQ_STACK_START
	137	FIQ_STACK_START:
	138	.word 0x0badc0de
	139	#endif
	140
2af0a099 HS	141	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	142	.globl IRQ_STACK_START_IN
	143	IRQ_STACK_START_IN:
	144	.word 0x0badc0de
	145
2af0a099 HS	146	/*
	147	* the actual reset code
	148	*/
	149
	150	reset:
	151	/* disable mmu, set big-endian */
	152	mov r0, #0xf8
	153	mcr p15, 0, r0, c1, c0, 0
	154	CPWAIT r0
	155
	156	/* invalidate I & D caches & BTB */
	157	mcr p15, 0, r0, c7, c7, 0
	158	CPWAIT r0
	159
	160	/* invalidate I & Data TLB */
	161	mcr p15, 0, r0, c8, c7, 0
	162	CPWAIT r0
	163
	164	/* drain write and fill buffers */
	165	mcr p15, 0, r0, c7, c10, 4
	166	CPWAIT r0
	167
	168	/* disable write buffer coalescing */
	169	mrc p15, 0, r0, c1, c0, 1
	170	orr r0, r0, #1
	171	mcr p15, 0, r0, c1, c0, 1
	172	CPWAIT r0
	173
	174	/* set EXP CS0 to the optimum timing */
	175	ldr r1, =CONFIG_SYS_EXP_CS0
	176	ldr r2, =IXP425_EXP_CS0
	177	str r1, [r2]
	178
	179	/* make sure flash is visible at 0 */
2af0a099 HS	180	mov r1, #CONFIG_SYS_SDR_CONFIG
	181	ldr r2, =IXP425_SDR_CONFIG
	182	str r1, [r2]
	183
	184	/* disable refresh cycles */
	185	mov r1, #0
	186	ldr r3, =IXP425_SDR_REFRESH
	187	str r1, [r3]
	188
	189	/* send nop command */
	190	mov r1, #3
	191	ldr r4, =IXP425_SDR_IR
	192	str r1, [r4]
	193	DELAY_FOR 0x4000, r0
	194
	195	/* set SDRAM internal refresh val */
	196	ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
	197	str r1, [r3]
	198	DELAY_FOR 0x4000, r0
	199
	200	/* send precharge-all command to close all open banks */
	201	mov r1, #2
	202	str r1, [r4]
	203	DELAY_FOR 0x4000, r0
	204
	205	/* provide 8 auto-refresh cycles */
	206	mov r1, #4
	207	mov r5, #8
	208	111: str r1, [r4]
	209	DELAY_FOR 0x100, r0
	210	subs r5, r5, #1
	211	bne 111b
	212
	213	/* set mode register in sdram */
	214	mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
	215	str r1, [r4]
	216	DELAY_FOR 0x4000, r0
	217
	218	/* send normal operation command */
	219	mov r1, #6
	220	str r1, [r4]
	221	DELAY_FOR 0x4000, r0
	222
2af0a099 HS	223	/* invalidate I & D caches & BTB */
	224	mcr p15, 0, r0, c7, c7, 0
	225	CPWAIT r0
	226
	227	/* invalidate I & Data TLB */
	228	mcr p15, 0, r0, c8, c7, 0
	229	CPWAIT r0
	230
	231	/* drain write and fill buffers */
	232	mcr p15, 0, r0, c7, c10, 4
	233	CPWAIT r0
	234
ce04bb41	235	/* remove flash mirror at 0x00000000 */
2af0a099 HS	236	ldr r2, =IXP425_EXP_CFG0
	237	ldr r1, [r2]
	238	bic r1, r1, #0x80000000
	239	str r1, [r2]
	240
2af0a099 HS	241	/* invalidate I & Data TLB */
	242	mcr p15, 0, r0, c8, c7, 0
	243	CPWAIT r0
	244
	245	/* enable I cache */
	246	mrc p15, 0, r0, c1, c0, 0
	247	orr r0, r0, #MMU_Control_I
	248	mcr p15, 0, r0, c1, c0, 0
	249	CPWAIT r0
	250
	251	mrs r0,cpsr /* set the cpu to SVC32 mode */
	252	bic r0,r0,#0x1f /* (superviser mode, M=10011) */
	253	orr r0,r0,#0x13
	254	msr cpsr,r0
	255
e05e5de7	256	bl _main
2af0a099 HS	257
	258	/------------------------------------------------------------------------------/
	259
	260	/*
5c6db120	261	* void relocate_code(addr_moni)
2af0a099	262	*
959eaa74	263	* This function relocates the monitor code.
2af0a099 HS	264	*/
	265	.globl relocate_code
	266	relocate_code:
5c6db120	267	mov r6, r0 /* save addr of destination */
2af0a099	268
2af0a099	269	adr r0, _start
4b3db1cd	270	subs r9, r6, r0 /* r9 <- relocation offset */
e05e5de7	271	beq relocate_done /* skip relocation */
a78fb68f	272	mov r1, r6 /* r1 <- scratch for copy_loop */
7086e91b	273	ldr r3, _image_copy_end_ofs
3336ca60	274	add r2, r0, r3 /* r2 <- source end address */
2af0a099	275
2af0a099	276	copy_loop:
4b3db1cd BT	277	ldmia r0!, {r10-r11} /* copy from source address [r0] */
4b3db1cd BT	278	stmia r1!, {r10-r11} /* copy to target address [r1] */
da90d4ce AA	279	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	280	blo copy_loop
2af0a099	281
401bb30b	282	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	283	/*
	284	* fix .rel.dyn relocations
	285	*/
	286	ldr r0, _TEXT_BASE /* r0 <- Text base */
3336ca60 AA	287	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	288	add r10, r10, r0 /* r10 <- sym table in FLASH */
	289	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	290	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	291	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	292	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
2af0a099	293	fixloop:
3336ca60 AA	294	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	295	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	296	ldr r1, [r2, #4]
1f52d89f AB	297	and r7, r1, #0xff
1f52d89f AB	298	cmp r7, #23 /* relative fixup? */
3336ca60	299	beq fixrel
1f52d89f	300	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	301	beq fixabs
	302	/* ignore unknown type of fixup */
	303	b fixnext
	304	fixabs:
	305	/* absolute fix: set location to (offset) symbol value */
	306	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	307	add r1, r10, r1 /* r1 <- address of symbol in table */
	308	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	309	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	310	b fixnext
	311	fixrel:
	312	/* relative fix: increase location by offset */
	313	ldr r1, [r0]
	314	add r1, r1, r9
	315	fixnext:
	316	str r1, [r0]
	317	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
2af0a099	318	cmp r2, r3
79e63139	319	blo fixloop
2af0a099	320	#endif
2af0a099	321
e05e5de7	322	relocate_done:
2af0a099	323
e05e5de7	324	bx lr
2af0a099	325
3336ca60 AA	326	_rel_dyn_start_ofs:
	327	.word __rel_dyn_start - _start
	328	_rel_dyn_end_ofs:
	329	.word __rel_dyn_end - _start
	330	_dynsym_start_ofs:
	331	.word __dynsym_start - _start
2d5b561e	332
e05e5de7 AA	333	.globl c_runtime_cpu_setup
	334	c_runtime_cpu_setup:
	335
	336	bx lr
	337
2d5b561e WD	338	/****************************************************************************/
	339	/* */
	340	/* Interrupt handling */
	341	/* */
	342	/****************************************************************************/
	343
	344	/* IRQ stack frame */
	345
	346	#define S_FRAME_SIZE 72
	347
	348	#define S_OLD_R0 68
	349	#define S_PSR 64
	350	#define S_PC 60
	351	#define S_LR 56
	352	#define S_SP 52
	353
	354	#define S_IP 48
	355	#define S_FP 44
	356	#define S_R10 40
	357	#define S_R9 36
	358	#define S_R8 32
	359	#define S_R7 28
	360	#define S_R6 24
	361	#define S_R5 20
	362	#define S_R4 16
	363	#define S_R3 12
	364	#define S_R2 8
	365	#define S_R1 4
	366	#define S_R0 0
	367
	368	#define MODE_SVC 0x13
	369
	370	/* use bad_save_user_regs for abort/prefetch/undef/swi ... */
	371
	372	.macro bad_save_user_regs
	373	sub sp, sp, #S_FRAME_SIZE
	374	stmia sp, {r0 - r12} /* Calling r0-r12 */
	375	add r8, sp, #S_PC
	376
2af0a099	377	ldr r2, IRQ_STACK_START_IN
2d5b561e WD	378	ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
	379	add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
	380
	381	add r5, sp, #S_SP
	382	mov r1, lr
	383	stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
	384	mov r0, sp
	385	.endm
	386
	387
	388	/* use irq_save_user_regs / irq_restore_user_regs for */
	389	/* IRQ/FIQ handling */
	390
	391	.macro irq_save_user_regs
	392	sub sp, sp, #S_FRAME_SIZE
	393	stmia sp, {r0 - r12} /* Calling r0-r12 */
	394	add r8, sp, #S_PC
	395	stmdb r8, {sp, lr}^ /* Calling SP, LR */
	396	str lr, [r8, #0] /* Save calling PC */
	397	mrs r6, spsr
	398	str r6, [r8, #4] /* Save CPSR */
	399	str r0, [r8, #8] /* Save OLD_R0 */
	400	mov r0, sp
	401	.endm
	402
	403	.macro irq_restore_user_regs
	404	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	405	mov r0, r0
	406	ldr lr, [sp, #S_PC] @ Get PC
	407	add sp, sp, #S_FRAME_SIZE
	408	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	409	.endm
	410
	411	.macro get_bad_stack
2af0a099	412	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
2d5b561e WD	413
	414	str lr, [r13] @ save caller lr / spsr
	415	mrs lr, spsr
	416	str lr, [r13, #4]
	417
	418	mov r13, #MODE_SVC @ prepare SVC-Mode
	419	msr spsr_c, r13
	420	mov lr, pc
	421	movs pc, lr
	422	.endm
	423
	424	.macro get_irq_stack @ setup IRQ stack
	425	ldr sp, IRQ_STACK_START
	426	.endm
	427
	428	.macro get_fiq_stack @ setup FIQ stack
	429	ldr sp, FIQ_STACK_START
	430	.endm
	431
	432
	433	/****************************************************************************/
	434	/* */
	435	/* exception handlers */
	436	/* */
	437	/****************************************************************************/
	438
	439	.align 5
	440	undefined_instruction:
	441	get_bad_stack
	442	bad_save_user_regs
	443	bl do_undefined_instruction
	444
	445	.align 5
	446	software_interrupt:
	447	get_bad_stack
	448	bad_save_user_regs
	449	bl do_software_interrupt
	450
	451	.align 5
	452	prefetch_abort:
	453	get_bad_stack
	454	bad_save_user_regs
	455	bl do_prefetch_abort
	456
	457	.align 5
	458	data_abort:
	459	get_bad_stack
	460	bad_save_user_regs
	461	bl do_data_abort
	462
	463	.align 5
	464	not_used:
	465	get_bad_stack
	466	bad_save_user_regs
	467	bl do_not_used
	468
	469	#ifdef CONFIG_USE_IRQ
	470
	471	.align 5
	472	irq:
	473	get_irq_stack
	474	irq_save_user_regs
	475	bl do_irq
	476	irq_restore_user_regs
477
478	.align 5
479	fiq:
480	get_fiq_stack
481	irq_save_user_regs /* someone ought to write a more */
482	bl do_fiq /* effiction fiq_save_user_regs */
483	irq_restore_user_regs
484
485	#else
486
487	.align 5
488	irq:
489	get_bad_stack
490	bad_save_user_regs
491	bl do_irq
492
493	.align 5
494	fiq:
495	get_bad_stack
496	bad_save_user_regs
497	bl do_fiq
498
499	#endif
500
501	/****************************************************************************/
502	/* */
503	/* Reset function: Use Watchdog to reset */
504	/* */
505	/****************************************************************************/
506
507	.align 5
508	.globl reset_cpu
509
510	reset_cpu:
53677ef1	511	ldr r1, =0x482e
2d5b561e WD	512	ldr r2, =IXP425_OSWK
2d5b561e WD	513	str r1, [r2]
53677ef1	514	ldr r1, =0x0fff
2d5b561e WD	515	ldr r2, =IXP425_OSWT
2d5b561e WD	516	str r1, [r2]
53677ef1	517	ldr r1, =0x5
2d5b561e WD	518	ldr r2, =IXP425_OSWE
	519	str r1, [r2]
	520	b reset_endless
	521
2d5b561e	522	reset_endless:
2d5b561e	523	b reset_endless