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PXA: pxafb: Add support for Sharp LQ038J7DH53
[people/ms/u-boot.git] / arch / arm / cpu / pxa / pxafb.c
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71f95118 1/*
8655b6f8
WD		 2 * PXA LCD Controller
3 *
71f95118
WD		 4 * (C) Copyright 2001-2002
5 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************/
27/* ** HEADER FILES */
28/************************************************************************/
29
71f95118
WD		 30#include <config.h>
31#include <common.h>
32#include <version.h>
33#include <stdarg.h>
71f95118 34#include <linux/types.h>
52cb4d4f 35#include <stdio_dev.h>
8655b6f8 36#include <lcd.h>
71f95118 37#include <asm/arch/pxa-regs.h>
3ba8bf7c 38#include <asm/io.h>
71f95118 39
8655b6f8 40/* #define DEBUG */
71f95118 41
8655b6f8 42#ifdef CONFIG_LCD
71f95118
WD		 43
44/*----------------------------------------------------------------------*/
71f95118 45/*
8655b6f8
WD		 46 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
47 * your display.
71f95118
WD		 48 */
49
8655b6f8
WD		 50#ifdef CONFIG_PXA_VGA
51/* LCD outputs connected to a video DAC */
52# define LCD_BPP LCD_COLOR8
71f95118
WD		 53
54/* you have to set lccr0 and lccr3 (including pcd) */
8655b6f8
WD		 55# define REG_LCCR0 0x003008f8
56# define REG_LCCR3 0x0300FF01
71f95118
WD		 57
58/* 640x480x16 @ 61 Hz */
8655b6f8 59vidinfo_t panel_info = {
9f80a20e
MV		 60 .vl_col = 640,
61 .vl_row = 480,
62 .vl_width = 640,
63 .vl_height = 480,
64 .vl_clkp = CONFIG_SYS_HIGH,
65 .vl_oep = CONFIG_SYS_HIGH,
66 .vl_hsp = CONFIG_SYS_HIGH,
67 .vl_vsp = CONFIG_SYS_HIGH,
68 .vl_dp = CONFIG_SYS_HIGH,
69 .vl_bpix = LCD_BPP,
70 .vl_lbw = 0,
71 .vl_splt = 0,
72 .vl_clor = 0,
73 .vl_tft = 1,
74 .vl_hpw = 40,
75 .vl_blw = 56,
76 .vl_elw = 56,
77 .vl_vpw = 20,
78 .vl_bfw = 8,
79 .vl_efw = 8,
71f95118
WD		 80};
81#endif /* CONFIG_PXA_VIDEO */
82
8655b6f8 83/*----------------------------------------------------------------------*/
71f95118
WD		 84#ifdef CONFIG_SHARP_LM8V31
85
8655b6f8
WD		 86# define LCD_BPP LCD_COLOR8
87# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
71f95118
WD		 88
89/* you have to set lccr0 and lccr3 (including pcd) */
8655b6f8
WD		 90# define REG_LCCR0 0x0030087C
91# define REG_LCCR3 0x0340FF08
92
93vidinfo_t panel_info = {
9f80a20e
MV		 94 .vl_col = 640,
95 .vl_row = 480,
96 .vl_width = 157,
97 .vl_height = 118,
98 .vl_clkp = CONFIG_SYS_HIGH,
99 .vl_oep = CONFIG_SYS_HIGH,
100 .vl_hsp = CONFIG_SYS_HIGH,
101 .vl_vsp = CONFIG_SYS_HIGH,
102 .vl_dp = CONFIG_SYS_HIGH,
103 .vl_bpix = LCD_BPP,
104 .vl_lbw = 0,
105 .vl_splt = 1,
106 .vl_clor = 1,
107 .vl_tft = 0,
108 .vl_hpw = 1,
109 .vl_blw = 3,
110 .vl_elw = 3,
111 .vl_vpw = 1,
112 .vl_bfw = 0,
113 .vl_efw = 0,
71f95118
WD		 114};
115#endif /* CONFIG_SHARP_LM8V31 */
9b92cf04
MV		 116/*----------------------------------------------------------------------*/
117#ifdef CONFIG_VOIPAC_LCD
118
119# define LCD_BPP LCD_COLOR8
120# define LCD_INVERT_COLORS
121
122/* you have to set lccr0 and lccr3 (including pcd) */
123# define REG_LCCR0 0x043008f8
124# define REG_LCCR3 0x0340FF08
125
126vidinfo_t panel_info = {
9f80a20e
MV		 127 .vl_col = 640,
128 .vl_row = 480,
129 .vl_width = 157,
130 .vl_height = 118,
131 .vl_clkp = CONFIG_SYS_HIGH,
132 .vl_oep = CONFIG_SYS_HIGH,
133 .vl_hsp = CONFIG_SYS_HIGH,
134 .vl_vsp = CONFIG_SYS_HIGH,
135 .vl_dp = CONFIG_SYS_HIGH,
136 .vl_bpix = LCD_BPP,
137 .vl_lbw = 0,
138 .vl_splt = 1,
139 .vl_clor = 1,
140 .vl_tft = 1,
141 .vl_hpw = 32,
142 .vl_blw = 144,
143 .vl_elw = 32,
144 .vl_vpw = 2,
145 .vl_bfw = 13,
146 .vl_efw = 30,
9b92cf04
MV		 147};
148#endif /* CONFIG_VOIPAC_LCD */
71f95118
WD		 149
150/*----------------------------------------------------------------------*/
8655b6f8
WD		 151#ifdef CONFIG_HITACHI_SX14
152/* Hitachi SX14Q004-ZZA color STN LCD */
153#define LCD_BPP LCD_COLOR8
71f95118 154
8655b6f8
WD		 155/* you have to set lccr0 and lccr3 (including pcd) */
156#define REG_LCCR0 0x00301079
157#define REG_LCCR3 0x0340FF20
158
159vidinfo_t panel_info = {
9f80a20e
MV		 160 .vl_col = 320,
161 .vl_row = 240,
162 .vl_width = 167,
163 .vl_height = 109,
164 .vl_clkp = CONFIG_SYS_HIGH,
165 .vl_oep = CONFIG_SYS_HIGH,
166 .vl_hsp = CONFIG_SYS_HIGH,
167 .vl_vsp = CONFIG_SYS_HIGH,
168 .vl_dp = CONFIG_SYS_HIGH,
169 .vl_bpix = LCD_BPP,
170 .vl_lbw = 1,
171 .vl_splt = 0,
172 .vl_clor = 1,
173 .vl_tft = 0,
174 .vl_hpw = 1,
175 .vl_blw = 1,
176 .vl_elw = 1,
177 .vl_vpw = 7,
178 .vl_bfw = 0,
179 .vl_efw = 0,
71f95118 180};
8655b6f8 181#endif /* CONFIG_HITACHI_SX14 */
71f95118 182
546cd608
MV		 183/*----------------------------------------------------------------------*/
184#ifdef CONFIG_LMS283GF05
185
186# define LCD_BPP LCD_COLOR8
07517e7f 187/*# define LCD_INVERT_COLORS*/
546cd608
MV		 188
189/* you have to set lccr0 and lccr3 (including pcd) */
190# define REG_LCCR0 0x043008f8
191# define REG_LCCR3 0x03b00009
192
193vidinfo_t panel_info = {
9f80a20e
MV		 194 .vl_col = 240,
195 .vl_row = 320,
196 .vl_width = 240,
197 .vl_height = 320,
198 .vl_clkp = CONFIG_SYS_HIGH,
199 .vl_oep = CONFIG_SYS_LOW,
200 .vl_hsp = CONFIG_SYS_LOW,
201 .vl_vsp = CONFIG_SYS_LOW,
202 .vl_dp = CONFIG_SYS_HIGH,
203 .vl_bpix = LCD_BPP,
204 .vl_lbw = 0,
205 .vl_splt = 1,
206 .vl_clor = 1,
207 .vl_tft = 1,
208 .vl_hpw = 4,
209 .vl_blw = 4,
210 .vl_elw = 8,
211 .vl_vpw = 4,
212 .vl_bfw = 4,
213 .vl_efw = 8,
546cd608
MV		 214};
215#endif /* CONFIG_LMS283GF05 */
216
71f95118
WD		 217/*----------------------------------------------------------------------*/
218
f7d58d91
MV		 219#ifdef CONFIG_ACX517AKN
220
221# define LCD_BPP LCD_COLOR8
222
223/* you have to set lccr0 and lccr3 (including pcd) */
224# define REG_LCCR0 0x003008f9
225# define REG_LCCR3 0x03700006
226
227vidinfo_t panel_info = {
228 .vl_col = 320,
229 .vl_row = 320,
230 .vl_width = 320,
231 .vl_height = 320,
232 .vl_clkp = CONFIG_SYS_HIGH,
233 .vl_oep = CONFIG_SYS_LOW,
234 .vl_hsp = CONFIG_SYS_LOW,
235 .vl_vsp = CONFIG_SYS_LOW,
236 .vl_dp = CONFIG_SYS_HIGH,
237 .vl_bpix = LCD_BPP,
238 .vl_lbw = 0,
239 .vl_splt = 1,
240 .vl_clor = 1,
241 .vl_tft = 1,
242 .vl_hpw = 0x04,
243 .vl_blw = 0x1c,
244 .vl_elw = 0x08,
245 .vl_vpw = 0x01,
246 .vl_bfw = 0x07,
247 .vl_efw = 0x08,
248};
249#endif /* CONFIG_ACX517AKN */
250
251/*----------------------------------------------------------------------*/
252
42222be4
MV		 253#ifdef CONFIG_LQ038J7DH53
254
255# define LCD_BPP LCD_COLOR8
256
257/* you have to set lccr0 and lccr3 (including pcd) */
258# define REG_LCCR0 0x003008f9
259# define REG_LCCR3 0x03700004
260
261vidinfo_t panel_info = {
262 .vl_col = 320,
263 .vl_row = 480,
264 .vl_width = 320,
265 .vl_height = 480,
266 .vl_clkp = CONFIG_SYS_HIGH,
267 .vl_oep = CONFIG_SYS_LOW,
268 .vl_hsp = CONFIG_SYS_LOW,
269 .vl_vsp = CONFIG_SYS_LOW,
270 .vl_dp = CONFIG_SYS_HIGH,
271 .vl_bpix = LCD_BPP,
272 .vl_lbw = 0,
273 .vl_splt = 1,
274 .vl_clor = 1,
275 .vl_tft = 1,
276 .vl_hpw = 0x04,
277 .vl_blw = 0x20,
278 .vl_elw = 0x01,
279 .vl_vpw = 0x01,
280 .vl_bfw = 0x04,
281 .vl_efw = 0x01,
282};
283#endif /* CONFIG_ACX517AKN */
284
285/*----------------------------------------------------------------------*/
286
8655b6f8
WD		 287#if LCD_BPP == LCD_COLOR8
288void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
71f95118 289#endif
8655b6f8
WD		 290#if LCD_BPP == LCD_MONOCHROME
291void lcd_initcolregs (void);
71f95118
WD		 292#endif
293
8655b6f8
WD		 294#ifdef NOT_USED_SO_FAR
295void lcd_disable (void);
296void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
297#endif /* NOT_USED_SO_FAR */
71f95118 298
8655b6f8
WD		 299void lcd_ctrl_init (void *lcdbase);
300void lcd_enable (void);
71f95118 301
8655b6f8
WD		 302int lcd_line_length;
303int lcd_color_fg;
304int lcd_color_bg;
71f95118 305
8655b6f8
WD		 306void *lcd_base; /* Start of framebuffer memory */
307void *lcd_console_address; /* Start of console buffer */
71f95118 308
8655b6f8
WD		 309short console_col;
310short console_row;
71f95118 311
8655b6f8
WD		 312static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
313static void pxafb_setup_gpio (vidinfo_t *vid);
314static void pxafb_enable_controller (vidinfo_t *vid);
315static int pxafb_init (vidinfo_t *vid);
71f95118
WD		 316/************************************************************************/
317
71f95118 318/************************************************************************/
8655b6f8 319/* --------------- PXA chipset specific functions ------------------- */
71f95118
WD		 320/************************************************************************/
321
8655b6f8 322void lcd_ctrl_init (void *lcdbase)
71f95118 323{
8bde7f77 324 pxafb_init_mem(lcdbase, &panel_info);
71f95118
WD		 325 pxafb_init(&panel_info);
326 pxafb_setup_gpio(&panel_info);
327 pxafb_enable_controller(&panel_info);
328}
329
330/*----------------------------------------------------------------------*/
8655b6f8
WD		 331#ifdef NOT_USED_SO_FAR
332void
71f95118
WD		 333lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
334{
335}
8655b6f8 336#endif /* NOT_USED_SO_FAR */
71f95118
WD		 337
338/*----------------------------------------------------------------------*/
71f95118 339#if LCD_BPP == LCD_COLOR8
8655b6f8 340void
71f95118
WD		 341lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
342{
343 struct pxafb_info *fbi = &panel_info.pxa;
344 unsigned short *palette = (unsigned short *)fbi->palette;
345 u_int val;
8bde7f77 346
71f95118
WD		 347 if (regno < fbi->palette_size) {
348 val = ((red << 8) & 0xf800);
349 val |= ((green << 4) & 0x07e0);
350 val |= (blue & 0x001f);
351
352#ifdef LCD_INVERT_COLORS
353 palette[regno] = ~val;
354#else
8655b6f8 355 palette[regno] = val;
71f95118
WD		 356#endif
357 }
358
359 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
360 regno, &palette[regno],
361 red, green, blue,
362 palette[regno]);
363}
8655b6f8 364#endif /* LCD_COLOR8 */
71f95118
WD		 365
366/*----------------------------------------------------------------------*/
71f95118 367#if LCD_BPP == LCD_MONOCHROME
71f95118
WD		 368void lcd_initcolregs (void)
369{
8655b6f8
WD		 370 struct pxafb_info *fbi = &panel_info.pxa;
371 cmap = (ushort *)fbi->palette;
71f95118
WD		 372 ushort regno;
373
374 for (regno = 0; regno < 16; regno++) {
8655b6f8
WD		 375 cmap[regno * 2] = 0;
376 cmap[(regno * 2) + 1] = regno & 0x0f;
71f95118
WD		 377 }
378}
8655b6f8 379#endif /* LCD_MONOCHROME */
71f95118
WD		 380
381/*----------------------------------------------------------------------*/
8655b6f8 382void lcd_enable (void)
71f95118 383{
71f95118 384}
71f95118
WD		 385
386/*----------------------------------------------------------------------*/
71f95118
WD		 387#ifdef NOT_USED_SO_FAR
388static void lcd_disable (void)
389{
390}
8655b6f8 391#endif /* NOT_USED_SO_FAR */
71f95118 392
8655b6f8 393/*----------------------------------------------------------------------*/
71f95118
WD		 394
395/************************************************************************/
8655b6f8 396/* ** PXA255 specific routines */
71f95118
WD		 397/************************************************************************/
398
8655b6f8
WD		 399/*
400 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
401 * descriptors and palette areas.
402 */
403ulong calc_fbsize (void)
71f95118 404{
8655b6f8
WD		 405 ulong size;
406 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
71f95118 407
8655b6f8
WD		 408 size = line_length * panel_info.vl_row;
409 size += PAGE_SIZE;
71f95118 410
8655b6f8 411 return size;
71f95118
WD		 412}
413
8655b6f8 414static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
71f95118
WD		 415{
416 u_long palette_mem_size;
417 struct pxafb_info *fbi = &vid->pxa;
418 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
419
420 fbi->screen = (u_long)lcdbase;
421
422 fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
423 palette_mem_size = fbi->palette_size * sizeof(u16);
8655b6f8 424
71f95118
WD		 425 debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
426 /* locate palette and descs at end of page following fb */
8655b6f8 427 fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
71f95118
WD		 428
429 return 0;
430}
8c35d0c5
MV		 431#ifdef CONFIG_CPU_MONAHANS
432static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
433#else
8655b6f8 434static void pxafb_setup_gpio (vidinfo_t *vid)
71f95118
WD		 435{
436 u_long lccr0;
437
438 /*
439 * setup is based on type of panel supported
440 */
441
442 lccr0 = vid->pxa.reg_lccr0;
443
444 /* 4 bit interface */
445 if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
446 {
447 debug("Setting GPIO for 4 bit data\n");
448 /* bits 58-61 */
3ba8bf7c
MV		 449 writel(readl(GPDR1) | (0xf << 26), GPDR1);
450 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
451 GAFR1_U);
71f95118
WD		 452
453 /* bits 74-77 */
3ba8bf7c
MV		 454 writel(readl(GPDR2) | (0xf << 10), GPDR2);
455 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
456 GAFR2_L);
71f95118
WD		 457 }
458
459 /* 8 bit interface */
460 else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
8655b6f8 461 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
71f95118
WD		 462 {
463 debug("Setting GPIO for 8 bit data\n");
464 /* bits 58-65 */
3ba8bf7c
MV		 465 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
466 writel(readl(GPDR2) | (0x3), GPDR2);
71f95118 467
3ba8bf7c
MV		 468 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
469 GAFR1_U);
470 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
71f95118
WD		 471
472 /* bits 74-77 */
3ba8bf7c
MV		 473 writel(readl(GPDR2) | (0xf << 10), GPDR2);
474 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
475 GAFR2_L);
71f95118
WD		 476 }
477
478 /* 16 bit interface */
479 else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
480 {
481 debug("Setting GPIO for 16 bit data\n");
482 /* bits 58-77 */
3ba8bf7c
MV		 483 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
484 writel(readl(GPDR2) | 0x00003fff, GPDR2);
71f95118 485
3ba8bf7c
MV		 486 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
487 GAFR1_U);
488 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
71f95118
WD		 489 }
490 else
491 {
492 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
493 }
494}
8c35d0c5 495#endif
71f95118 496
8655b6f8 497static void pxafb_enable_controller (vidinfo_t *vid)
71f95118
WD		 498{
499 debug("Enabling LCD controller\n");
500
501 /* Sequence from 11.7.10 */
3ba8bf7c
MV		 502 writel(vid->pxa.reg_lccr3, LCCR3);
503 writel(vid->pxa.reg_lccr2, LCCR2);
504 writel(vid->pxa.reg_lccr1, LCCR1);
505 writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
506 writel(vid->pxa.fdadr0, FDADR0);
507 writel(vid->pxa.fdadr1, FDADR1);
508 writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
71f95118 509
8c35d0c5 510#ifdef CONFIG_CPU_MONAHANS
3ba8bf7c 511 writel(readl(CKENA) | CKENA_1_LCD, CKENA);
8c35d0c5 512#else
3ba8bf7c 513 writel(readl(CKEN) | CKEN16_LCD, CKEN);
8c35d0c5 514#endif
71f95118 515
3ba8bf7c
MV		 516 debug("FDADR0 = 0x%08x\n", readl(FDADR0));
517 debug("FDADR1 = 0x%08x\n", readl(FDADR1));
518 debug("LCCR0 = 0x%08x\n", readl(LCCR0));
519 debug("LCCR1 = 0x%08x\n", readl(LCCR1));
520 debug("LCCR2 = 0x%08x\n", readl(LCCR2));
521 debug("LCCR3 = 0x%08x\n", readl(LCCR3));
71f95118
WD		 522}
523
8655b6f8 524static int pxafb_init (vidinfo_t *vid)
71f95118
WD		 525{
526 struct pxafb_info *fbi = &vid->pxa;
527
528 debug("Configuring PXA LCD\n");
529
530 fbi->reg_lccr0 = REG_LCCR0;
531 fbi->reg_lccr3 = REG_LCCR3;
532
533 debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
534 vid->vl_col, vid->vl_hpw,
535 vid->vl_blw, vid->vl_elw);
536 debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
537 vid->vl_row, vid->vl_vpw,
538 vid->vl_bfw, vid->vl_efw);
539
540 fbi->reg_lccr1 =
541 LCCR1_DisWdth(vid->vl_col) +
542 LCCR1_HorSnchWdth(vid->vl_hpw) +
543 LCCR1_BegLnDel(vid->vl_blw) +
544 LCCR1_EndLnDel(vid->vl_elw);
8bde7f77 545
71f95118
WD		 546 fbi->reg_lccr2 =
547 LCCR2_DisHght(vid->vl_row) +
548 LCCR2_VrtSnchWdth(vid->vl_vpw) +
549 LCCR2_BegFrmDel(vid->vl_bfw) +
550 LCCR2_EndFrmDel(vid->vl_efw);
551
8bde7f77 552 fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
8655b6f8
WD		 553 fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
554 | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
8bde7f77 555
71f95118
WD		 556
557 /* setup dma descriptors */
558 fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
559 fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
560 fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
561
562 #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
8bde7f77
WD		 563 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
564 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
565
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WD		 566 /* populate descriptors */
567 fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
568 fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
569 fbi->dmadesc_fblow->fidr = 0;
570 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
571
572 fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
8bde7f77 573
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WD		 574 fbi->dmadesc_fbhigh->fsadr = fbi->screen;
575 fbi->dmadesc_fbhigh->fidr = 0;
576 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
577
578 fbi->dmadesc_palette->fsadr = fbi->palette;
579 fbi->dmadesc_palette->fidr = 0;
580 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
581
582 if( NBITS(vid->vl_bpix) < 12)
583 {
584 /* assume any mode with <12 bpp is palette driven */
585 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
586 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
587 /* flips back and forth between pal and fbhigh */
8bde7f77 588 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
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WD		 589 }
590 else
591 {
592 /* palette shouldn't be loaded in true-color mode */
593 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
594 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
595 }
596
597 debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
598 debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
599 debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
600
601 debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
602 debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
603 debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
604
605 debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
606 debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
607 debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
608
609 debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
610 debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
611 debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
8bde7f77 612
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WD		 613 return 0;
614}
615
616/************************************************************************/
617/************************************************************************/
618
619#endif /* CONFIG_LCD */
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