[people/ms/u-boot.git] / arch / arm / cpu / s3c44b0 / start.S

/*
 * Startup Code for S3C44B0 CPU-core
 *
 * (C) Copyright 2004
 * DAVE Srl
 *
 * http://www.dave-tech.it
 * http://www.wawnet.biz
 * mailto:info@wawnet.biz
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>

/*
 * Jump vector table
 */


.globl _start
_start:	b       reset
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000
	add	pc, pc, #0x0c000000

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate u-boot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _image_copy_end_ofs
_image_copy_end_ofs:
	.word __image_copy_end - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	bl	lowlevel_init
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code(addr_moni)
 *
 * This function relocates the monitor code.
 */
	.globl	relocate_code
relocate_code:
	mov	r6, r0	/* save addr of destination */

	adr	r0, _start
	subs	r9, r6, r0		/* r9 <- relocation offset */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _image_copy_end_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	bx	lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	bx	lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */

#define INTCON (0x01c00000+0x200000)
#define INTMSK (0x01c00000+0x20000c)
#define LOCKTIME (0x01c00000+0x18000c)
#define PLLCON (0x01c00000+0x180000)
#define CLKCON (0x01c00000+0x180004)
#define WTCON (0x01c00000+0x130000)
cpu_init_crit:
	/* disable watch dog */
	ldr	r0, =WTCON
	ldr	r1, =0x0
	str	r1, [r0]

	/*
	 * mask all IRQs by clearing all bits in the INTMRs
	 */
	ldr	r1,=INTMSK
	ldr	r0, =0x03fffeff
	str	r0, [r1]

	ldr	r1, =INTCON
	ldr	r0, =0x05
	str	r0, [r1]

	/* Set Clock Control Register */
	ldr	r1, =LOCKTIME
	ldrb	r0, =800
	strb	r0, [r1]

	ldr	r1, =PLLCON

#if CONFIG_S3C44B0_CLOCK_SPEED==66
	ldr	r0, =0x34031	/* 66MHz (Quartz=11MHz) */
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
	ldr	r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif

	str	r0, [r1]

	ldr	r1,=CLKCON
	ldr	r0, =0x7ff8
	str	r0, [r1]

	mov	pc, lr


/*************************************************/
/*	interrupt vectors	*/
/*************************************************/
real_vectors:
	b	reset
	b	undefined_instruction
	b	software_interrupt
	b	prefetch_abort
	b	data_abort
	b	not_used
	b	irq
	b	fiq

/*************************************************/

undefined_instruction:
	mov	r6, #3
	b	reset

software_interrupt:
	mov	r6, #4
	b	reset

prefetch_abort:
	mov	r6, #5
	b	reset

data_abort:
	mov	r6, #6
	b	reset

not_used:
	/* we *should* never reach this */
	mov	r6, #7
	b	reset

irq:
	mov	r6, #8
	b	reset

fiq:
	mov	r6, #9
	b	reset
Commit	Line	Data
074cff0d WD	1	/*
	2	* Startup Code for S3C44B0 CPU-core
	3	*
	4	* (C) Copyright 2004
	5	* DAVE Srl
	6	*
	7	* http://www.dave-tech.it
	8	* http://www.wawnet.biz
	9	* mailto:info@wawnet.biz
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
25ddd1fb	30	#include <asm-offsets.h>
074cff0d WD	31	#include <config.h>
	32	#include <version.h>
	33
074cff0d WD	34	/*
	35	* Jump vector table
	36	*/
	37
	38
	39	.globl _start
	40	_start: b reset
	41	add pc, pc, #0x0c000000
	42	add pc, pc, #0x0c000000
	43	add pc, pc, #0x0c000000
	44	add pc, pc, #0x0c000000
	45	add pc, pc, #0x0c000000
	46	add pc, pc, #0x0c000000
	47	add pc, pc, #0x0c000000
	48
	49	.balignl 16,0xdeadbeef
	50
	51
	52	/*
	53	*************************************************************************
	54	*
	55	* Startup Code (reset vector)
	56	*
	57	* do important init only if we don't start from memory!
	58	* relocate u-boot to ram
	59	* setup stack
	60	* jump to second stage
	61	*
	62	*************************************************************************
	63	*/
	64
0110955a	65	.globl _TEXT_BASE
074cff0d	66	_TEXT_BASE:
508611bc BT	67	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
	68	.word CONFIG_SPL_TEXT_BASE
	69	#else
14d0a02a	70	.word CONFIG_SYS_TEXT_BASE
508611bc	71	#endif
074cff0d	72
074cff0d	73	/*
42dfe7a1	74	* These are defined in the board-specific linker script.
3336ca60 AA	75	* Subtracting _start from them lets the linker put their
	76	* relative position in the executable instead of leaving
	77	* them null.
074cff0d	78	*/
3336ca60 AA	79	.globl _bss_start_ofs
	80	_bss_start_ofs:
	81	.word __bss_start - _start
42dfe7a1	82
7086e91b BT	83	.globl _image_copy_end_ofs
	84	_image_copy_end_ofs:
	85	.word __image_copy_end - _start
	86
3336ca60 AA	87	.globl _bss_end_ofs
3336ca60 AA	88	_bss_end_ofs:
3929fb0a	89	.word __bss_end - _start
074cff0d	90
f326cbba PYC	91	.globl _end_ofs
	92	_end_ofs:
	93	.word _end - _start
	94
074cff0d WD	95	#ifdef CONFIG_USE_IRQ
	96	/* IRQ stack memory (calculated at run-time) */
	97	.globl IRQ_STACK_START
	98	IRQ_STACK_START:
	99	.word 0x0badc0de
	100
	101	/* IRQ stack memory (calculated at run-time) */
	102	.globl FIQ_STACK_START
	103	FIQ_STACK_START:
	104	.word 0x0badc0de
	105	#endif
	106
0110955a HS	107	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	108	.globl IRQ_STACK_START_IN
	109	IRQ_STACK_START_IN:
	110	.word 0x0badc0de
	111
0110955a HS	112	/*
	113	* the actual reset code
	114	*/
	115
	116	reset:
	117	/*
	118	* set the cpu to SVC32 mode
	119	*/
	120	mrs r0,cpsr
	121	bic r0,r0,#0x1f
	122	orr r0,r0,#0xd3
	123	msr cpsr,r0
	124
	125	/*
	126	* we do sys-critical inits only at reboot,
	127	* not when booting from ram!
	128	*/
	129	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	130	bl cpu_init_crit
	131	/*
	132	* before relocating, we have to setup RAM timing
	133	* because memory timing is board-dependend, you will
	134	* find a lowlevel_init.S in your board directory.
	135	*/
	136	bl lowlevel_init
	137	#endif
	138
e05e5de7	139	bl _main
0110955a HS	140
	141	/------------------------------------------------------------------------------/
	142
	143	/*
5c6db120	144	* void relocate_code(addr_moni)
0110955a	145	*
959eaa74	146	* This function relocates the monitor code.
0110955a HS	147	*/
	148	.globl relocate_code
	149	relocate_code:
5c6db120	150	mov r6, r0 /* save addr of destination */
0110955a	151
0110955a	152	adr r0, _start
4b3db1cd	153	subs r9, r6, r0 /* r9 <- relocation offset */
e05e5de7	154	beq relocate_done /* skip relocation */
a78fb68f	155	mov r1, r6 /* r1 <- scratch for copy_loop */
7086e91b	156	ldr r3, _image_copy_end_ofs
3336ca60	157	add r2, r0, r3 /* r2 <- source end address */
0110955a	158
0110955a	159	copy_loop:
4b3db1cd BT	160	ldmia r0!, {r10-r11} /* copy from source address [r0] */
4b3db1cd BT	161	stmia r1!, {r10-r11} /* copy to target address [r1] */
da90d4ce AA	162	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	163	blo copy_loop
0110955a	164
401bb30b	165	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	166	/*
	167	* fix .rel.dyn relocations
	168	*/
	169	ldr r0, _TEXT_BASE /* r0 <- Text base */
3336ca60 AA	170	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	171	add r10, r10, r0 /* r10 <- sym table in FLASH */
	172	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	173	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	174	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	175	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
0110955a	176	fixloop:
3336ca60 AA	177	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	178	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	179	ldr r1, [r2, #4]
1f52d89f AB	180	and r7, r1, #0xff
1f52d89f AB	181	cmp r7, #23 /* relative fixup? */
3336ca60	182	beq fixrel
1f52d89f	183	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	184	beq fixabs
	185	/* ignore unknown type of fixup */
	186	b fixnext
	187	fixabs:
	188	/* absolute fix: set location to (offset) symbol value */
	189	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	190	add r1, r10, r1 /* r1 <- address of symbol in table */
	191	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	192	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	193	b fixnext
	194	fixrel:
	195	/* relative fix: increase location by offset */
	196	ldr r1, [r0]
	197	add r1, r1, r9
	198	fixnext:
	199	str r1, [r0]
	200	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
0110955a	201	cmp r2, r3
79e63139	202	blo fixloop
0110955a	203	#endif
0110955a	204
e05e5de7	205	relocate_done:
074cff0d	206
e05e5de7	207	bx lr
3336ca60 AA	208
	209	_rel_dyn_start_ofs:
	210	.word __rel_dyn_start - _start
	211	_rel_dyn_end_ofs:
	212	.word __rel_dyn_end - _start
	213	_dynsym_start_ofs:
	214	.word __dynsym_start - _start
0110955a	215
e05e5de7 AA	216	.globl c_runtime_cpu_setup
	217	c_runtime_cpu_setup:
	218
	219	bx lr
	220
074cff0d WD	221	/*
	222	*************************************************************************
	223	*
	224	* CPU_init_critical registers
	225	*
	226	* setup important registers
	227	* setup memory timing
	228	*
	229	*************************************************************************
	230	*/
	231
	232	#define INTCON (0x01c00000+0x200000)
	233	#define INTMSK (0x01c00000+0x20000c)
	234	#define LOCKTIME (0x01c00000+0x18000c)
	235	#define PLLCON (0x01c00000+0x180000)
	236	#define CLKCON (0x01c00000+0x180004)
	237	#define WTCON (0x01c00000+0x130000)
	238	cpu_init_crit:
	239	/* disable watch dog */
53677ef1	240	ldr r0, =WTCON
074cff0d WD	241	ldr r1, =0x0
	242	str r1, [r0]
	243
	244	/*
	245	* mask all IRQs by clearing all bits in the INTMRs
	246	*/
	247	ldr r1,=INTMSK
	248	ldr r0, =0x03fffeff
	249	str r0, [r1]
	250
	251	ldr r1, =INTCON
	252	ldr r0, =0x05
	253	str r0, [r1]
	254
	255	/* Set Clock Control Register */
	256	ldr r1, =LOCKTIME
	257	ldrb r0, =800
	258	strb r0, [r1]
	259
	260	ldr r1, =PLLCON
	261
	262	#if CONFIG_S3C44B0_CLOCK_SPEED==66
53677ef1	263	ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
074cff0d WD	264	#elif CONFIG_S3C44B0_CLOCK_SPEED==75
	265	ldr r0, =0x610c1 /B2: Xtal=20mhz Fclk=75MHz /
	266	#else
	267	# error CONFIG_S3C44B0_CLOCK_SPEED undefined
	268	#endif
	269
	270	str r0, [r1]
	271
	272	ldr r1,=CLKCON
	273	ldr r0, =0x7ff8
	274	str r0, [r1]
	275
	276	mov pc, lr
	277
	278
	279	/*************************************************/
	280	/* interrupt vectors */
	281	/*************************************************/
	282	real_vectors:
	283	b reset
	284	b undefined_instruction
	285	b software_interrupt
	286	b prefetch_abort
	287	b data_abort
	288	b not_used
	289	b irq
	290	b fiq
	291
	292	/*************************************************/
	293
	294	undefined_instruction:
	295	mov r6, #3
	296	b reset
	297
	298	software_interrupt:
	299	mov r6, #4
	300	b reset
	301
	302	prefetch_abort:
	303	mov r6, #5
	304	b reset
	305
	306	data_abort:
	307	mov r6, #6
	308	b reset
	309
	310	not_used:
	311	/* we should never reach this */
	312	mov r6, #7
	313	b reset
	314
	315	irq:
	316	mov r6, #8
	317	b reset
	318
	319	fiq:
	320	mov r6, #9
	321	b reset