[people/ms/u-boot.git] / arch / arm / cpu / tegra20-common / clock.c

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* Tegra20 Clock control functions */

#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/timer.h>
#include <div64.h>
#include <fdtdec.h>

/*
 * Clock types that we can use as a source. The Tegra20 has muxes for the
 * peripheral clocks, and in most cases there are four options for the clock
 * source. This gives us a clock 'type' and exploits what commonality exists
 * in the device.
 *
 * Letters are obvious, except for T which means CLK_M, and S which means the
 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
 * datasheet) and PLL_M are different things. The former is the basic
 * clock supplied to the SOC from an external oscillator. The latter is the
 * memory clock PLL.
 *
 * See definitions in clock_id in the header file.
 */
enum clock_type_id {
	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
	CLOCK_TYPE_MCPA,	/* and so on */
	CLOCK_TYPE_MCPT,
	CLOCK_TYPE_PCM,
	CLOCK_TYPE_PCMT,
	CLOCK_TYPE_PCMT16,	/* CLOCK_TYPE_PCMT with 16-bit divider */
	CLOCK_TYPE_PCXTS,
	CLOCK_TYPE_PDCT,

	CLOCK_TYPE_COUNT,
	CLOCK_TYPE_NONE = -1,	/* invalid clock type */
};

enum {
	CLOCK_MAX_MUX	= 4	/* number of source options for each clock */
};

/*
 * Clock source mux for each clock type. This just converts our enum into
 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
 * is special as it has 5 sources. Since it also has a different number of
 * bits in its register for the source, we just handle it with a special
 * case in the code.
 */
#define CLK(x) CLOCK_ID_ ## x
static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC)	},
	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO)	},
	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC)	},
	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE)	},
	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(XCPU),	CLK(OSC)	},
	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC)	},
};

/*
 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
 * not in the header file since it is for purely internal use - we want
 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
 * confusion bewteen PERIPH_ID_... and PERIPHC_...
 *
 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
 * confusing.
 *
 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
 * use it for reset, clock enable, clock source/divider and even pinmuxing
 * if you can.
 */
enum periphc_internal_id {
	/* 0x00 */
	PERIPHC_I2S1,
	PERIPHC_I2S2,
	PERIPHC_SPDIF_OUT,
	PERIPHC_SPDIF_IN,
	PERIPHC_PWM,
	PERIPHC_SPI1,
	PERIPHC_SPI2,
	PERIPHC_SPI3,

	/* 0x08 */
	PERIPHC_XIO,
	PERIPHC_I2C1,
	PERIPHC_DVC_I2C,
	PERIPHC_TWC,
	PERIPHC_0c,
	PERIPHC_10,	/* PERIPHC_SPI1, what is this really? */
	PERIPHC_DISP1,
	PERIPHC_DISP2,

	/* 0x10 */
	PERIPHC_CVE,
	PERIPHC_IDE0,
	PERIPHC_VI,
	PERIPHC_1c,
	PERIPHC_SDMMC1,
	PERIPHC_SDMMC2,
	PERIPHC_G3D,
	PERIPHC_G2D,

	/* 0x18 */
	PERIPHC_NDFLASH,
	PERIPHC_SDMMC4,
	PERIPHC_VFIR,
	PERIPHC_EPP,
	PERIPHC_MPE,
	PERIPHC_MIPI,
	PERIPHC_UART1,
	PERIPHC_UART2,

	/* 0x20 */
	PERIPHC_HOST1X,
	PERIPHC_21,
	PERIPHC_TVO,
	PERIPHC_HDMI,
	PERIPHC_24,
	PERIPHC_TVDAC,
	PERIPHC_I2C2,
	PERIPHC_EMC,

	/* 0x28 */
	PERIPHC_UART3,
	PERIPHC_29,
	PERIPHC_VI_SENSOR,
	PERIPHC_2b,
	PERIPHC_2c,
	PERIPHC_SPI4,
	PERIPHC_I2C3,
	PERIPHC_SDMMC3,

	/* 0x30 */
	PERIPHC_UART4,
	PERIPHC_UART5,
	PERIPHC_VDE,
	PERIPHC_OWR,
	PERIPHC_NOR,
	PERIPHC_CSITE,

	PERIPHC_COUNT,

	PERIPHC_NONE = -1,
};

/*
 * Clock type for each peripheral clock source. We put the name in each
 * record just so it is easy to match things up
 */
#define TYPE(name, type) type
static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
	/* 0x00 */
	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PCM),
	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PCXTS),
	TYPE(PERIPHC_SPI1,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_SPI22,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_SPI3,	CLOCK_TYPE_PCMT),

	/* 0x08 */
	TYPE(PERIPHC_XIO,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_DVC_I2C,	CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_TWC,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SPI1,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PDCT),
	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PDCT),

	/* 0x10 */
	TYPE(PERIPHC_CVE,	CLOCK_TYPE_PDCT),
	TYPE(PERIPHC_IDE0,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),

	/* 0x18 */
	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_EPP,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_MPE,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_MIPI,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PCMT),

	/* 0x20 */
	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
	TYPE(PERIPHC_TVO,	CLOCK_TYPE_PDCT),
	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PDCT),
	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
	TYPE(PERIPHC_TVDAC,	CLOCK_TYPE_PDCT),
	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),

	/* 0x28 */
	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
	TYPE(PERIPHC_SPI4,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PCMT16),
	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PCMT),

	/* 0x30 */
	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PCMT),
	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PCMT),
};

/*
 * This array translates a periph_id to a periphc_internal_id
 *
 * Not present/matched up:
 *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
 *	SPDIF - which is both 0x08 and 0x0c
 *
 */
#define NONE(name) (-1)
#define OFFSET(name, value) PERIPHC_ ## name
static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
	/* Low word: 31:0 */
	NONE(CPU),
	NONE(RESERVED1),
	NONE(RESERVED2),
	NONE(AC97),
	NONE(RTC),
	NONE(TMR),
	PERIPHC_UART1,
	PERIPHC_UART2,	/* and vfir 0x68 */

	/* 0x08 */
	NONE(GPIO),
	PERIPHC_SDMMC2,
	NONE(SPDIF),		/* 0x08 and 0x0c, unclear which to use */
	PERIPHC_I2S1,
	PERIPHC_I2C1,
	PERIPHC_NDFLASH,
	PERIPHC_SDMMC1,
	PERIPHC_SDMMC4,

	/* 0x10 */
	PERIPHC_TWC,
	PERIPHC_PWM,
	PERIPHC_I2S2,
	PERIPHC_EPP,
	PERIPHC_VI,
	PERIPHC_G2D,
	NONE(USBD),
	NONE(ISP),

	/* 0x18 */
	PERIPHC_G3D,
	PERIPHC_IDE0,
	PERIPHC_DISP2,
	PERIPHC_DISP1,
	PERIPHC_HOST1X,
	NONE(VCP),
	NONE(RESERVED30),
	NONE(CACHE2),

	/* Middle word: 63:32 */
	NONE(MEM),
	NONE(AHBDMA),
	NONE(APBDMA),
	NONE(RESERVED35),
	NONE(KBC),
	NONE(STAT_MON),
	NONE(PMC),
	NONE(FUSE),

	/* 0x28 */
	NONE(KFUSE),
	NONE(SBC1),	/* SBC1, 0x34, is this SPI1? */
	PERIPHC_NOR,
	PERIPHC_SPI1,
	PERIPHC_SPI2,
	PERIPHC_XIO,
	PERIPHC_SPI3,
	PERIPHC_DVC_I2C,

	/* 0x30 */
	NONE(DSI),
	PERIPHC_TVO,	/* also CVE 0x40 */
	PERIPHC_MIPI,
	PERIPHC_HDMI,
	PERIPHC_CSITE,
	PERIPHC_TVDAC,
	PERIPHC_I2C2,
	PERIPHC_UART3,

	/* 0x38 */
	NONE(RESERVED56),
	PERIPHC_EMC,
	NONE(USB2),
	NONE(USB3),
	PERIPHC_MPE,
	PERIPHC_VDE,
	NONE(BSEA),
	NONE(BSEV),

	/* Upper word 95:64 */
	NONE(SPEEDO),
	PERIPHC_UART4,
	PERIPHC_UART5,
	PERIPHC_I2C3,
	PERIPHC_SPI4,
	PERIPHC_SDMMC3,
	NONE(PCIE),
	PERIPHC_OWR,

	/* 0x48 */
	NONE(AFI),
	NONE(CORESIGHT),
	NONE(PCIEXCLK),
	NONE(AVPUCQ),
	NONE(RESERVED76),
	NONE(RESERVED77),
	NONE(RESERVED78),
	NONE(RESERVED79),

	/* 0x50 */
	NONE(RESERVED80),
	NONE(RESERVED81),
	NONE(RESERVED82),
	NONE(RESERVED83),
	NONE(IRAMA),
	NONE(IRAMB),
	NONE(IRAMC),
	NONE(IRAMD),

	/* 0x58 */
	NONE(CRAM2),
};

/*
 * Get the oscillator frequency, from the corresponding hardware configuration
 * field. T20 has 4 frequencies that it supports.
 */
enum clock_osc_freq clock_get_osc_freq(void)
{
	struct clk_rst_ctlr *clkrst =
			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 reg;

	reg = readl(&clkrst->crc_osc_ctrl);
	return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}

/* Returns a pointer to the clock source register for a peripheral */
u32 *get_periph_source_reg(enum periph_id periph_id)
{
	struct clk_rst_ctlr *clkrst =
			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	enum periphc_internal_id internal_id;

	assert(clock_periph_id_isvalid(periph_id));
	internal_id = periph_id_to_internal_id[periph_id];
	assert(internal_id != -1);
	return &clkrst->crc_clk_src[internal_id];
}

/**
 * Given a peripheral ID and the required source clock, this returns which
 * value should be programmed into the source mux for that peripheral.
 *
 * There is special code here to handle the one source type with 5 sources.
 *
 * @param periph_id	peripheral to start
 * @param source	PLL id of required parent clock
 * @param mux_bits	Set to number of bits in mux register: 2 or 4
 * @param divider_bits	Set to number of divider bits (8 or 16)
 * @return mux value (0-4, or -1 if not found)
 */
int get_periph_clock_source(enum periph_id periph_id,
		enum clock_id parent, int *mux_bits, int *divider_bits)
{
	enum clock_type_id type;
	enum periphc_internal_id internal_id;
	int mux;

	assert(clock_periph_id_isvalid(periph_id));

	internal_id = periph_id_to_internal_id[periph_id];
	assert(periphc_internal_id_isvalid(internal_id));

	type = clock_periph_type[internal_id];
	assert(clock_type_id_isvalid(type));

	/*
	 * Special cases here for the clock with a 4-bit source mux and I2C
	 * with its 16-bit divisor
	 */
	if (type == CLOCK_TYPE_PCXTS)
		*mux_bits = MASK_BITS_31_28;
	else
		*mux_bits = MASK_BITS_31_30;
	if (type == CLOCK_TYPE_PCMT16)
		*divider_bits = 16;
	else
		*divider_bits = 8;

	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
		if (clock_source[type][mux] == parent)
			return mux;

	/*
	 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
	 * which is not in our table. If not, then they are asking for a
	 * source which this peripheral can't access through its mux.
	 */
	assert(type == CLOCK_TYPE_PCXTS);
	assert(parent == CLOCK_ID_SFROM32KHZ);
	if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
		return 4;	/* mux value for this clock */

	/* if we get here, either us or the caller has made a mistake */
	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
		parent);
	return -1;
}

void clock_set_enable(enum periph_id periph_id, int enable)
{
	struct clk_rst_ctlr *clkrst =
			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
	u32 reg;

	/* Enable/disable the clock to this peripheral */
	assert(clock_periph_id_isvalid(periph_id));
	reg = readl(clk);
	if (enable)
		reg |= PERIPH_MASK(periph_id);
	else
		reg &= ~PERIPH_MASK(periph_id);
	writel(reg, clk);
}

void reset_set_enable(enum periph_id periph_id, int enable)
{
	struct clk_rst_ctlr *clkrst =
			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
	u32 reg;

	/* Enable/disable reset to the peripheral */
	assert(clock_periph_id_isvalid(periph_id));
	reg = readl(reset);
	if (enable)
		reg |= PERIPH_MASK(periph_id);
	else
		reg &= ~PERIPH_MASK(periph_id);
	writel(reg, reset);
}

#ifdef CONFIG_OF_CONTROL
/*
 * Convert a device tree clock ID to our peripheral ID. They are mostly
 * the same but we are very cautious so we check that a valid clock ID is
 * provided.
 *
 * @param clk_id	Clock ID according to tegra20 device tree binding
 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
 */
enum periph_id clk_id_to_periph_id(int clk_id)
{
	if (clk_id > PERIPH_ID_COUNT)
		return PERIPH_ID_NONE;

	switch (clk_id) {
	case PERIPH_ID_RESERVED1:
	case PERIPH_ID_RESERVED2:
	case PERIPH_ID_RESERVED30:
	case PERIPH_ID_RESERVED35:
	case PERIPH_ID_RESERVED56:
	case PERIPH_ID_PCIEXCLK:
	case PERIPH_ID_RESERVED76:
	case PERIPH_ID_RESERVED77:
	case PERIPH_ID_RESERVED78:
	case PERIPH_ID_RESERVED79:
	case PERIPH_ID_RESERVED80:
	case PERIPH_ID_RESERVED81:
	case PERIPH_ID_RESERVED82:
	case PERIPH_ID_RESERVED83:
	case PERIPH_ID_RESERVED91:
		return PERIPH_ID_NONE;
	default:
		return clk_id;
	}
}
#endif /* CONFIG_OF_CONTROL */

void clock_early_init(void)
{
	/*
	 * PLLP output frequency set to 216MHz
	 * PLLC output frequency set to 600Mhz
	 *
	 * TODO: Can we calculate these values instead of hard-coding?
	 */
	switch (clock_get_osc_freq()) {
	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
		clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
		break;

	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
		clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
		break;

	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
		clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
		break;
	case CLOCK_OSC_FREQ_19_2:
	default:
		/*
		 * These are not supported. It is too early to print a
		 * message and the UART likely won't work anyway due to the
		 * oscillator being wrong.
		 */
		break;
	}
}

void arch_timer_init(void)
{
}

#define PMC_SATA_PWRGT 0x1ac
#define  PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
#define  PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)

#define PLLE_SS_CNTL 0x68
#define  PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
#define  PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
#define  PLLE_SS_CNTL_SSCBYP (1 << 12)
#define  PLLE_SS_CNTL_INTERP_RESET (1 << 11)
#define  PLLE_SS_CNTL_BYPASS_SS (1 << 10)
#define  PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)

#define PLLE_BASE 0x0e8
#define  PLLE_BASE_ENABLE_CML (1 << 31)
#define  PLLE_BASE_ENABLE (1 << 30)
#define  PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
#define  PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
#define  PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
#define  PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)

#define PLLE_MISC 0x0ec
#define  PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
#define  PLLE_MISC_PLL_READY (1 << 15)
#define  PLLE_MISC_LOCK (1 << 11)
#define  PLLE_MISC_LOCK_ENABLE (1 << 9)
#define  PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)

static int tegra_plle_train(void)
{
	unsigned int timeout = 2000;
	unsigned long value;

	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);

	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);

	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);

	do {
		value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
		if (value & PLLE_MISC_PLL_READY)
			break;

		udelay(100);
	} while (--timeout);

	if (timeout == 0) {
		error("timeout waiting for PLLE to become ready");
		return -ETIMEDOUT;
	}

	return 0;
}

int tegra_plle_enable(void)
{
	unsigned int timeout = 1000;
	u32 value;
	int err;

	/* disable PLLE clock */
	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
	value &= ~PLLE_BASE_ENABLE_CML;
	value &= ~PLLE_BASE_ENABLE;
	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);

	/* clear lock enable and setup field */
	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
	value &= ~PLLE_MISC_LOCK_ENABLE;
	value &= ~PLLE_MISC_SETUP_BASE(0xffff);
	value &= ~PLLE_MISC_SETUP_EXT(0x3);
	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);

	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
	if ((value & PLLE_MISC_PLL_READY) == 0) {
		err = tegra_plle_train();
		if (err < 0) {
			error("failed to train PLLE: %d", err);
			return err;
		}
	}

	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
	value |= PLLE_MISC_SETUP_BASE(0x7);
	value |= PLLE_MISC_LOCK_ENABLE;
	value |= PLLE_MISC_SETUP_EXT(0);
	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);

	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
	value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
		 PLLE_SS_CNTL_BYPASS_SS;
	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);

	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
	value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);

	do {
		value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
		if (value & PLLE_MISC_LOCK)
			break;

		udelay(2);
	} while (--timeout);

	if (timeout == 0) {
		error("timeout waiting for PLLE to lock");
		return -ETIMEDOUT;
	}

	udelay(50);

	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
	value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
	value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);

	value &= ~PLLE_SS_CNTL_SSCINC(0xff);
	value |= PLLE_SS_CNTL_SSCINC(0x01);

	value &= ~PLLE_SS_CNTL_SSCBYP;
	value &= ~PLLE_SS_CNTL_INTERP_RESET;
	value &= ~PLLE_SS_CNTL_BYPASS_SS;

	value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
	value |= PLLE_SS_CNTL_SSCMAX(0x24);
	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);

	return 0;
}
Commit	Line	Data
b4ba2be8 SG	1	/*
b4ba2be8 SG	2	* Copyright (c) 2011 The Chromium OS Authors.
b4ba2be8	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
b4ba2be8 SG	5	*/
b4ba2be8 SG	6
00a2749d	7	/* Tegra20 Clock control functions */
b4ba2be8	8
150c2493	9	#include <common.h>
a7230745	10	#include <errno.h>
b4ba2be8	11	#include <asm/io.h>
b4ba2be8	12	#include <asm/arch/clock.h>
150c2493 TW	13	#include <asm/arch/tegra.h>
	14	#include <asm/arch-tegra/clk_rst.h>
	15	#include <asm/arch-tegra/timer.h>
4ed59e70	16	#include <div64.h>
ed297449	17	#include <fdtdec.h>
4ed59e70	18
4ed59e70	19	/*
00a2749d	20	* Clock types that we can use as a source. The Tegra20 has muxes for the
4ed59e70 SG	21	* peripheral clocks, and in most cases there are four options for the clock
	22	* source. This gives us a clock 'type' and exploits what commonality exists
	23	* in the device.
	24	*
	25	* Letters are obvious, except for T which means CLK_M, and S which means the
	26	* clock derived from 32KHz. Beware that CLK_M (also called OSC in the
	27	* datasheet) and PLL_M are different things. The former is the basic
	28	* clock supplied to the SOC from an external oscillator. The latter is the
	29	* memory clock PLL.
	30	*
	31	* See definitions in clock_id in the header file.
	32	*/
	33	enum clock_type_id {
	34	CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
	35	CLOCK_TYPE_MCPA, /* and so on */
	36	CLOCK_TYPE_MCPT,
	37	CLOCK_TYPE_PCM,
	38	CLOCK_TYPE_PCMT,
2e33559f	39	CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
4ed59e70 SG	40	CLOCK_TYPE_PCXTS,
	41	CLOCK_TYPE_PDCT,
	42
	43	CLOCK_TYPE_COUNT,
	44	CLOCK_TYPE_NONE = -1, /* invalid clock type */
	45	};
	46
4ed59e70 SG	47	enum {
	48	CLOCK_MAX_MUX = 4 /* number of source options for each clock */
	49	};
	50
	51	/*
	52	* Clock source mux for each clock type. This just converts our enum into
	53	* a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
	54	* is special as it has 5 sources. Since it also has a different number of
	55	* bits in its register for the source, we just handle it with a special
	56	* case in the code.
	57	*/
	58	#define CLK(x) CLOCK_ID_ ## x
	59	static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
	60	{ CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
	61	{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
	62	{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
	63	{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
	64	{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
2e33559f	65	{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
4ed59e70 SG	66	{ CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
	67	{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
	68	};
	69
	70	/*
	71	* Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
	72	* not in the header file since it is for purely internal use - we want
	73	* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
	74	* confusion bewteen PERIPH_ID_... and PERIPHC_...
	75	*
	76	* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
	77	* confusing.
	78	*
	79	* Note to SOC vendors: perhaps define a unified numbering for peripherals and
	80	* use it for reset, clock enable, clock source/divider and even pinmuxing
	81	* if you can.
	82	*/
	83	enum periphc_internal_id {
	84	/* 0x00 */
	85	PERIPHC_I2S1,
	86	PERIPHC_I2S2,
	87	PERIPHC_SPDIF_OUT,
	88	PERIPHC_SPDIF_IN,
	89	PERIPHC_PWM,
	90	PERIPHC_SPI1,
	91	PERIPHC_SPI2,
	92	PERIPHC_SPI3,
	93
	94	/* 0x08 */
	95	PERIPHC_XIO,
	96	PERIPHC_I2C1,
	97	PERIPHC_DVC_I2C,
	98	PERIPHC_TWC,
	99	PERIPHC_0c,
	100	PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
	101	PERIPHC_DISP1,
	102	PERIPHC_DISP2,
	103
	104	/* 0x10 */
	105	PERIPHC_CVE,
	106	PERIPHC_IDE0,
	107	PERIPHC_VI,
	108	PERIPHC_1c,
	109	PERIPHC_SDMMC1,
	110	PERIPHC_SDMMC2,
	111	PERIPHC_G3D,
	112	PERIPHC_G2D,
	113
	114	/* 0x18 */
	115	PERIPHC_NDFLASH,
	116	PERIPHC_SDMMC4,
	117	PERIPHC_VFIR,
	118	PERIPHC_EPP,
	119	PERIPHC_MPE,
	120	PERIPHC_MIPI,
	121	PERIPHC_UART1,
	122	PERIPHC_UART2,
	123
	124	/* 0x20 */
	125	PERIPHC_HOST1X,
	126	PERIPHC_21,
	127	PERIPHC_TVO,
	128	PERIPHC_HDMI,
	129	PERIPHC_24,
130	PERIPHC_TVDAC,
131	PERIPHC_I2C2,
132	PERIPHC_EMC,
133
134	/* 0x28 */
135	PERIPHC_UART3,
136	PERIPHC_29,
137	PERIPHC_VI_SENSOR,
138	PERIPHC_2b,
139	PERIPHC_2c,
140	PERIPHC_SPI4,
141	PERIPHC_I2C3,
142	PERIPHC_SDMMC3,
143
144	/* 0x30 */
145	PERIPHC_UART4,
146	PERIPHC_UART5,
147	PERIPHC_VDE,
148	PERIPHC_OWR,
149	PERIPHC_NOR,
150	PERIPHC_CSITE,
151
152	PERIPHC_COUNT,
153
154	PERIPHC_NONE = -1,
155	};
156
4ed59e70 SG	157	/*
	158	* Clock type for each peripheral clock source. We put the name in each
	159	* record just so it is easy to match things up
	160	*/
	161	#define TYPE(name, type) type
	162	static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
	163	/* 0x00 */
	164	TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
	165	TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
	166	TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
	167	TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
	168	TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
	169	TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
	170	TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
	171	TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
	172
	173	/* 0x08 */
	174	TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
2e33559f SG	175	TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
2e33559f SG	176	TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
4ed59e70 SG	177	TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
	178	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	179	TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
	180	TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
	181	TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
	182
	183	/* 0x10 */
	184	TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
	185	TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
	186	TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
	187	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	188	TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
	189	TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
	190	TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
	191	TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
	192
	193	/* 0x18 */
	194	TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
	195	TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
	196	TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
	197	TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
	198	TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
	199	TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
	200	TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
	201	TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
	202
	203	/* 0x20 */
	204	TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
	205	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	206	TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
	207	TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
	208	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	209	TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
2e33559f	210	TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
4ed59e70 SG	211	TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
	212
	213	/* 0x28 */
	214	TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
	215	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	216	TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
	217	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	218	TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
	219	TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
2e33559f	220	TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
4ed59e70 SG	221	TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
	222
	223	/* 0x30 */
	224	TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
	225	TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
	226	TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
	227	TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
	228	TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
	229	TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
	230	};
	231
	232	/*
	233	* This array translates a periph_id to a periphc_internal_id
	234	*
	235	* Not present/matched up:
	236	* uint vi_sensor; _VI_SENSOR_0, 0x1A8
	237	* SPDIF - which is both 0x08 and 0x0c
	238	*
	239	*/
	240	#define NONE(name) (-1)
	241	#define OFFSET(name, value) PERIPHC_ ## name
	242	static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
	243	/* Low word: 31:0 */
	244	NONE(CPU),
	245	NONE(RESERVED1),
	246	NONE(RESERVED2),
	247	NONE(AC97),
	248	NONE(RTC),
	249	NONE(TMR),
	250	PERIPHC_UART1,
	251	PERIPHC_UART2, /* and vfir 0x68 */
	252
	253	/* 0x08 */
	254	NONE(GPIO),
	255	PERIPHC_SDMMC2,
	256	NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
	257	PERIPHC_I2S1,
	258	PERIPHC_I2C1,
	259	PERIPHC_NDFLASH,
	260	PERIPHC_SDMMC1,
	261	PERIPHC_SDMMC4,
	262
	263	/* 0x10 */
	264	PERIPHC_TWC,
	265	PERIPHC_PWM,
	266	PERIPHC_I2S2,
	267	PERIPHC_EPP,
	268	PERIPHC_VI,
	269	PERIPHC_G2D,
	270	NONE(USBD),
	271	NONE(ISP),
	272
	273	/* 0x18 */
	274	PERIPHC_G3D,
	275	PERIPHC_IDE0,
	276	PERIPHC_DISP2,
	277	PERIPHC_DISP1,
	278	PERIPHC_HOST1X,
	279	NONE(VCP),
	280	NONE(RESERVED30),
	281	NONE(CACHE2),
	282
	283	/* Middle word: 63:32 */
	284	NONE(MEM),
285	NONE(AHBDMA),
286	NONE(APBDMA),
287	NONE(RESERVED35),
288	NONE(KBC),
289	NONE(STAT_MON),
290	NONE(PMC),
291	NONE(FUSE),
292
293	/* 0x28 */
294	NONE(KFUSE),
295	NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
296	PERIPHC_NOR,
297	PERIPHC_SPI1,
298	PERIPHC_SPI2,
299	PERIPHC_XIO,
300	PERIPHC_SPI3,
301	PERIPHC_DVC_I2C,
302
303	/* 0x30 */
304	NONE(DSI),
305	PERIPHC_TVO, /* also CVE 0x40 */
306	PERIPHC_MIPI,
307	PERIPHC_HDMI,
308	PERIPHC_CSITE,
309	PERIPHC_TVDAC,
310	PERIPHC_I2C2,
311	PERIPHC_UART3,
312
313	/* 0x38 */
314	NONE(RESERVED56),
315	PERIPHC_EMC,
316	NONE(USB2),
317	NONE(USB3),
318	PERIPHC_MPE,
319	PERIPHC_VDE,
320	NONE(BSEA),
321	NONE(BSEV),
322
323	/* Upper word 95:64 */
324	NONE(SPEEDO),
325	PERIPHC_UART4,
326	PERIPHC_UART5,
327	PERIPHC_I2C3,
328	PERIPHC_SPI4,
329	PERIPHC_SDMMC3,
330	NONE(PCIE),
331	PERIPHC_OWR,
332
333	/* 0x48 */
334	NONE(AFI),
335	NONE(CORESIGHT),
59cb3bf4	336	NONE(PCIEXCLK),
4ed59e70 SG	337	NONE(AVPUCQ),
	338	NONE(RESERVED76),
	339	NONE(RESERVED77),
	340	NONE(RESERVED78),
	341	NONE(RESERVED79),
	342
	343	/* 0x50 */
	344	NONE(RESERVED80),
	345	NONE(RESERVED81),
	346	NONE(RESERVED82),
	347	NONE(RESERVED83),
	348	NONE(IRAMA),
	349	NONE(IRAMB),
	350	NONE(IRAMC),
	351	NONE(IRAMD),
	352
	353	/* 0x58 */
	354	NONE(CRAM2),
	355	};
b4ba2be8	356
b4ba2be8 SG	357	/*
b4ba2be8 SG	358	* Get the oscillator frequency, from the corresponding hardware configuration
f29f086a	359	* field. T20 has 4 frequencies that it supports.
b4ba2be8 SG	360	*/
	361	enum clock_osc_freq clock_get_osc_freq(void)
	362	{
	363	struct clk_rst_ctlr *clkrst =
	364	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	365	u32 reg;
	366
	367	reg = readl(&clkrst->crc_osc_ctrl);
	368	return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
	369	}
	370
4ed59e70	371	/* Returns a pointer to the clock source register for a peripheral */
f29f086a	372	u32 *get_periph_source_reg(enum periph_id periph_id)
4ed59e70 SG	373	{
	374	struct clk_rst_ctlr *clkrst =
	375	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	376	enum periphc_internal_id internal_id;
	377
	378	assert(clock_periph_id_isvalid(periph_id));
	379	internal_id = periph_id_to_internal_id[periph_id];
	380	assert(internal_id != -1);
	381	return &clkrst->crc_clk_src[internal_id];
	382	}
	383
4ed59e70 SG	384	/**
	385	* Given a peripheral ID and the required source clock, this returns which
	386	* value should be programmed into the source mux for that peripheral.
	387	*
	388	* There is special code here to handle the one source type with 5 sources.
	389	*
	390	* @param periph_id peripheral to start
	391	* @param source PLL id of required parent clock
	392	* @param mux_bits Set to number of bits in mux register: 2 or 4
2e33559f	393	* @param divider_bits Set to number of divider bits (8 or 16)
4ed59e70 SG	394	* @return mux value (0-4, or -1 if not found)
4ed59e70 SG	395	*/
f29f086a	396	int get_periph_clock_source(enum periph_id periph_id,
2e33559f	397	enum clock_id parent, int mux_bits, int divider_bits)
4ed59e70 SG	398	{
	399	enum clock_type_id type;
	400	enum periphc_internal_id internal_id;
	401	int mux;
	402
	403	assert(clock_periph_id_isvalid(periph_id));
	404
	405	internal_id = periph_id_to_internal_id[periph_id];
	406	assert(periphc_internal_id_isvalid(internal_id));
	407
	408	type = clock_periph_type[internal_id];
	409	assert(clock_type_id_isvalid(type));
	410
2e33559f SG	411	/*
	412	* Special cases here for the clock with a 4-bit source mux and I2C
	413	* with its 16-bit divisor
	414	*/
4ed59e70	415	if (type == CLOCK_TYPE_PCXTS)
54d2e182	416	*mux_bits = MASK_BITS_31_28;
4ed59e70	417	else
54d2e182	418	*mux_bits = MASK_BITS_31_30;
2e33559f SG	419	if (type == CLOCK_TYPE_PCMT16)
	420	*divider_bits = 16;
	421	else
	422	*divider_bits = 8;
4ed59e70 SG	423
	424	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
	425	if (clock_source[type][mux] == parent)
	426	return mux;
	427
	428	/*
	429	* Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
	430	* which is not in our table. If not, then they are asking for a
	431	* source which this peripheral can't access through its mux.
	432	*/
	433	assert(type == CLOCK_TYPE_PCXTS);
	434	assert(parent == CLOCK_ID_SFROM32KHZ);
	435	if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
	436	return 4; /* mux value for this clock */
	437
	438	/* if we get here, either us or the caller has made a mistake */
	439	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
	440	parent);
	441	return -1;
	442	}
	443
b4ba2be8 SG	444	void clock_set_enable(enum periph_id periph_id, int enable)
	445	{
	446	struct clk_rst_ctlr *clkrst =
	447	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	448	u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
	449	u32 reg;
	450
	451	/* Enable/disable the clock to this peripheral */
	452	assert(clock_periph_id_isvalid(periph_id));
	453	reg = readl(clk);
	454	if (enable)
	455	reg \|= PERIPH_MASK(periph_id);
	456	else
	457	reg &= ~PERIPH_MASK(periph_id);
	458	writel(reg, clk);
	459	}
	460
b4ba2be8 SG	461	void reset_set_enable(enum periph_id periph_id, int enable)
	462	{
	463	struct clk_rst_ctlr *clkrst =
	464	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	465	u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
	466	u32 reg;
	467
	468	/* Enable/disable reset to the peripheral */
	469	assert(clock_periph_id_isvalid(periph_id));
	470	reg = readl(reset);
	471	if (enable)
	472	reg \|= PERIPH_MASK(periph_id);
	473	else
	474	reg &= ~PERIPH_MASK(periph_id);
	475	writel(reg, reset);
	476	}
	477
ed297449 SG	478	#ifdef CONFIG_OF_CONTROL
	479	/*
	480	* Convert a device tree clock ID to our peripheral ID. They are mostly
	481	* the same but we are very cautious so we check that a valid clock ID is
	482	* provided.
	483	*
00a2749d	484	* @param clk_id Clock ID according to tegra20 device tree binding
ed297449 SG	485	* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
ed297449 SG	486	*/
f29f086a	487	enum periph_id clk_id_to_periph_id(int clk_id)
ed297449	488	{
f29f086a	489	if (clk_id > PERIPH_ID_COUNT)
ed297449 SG	490	return PERIPH_ID_NONE;
	491
	492	switch (clk_id) {
f29f086a TW	493	case PERIPH_ID_RESERVED1:
	494	case PERIPH_ID_RESERVED2:
	495	case PERIPH_ID_RESERVED30:
	496	case PERIPH_ID_RESERVED35:
	497	case PERIPH_ID_RESERVED56:
59cb3bf4	498	case PERIPH_ID_PCIEXCLK:
f29f086a TW	499	case PERIPH_ID_RESERVED76:
	500	case PERIPH_ID_RESERVED77:
	501	case PERIPH_ID_RESERVED78:
	502	case PERIPH_ID_RESERVED79:
	503	case PERIPH_ID_RESERVED80:
	504	case PERIPH_ID_RESERVED81:
	505	case PERIPH_ID_RESERVED82:
	506	case PERIPH_ID_RESERVED83:
	507	case PERIPH_ID_RESERVED91:
ed297449 SG	508	return PERIPH_ID_NONE;
	509	default:
	510	return clk_id;
	511	}
	512	}
ed297449 SG	513	#endif /* CONFIG_OF_CONTROL */
ed297449 SG	514
4ed59e70 SG	515	void clock_early_init(void)
	516	{
	517	/*
	518	* PLLP output frequency set to 216MHz
	519	* PLLC output frequency set to 600Mhz
	520	*
	521	* TODO: Can we calculate these values instead of hard-coding?
	522	*/
	523	switch (clock_get_osc_freq()) {
	524	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
	525	clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
	526	clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
	527	break;
	528
	529	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
	530	clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
	531	clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
	532	break;
	533
b8cb5194 LS	534	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
	535	clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
	536	clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
	537	break;
4ed59e70 SG	538	case CLOCK_OSC_FREQ_19_2:
	539	default:
	540	/*
	541	* These are not supported. It is too early to print a
	542	* message and the UART likely won't work anyway due to the
	543	* oscillator being wrong.
	544	*/
	545	break;
	546	}
	547	}
b40f734a TW	548
	549	void arch_timer_init(void)
	550	{
	551	}
a7230745 TR	552
	553	#define PMC_SATA_PWRGT 0x1ac
	554	#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
	555	#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
	556
	557	#define PLLE_SS_CNTL 0x68
	558	#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
	559	#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
	560	#define PLLE_SS_CNTL_SSCBYP (1 << 12)
	561	#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
	562	#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
	563	#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
	564
	565	#define PLLE_BASE 0x0e8
	566	#define PLLE_BASE_ENABLE_CML (1 << 31)
	567	#define PLLE_BASE_ENABLE (1 << 30)
	568	#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
	569	#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
	570	#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
	571	#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
	572
	573	#define PLLE_MISC 0x0ec
	574	#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
	575	#define PLLE_MISC_PLL_READY (1 << 15)
	576	#define PLLE_MISC_LOCK (1 << 11)
	577	#define PLLE_MISC_LOCK_ENABLE (1 << 9)
	578	#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
	579
	580	static int tegra_plle_train(void)
	581	{
	582	unsigned int timeout = 2000;
	583	unsigned long value;
	584
	585	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	586	value \|= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
	587	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	588
	589	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	590	value \|= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
	591	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	592
	593	value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	594	value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
	595	writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
	596
	597	do {
	598	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
	599	if (value & PLLE_MISC_PLL_READY)
	600	break;
	601
	602	udelay(100);
	603	} while (--timeout);
	604
	605	if (timeout == 0) {
	606	error("timeout waiting for PLLE to become ready");
	607	return -ETIMEDOUT;
	608	}
	609
	610	return 0;
	611	}
	612
	613	int tegra_plle_enable(void)
	614	{
	615	unsigned int timeout = 1000;
616	u32 value;
617	int err;
618
619	/* disable PLLE clock */
620	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
621	value &= ~PLLE_BASE_ENABLE_CML;
622	value &= ~PLLE_BASE_ENABLE;
623	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
624
625	/* clear lock enable and setup field */
626	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
627	value &= ~PLLE_MISC_LOCK_ENABLE;
628	value &= ~PLLE_MISC_SETUP_BASE(0xffff);
629	value &= ~PLLE_MISC_SETUP_EXT(0x3);
630	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
631
632	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
633	if ((value & PLLE_MISC_PLL_READY) == 0) {
634	err = tegra_plle_train();
635	if (err < 0) {
636	error("failed to train PLLE: %d", err);
637	return err;
638	}
639	}
640
641	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
642	value \|= PLLE_MISC_SETUP_BASE(0x7);
643	value \|= PLLE_MISC_LOCK_ENABLE;
644	value \|= PLLE_MISC_SETUP_EXT(0);
645	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
646
647	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
648	value \|= PLLE_SS_CNTL_SSCBYP \| PLLE_SS_CNTL_INTERP_RESET \|
649	PLLE_SS_CNTL_BYPASS_SS;
650	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
651
652	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
653	value \|= PLLE_BASE_ENABLE_CML \| PLLE_BASE_ENABLE;
654	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
655
656	do {
657	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
658	if (value & PLLE_MISC_LOCK)
659	break;
660
661	udelay(2);
662	} while (--timeout);
663
664	if (timeout == 0) {
665	error("timeout waiting for PLLE to lock");
666	return -ETIMEDOUT;
667	}
668
669	udelay(50);
670
671	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
672	value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
673	value \|= PLLE_SS_CNTL_SSCINCINTRV(0x18);
674
675	value &= ~PLLE_SS_CNTL_SSCINC(0xff);
676	value \|= PLLE_SS_CNTL_SSCINC(0x01);
677
678	value &= ~PLLE_SS_CNTL_SSCBYP;
679	value &= ~PLLE_SS_CNTL_INTERP_RESET;
680	value &= ~PLLE_SS_CNTL_BYPASS_SS;
681
682	value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
683	value \|= PLLE_SS_CNTL_SSCMAX(0x24);
684	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
685
686	return 0;
687	}